CoCalc -- clc3c0qmd.h

GitHub Repository: PojavLauncherTeam/mesa
Path: blob/21.2-virgl/src/gallium/drivers/nouveau/nvc0/clc3c0qmd.h
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/*******************************************************************************
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    Copyright (c) 2001-2010 NVIDIA Corporation
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    Permission is hereby granted, free of charge, to any person obtaining a copy
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    of this software and associated documentation files (the "Software"), to
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    deal in the Software without restriction, including without limitation the
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    rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
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    sell copies of the Software, and to permit persons to whom the Software is
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    furnished to do so, subject to the following conditions:
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    The above copyright notice and this permission notice shall be
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    included in all copies or substantial portions of the Software.
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    THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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    IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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    FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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    THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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    LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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    FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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    DEALINGS IN THE SOFTWARE.
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*******************************************************************************/
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/* AUTO GENERATED FILE -- DO NOT EDIT */
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#ifndef __CLC3C0QMD_H__
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#define __CLC3C0QMD_H__
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/*
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** Queue Meta Data, Version 02_02
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 */
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// The below C preprocessor definitions describe "multi-word" structures, where
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// fields may have bit numbers beyond 32.  For example, MW(127:96) means
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// the field is in bits 0-31 of word number 3 of the structure.  The "MW(X:Y)"
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// syntax is to distinguish from similar "X:Y" single-word definitions: the
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// macros historically used for single-word definitions would fail with
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// multi-word definitions.
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//
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// See nvmisc.h:DRF_VAL_MW() in the source code of the kernel
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// interface layer of nvidia.ko for an example of how to manipulate
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// these MW(X:Y) definitions.
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#define NVC3C0_QMDV02_02_OUTER_PUT                                 MW(30:0)
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#define NVC3C0_QMDV02_02_OUTER_OVERFLOW                            MW(31:31)
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#define NVC3C0_QMDV02_02_OUTER_GET                                 MW(62:32)
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#define NVC3C0_QMDV02_02_OUTER_STICKY_OVERFLOW                     MW(63:63)
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#define NVC3C0_QMDV02_02_INNER_GET                                 MW(94:64)
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#define NVC3C0_QMDV02_02_INNER_OVERFLOW                            MW(95:95)
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#define NVC3C0_QMDV02_02_INNER_PUT                                 MW(126:96)
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#define NVC3C0_QMDV02_02_INNER_STICKY_OVERFLOW                     MW(127:127)
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#define NVC3C0_QMDV02_02_QMD_GROUP_ID                              MW(133:128)
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#define NVC3C0_QMDV02_02_SM_GLOBAL_CACHING_ENABLE                  MW(134:134)
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#define NVC3C0_QMDV02_02_RUN_CTA_IN_ONE_SM_PARTITION               MW(135:135)
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#define NVC3C0_QMDV02_02_RUN_CTA_IN_ONE_SM_PARTITION_FALSE         0x00000000
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#define NVC3C0_QMDV02_02_RUN_CTA_IN_ONE_SM_PARTITION_TRUE          0x00000001
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#define NVC3C0_QMDV02_02_IS_QUEUE                                  MW(136:136)
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#define NVC3C0_QMDV02_02_IS_QUEUE_FALSE                            0x00000000
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#define NVC3C0_QMDV02_02_IS_QUEUE_TRUE                             0x00000001
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#define NVC3C0_QMDV02_02_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST      MW(137:137)
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#define NVC3C0_QMDV02_02_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000
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#define NVC3C0_QMDV02_02_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001
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#define NVC3C0_QMDV02_02_SEMAPHORE_RELEASE_ENABLE0                 MW(138:138)
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#define NVC3C0_QMDV02_02_SEMAPHORE_RELEASE_ENABLE0_FALSE           0x00000000
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#define NVC3C0_QMDV02_02_SEMAPHORE_RELEASE_ENABLE0_TRUE            0x00000001
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#define NVC3C0_QMDV02_02_SEMAPHORE_RELEASE_ENABLE1                 MW(139:139)
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#define NVC3C0_QMDV02_02_SEMAPHORE_RELEASE_ENABLE1_FALSE           0x00000000
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#define NVC3C0_QMDV02_02_SEMAPHORE_RELEASE_ENABLE1_TRUE            0x00000001
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#define NVC3C0_QMDV02_02_REQUIRE_SCHEDULING_PCAS                   MW(140:140)
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#define NVC3C0_QMDV02_02_REQUIRE_SCHEDULING_PCAS_FALSE             0x00000000
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#define NVC3C0_QMDV02_02_REQUIRE_SCHEDULING_PCAS_TRUE              0x00000001
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#define NVC3C0_QMDV02_02_DEPENDENT_QMD_SCHEDULE_ENABLE             MW(141:141)
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#define NVC3C0_QMDV02_02_DEPENDENT_QMD_SCHEDULE_ENABLE_FALSE       0x00000000
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#define NVC3C0_QMDV02_02_DEPENDENT_QMD_SCHEDULE_ENABLE_TRUE        0x00000001
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#define NVC3C0_QMDV02_02_DEPENDENT_QMD_TYPE                        MW(142:142)
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#define NVC3C0_QMDV02_02_DEPENDENT_QMD_TYPE_QUEUE                  0x00000000
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#define NVC3C0_QMDV02_02_DEPENDENT_QMD_TYPE_GRID                   0x00000001
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#define NVC3C0_QMDV02_02_DEPENDENT_QMD_FIELD_COPY                  MW(143:143)
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#define NVC3C0_QMDV02_02_DEPENDENT_QMD_FIELD_COPY_FALSE            0x00000000
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#define NVC3C0_QMDV02_02_DEPENDENT_QMD_FIELD_COPY_TRUE             0x00000001
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#define NVC3C0_QMDV02_02_QMD_RESERVED_B                            MW(159:144)
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#define NVC3C0_QMDV02_02_CIRCULAR_QUEUE_SIZE                       MW(184:160)
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#define NVC3C0_QMDV02_02_QMD_RESERVED_C                            MW(185:185)
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#define NVC3C0_QMDV02_02_INVALIDATE_TEXTURE_HEADER_CACHE           MW(186:186)
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#define NVC3C0_QMDV02_02_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE     0x00000000
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#define NVC3C0_QMDV02_02_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE      0x00000001
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#define NVC3C0_QMDV02_02_INVALIDATE_TEXTURE_SAMPLER_CACHE          MW(187:187)
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#define NVC3C0_QMDV02_02_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE    0x00000000
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#define NVC3C0_QMDV02_02_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE     0x00000001
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#define NVC3C0_QMDV02_02_INVALIDATE_TEXTURE_DATA_CACHE             MW(188:188)
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#define NVC3C0_QMDV02_02_INVALIDATE_TEXTURE_DATA_CACHE_FALSE       0x00000000
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#define NVC3C0_QMDV02_02_INVALIDATE_TEXTURE_DATA_CACHE_TRUE        0x00000001
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#define NVC3C0_QMDV02_02_INVALIDATE_SHADER_DATA_CACHE              MW(189:189)
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#define NVC3C0_QMDV02_02_INVALIDATE_SHADER_DATA_CACHE_FALSE        0x00000000
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#define NVC3C0_QMDV02_02_INVALIDATE_SHADER_DATA_CACHE_TRUE         0x00000001
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#define NVC3C0_QMDV02_02_INVALIDATE_INSTRUCTION_CACHE              MW(190:190)
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#define NVC3C0_QMDV02_02_INVALIDATE_INSTRUCTION_CACHE_FALSE        0x00000000
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#define NVC3C0_QMDV02_02_INVALIDATE_INSTRUCTION_CACHE_TRUE         0x00000001
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#define NVC3C0_QMDV02_02_INVALIDATE_SHADER_CONSTANT_CACHE          MW(191:191)
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#define NVC3C0_QMDV02_02_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE    0x00000000
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#define NVC3C0_QMDV02_02_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE     0x00000001
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#define NVC3C0_QMDV02_02_CTA_RASTER_WIDTH_RESUME                   MW(223:192)
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#define NVC3C0_QMDV02_02_CTA_RASTER_HEIGHT_RESUME                  MW(239:224)
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#define NVC3C0_QMDV02_02_CTA_RASTER_DEPTH_RESUME                   MW(255:240)
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#define NVC3C0_QMDV02_02_PROGRAM_OFFSET                            MW(287:256)
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#define NVC3C0_QMDV02_02_CIRCULAR_QUEUE_ADDR_LOWER                 MW(319:288)
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#define NVC3C0_QMDV02_02_CIRCULAR_QUEUE_ADDR_UPPER                 MW(327:320)
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#define NVC3C0_QMDV02_02_QMD_RESERVED_D                            MW(335:328)
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#define NVC3C0_QMDV02_02_CIRCULAR_QUEUE_ENTRY_SIZE                 MW(351:336)
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#define NVC3C0_QMDV02_02_CWD_REFERENCE_COUNT_ID                    MW(357:352)
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#define NVC3C0_QMDV02_02_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE       MW(365:358)
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#define NVC3C0_QMDV02_02_RELEASE_MEMBAR_TYPE                       MW(366:366)
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#define NVC3C0_QMDV02_02_RELEASE_MEMBAR_TYPE_FE_NONE               0x00000000
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#define NVC3C0_QMDV02_02_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR          0x00000001
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#define NVC3C0_QMDV02_02_CWD_REFERENCE_COUNT_INCR_ENABLE           MW(367:367)
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#define NVC3C0_QMDV02_02_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE     0x00000000
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#define NVC3C0_QMDV02_02_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE      0x00000001
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#define NVC3C0_QMDV02_02_CWD_MEMBAR_TYPE                           MW(369:368)
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#define NVC3C0_QMDV02_02_CWD_MEMBAR_TYPE_L1_NONE                   0x00000000
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#define NVC3C0_QMDV02_02_CWD_MEMBAR_TYPE_L1_SYSMEMBAR              0x00000001
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#define NVC3C0_QMDV02_02_CWD_MEMBAR_TYPE_L1_MEMBAR                 0x00000003
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#define NVC3C0_QMDV02_02_SEQUENTIALLY_RUN_CTAS                     MW(370:370)
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#define NVC3C0_QMDV02_02_SEQUENTIALLY_RUN_CTAS_FALSE               0x00000000
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#define NVC3C0_QMDV02_02_SEQUENTIALLY_RUN_CTAS_TRUE                0x00000001
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#define NVC3C0_QMDV02_02_CWD_REFERENCE_COUNT_DECR_ENABLE           MW(371:371)
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#define NVC3C0_QMDV02_02_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE     0x00000000
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#define NVC3C0_QMDV02_02_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE      0x00000001
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#define NVC3C0_QMDV02_02_API_VISIBLE_CALL_LIMIT                    MW(378:378)
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#define NVC3C0_QMDV02_02_API_VISIBLE_CALL_LIMIT__32                0x00000000
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#define NVC3C0_QMDV02_02_API_VISIBLE_CALL_LIMIT_NO_CHECK           0x00000001
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#define NVC3C0_QMDV02_02_SAMPLER_INDEX                             MW(382:382)
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#define NVC3C0_QMDV02_02_SAMPLER_INDEX_INDEPENDENTLY               0x00000000
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#define NVC3C0_QMDV02_02_SAMPLER_INDEX_VIA_HEADER_INDEX            0x00000001
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#define NVC3C0_QMDV02_02_CTA_RASTER_WIDTH                          MW(415:384)
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#define NVC3C0_QMDV02_02_CTA_RASTER_HEIGHT                         MW(431:416)
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#define NVC3C0_QMDV02_02_QMD_RESERVED13A                           MW(447:432)
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#define NVC3C0_QMDV02_02_CTA_RASTER_DEPTH                          MW(463:448)
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#define NVC3C0_QMDV02_02_QMD_RESERVED14A                           MW(479:464)
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#define NVC3C0_QMDV02_02_DEPENDENT_QMD_POINTER                     MW(511:480)
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#define NVC3C0_QMDV02_02_QUEUE_ENTRIES_PER_CTA_MINUS_ONE           MW(518:512)
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#define NVC3C0_QMDV02_02_COALESCE_WAITING_PERIOD                   MW(529:522)
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#define NVC3C0_QMDV02_02_SHARED_MEMORY_SIZE                        MW(561:544)
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#define NVC3C0_QMDV02_02_MIN_SM_CONFIG_SHARED_MEM_SIZE             MW(568:562)
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#define NVC3C0_QMDV02_02_MAX_SM_CONFIG_SHARED_MEM_SIZE             MW(575:569)
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#define NVC3C0_QMDV02_02_QMD_VERSION                               MW(579:576)
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#define NVC3C0_QMDV02_02_QMD_MAJOR_VERSION                         MW(583:580)
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#define NVC3C0_QMDV02_02_QMD_RESERVED_H                            MW(591:584)
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#define NVC3C0_QMDV02_02_CTA_THREAD_DIMENSION0                     MW(607:592)
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#define NVC3C0_QMDV02_02_CTA_THREAD_DIMENSION1                     MW(623:608)
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#define NVC3C0_QMDV02_02_CTA_THREAD_DIMENSION2                     MW(639:624)
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#define NVC3C0_QMDV02_02_CONSTANT_BUFFER_VALID(i)                  MW((640+(i)*1):(640+(i)*1))
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#define NVC3C0_QMDV02_02_CONSTANT_BUFFER_VALID_FALSE               0x00000000
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#define NVC3C0_QMDV02_02_CONSTANT_BUFFER_VALID_TRUE                0x00000001
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#define NVC3C0_QMDV02_02_REGISTER_COUNT_V                          MW(656:648)
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#define NVC3C0_QMDV02_02_TARGET_SM_CONFIG_SHARED_MEM_SIZE          MW(663:657)
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#define NVC3C0_QMDV02_02_FREE_CTA_SLOTS_EMPTY_SM                   MW(671:664)
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#define NVC3C0_QMDV02_02_SM_DISABLE_MASK_LOWER                     MW(703:672)
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#define NVC3C0_QMDV02_02_SM_DISABLE_MASK_UPPER                     MW(735:704)
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#define NVC3C0_QMDV02_02_RELEASE0_ADDRESS_LOWER                    MW(767:736)
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#define NVC3C0_QMDV02_02_RELEASE0_ADDRESS_UPPER                    MW(775:768)
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#define NVC3C0_QMDV02_02_QMD_RESERVED_J                            MW(783:776)
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#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_OP                     MW(790:788)
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#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_OP_RED_ADD             0x00000000
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#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_OP_RED_MIN             0x00000001
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#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_OP_RED_MAX             0x00000002
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#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_OP_RED_INC             0x00000003
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#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_OP_RED_DEC             0x00000004
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#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_OP_RED_AND             0x00000005
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#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_OP_RED_OR              0x00000006
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#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_OP_RED_XOR             0x00000007
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#define NVC3C0_QMDV02_02_QMD_RESERVED_K                            MW(791:791)
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#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_FORMAT                 MW(793:792)
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#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32     0x00000000
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#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_FORMAT_SIGNED_32       0x00000001
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#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_ENABLE                 MW(794:794)
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#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_ENABLE_FALSE           0x00000000
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#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_ENABLE_TRUE            0x00000001
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#define NVC3C0_QMDV02_02_RELEASE0_STRUCTURE_SIZE                   MW(799:799)
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#define NVC3C0_QMDV02_02_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS        0x00000000
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#define NVC3C0_QMDV02_02_RELEASE0_STRUCTURE_SIZE_ONE_WORD          0x00000001
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#define NVC3C0_QMDV02_02_RELEASE0_PAYLOAD                          MW(831:800)
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#define NVC3C0_QMDV02_02_RELEASE1_ADDRESS_LOWER                    MW(863:832)
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#define NVC3C0_QMDV02_02_RELEASE1_ADDRESS_UPPER                    MW(871:864)
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#define NVC3C0_QMDV02_02_QMD_RESERVED_L                            MW(879:872)
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#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_OP                     MW(886:884)
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#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_OP_RED_ADD             0x00000000
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#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_OP_RED_MIN             0x00000001
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#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_OP_RED_MAX             0x00000002
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#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_OP_RED_INC             0x00000003
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#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_OP_RED_DEC             0x00000004
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#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_OP_RED_AND             0x00000005
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#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_OP_RED_OR              0x00000006
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#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_OP_RED_XOR             0x00000007
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#define NVC3C0_QMDV02_02_QMD_RESERVED_M                            MW(887:887)
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#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_FORMAT                 MW(889:888)
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#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32     0x00000000
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#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_FORMAT_SIGNED_32       0x00000001
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#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_ENABLE                 MW(890:890)
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#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_ENABLE_FALSE           0x00000000
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#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_ENABLE_TRUE            0x00000001
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#define NVC3C0_QMDV02_02_RELEASE1_STRUCTURE_SIZE                   MW(895:895)
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#define NVC3C0_QMDV02_02_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS        0x00000000
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#define NVC3C0_QMDV02_02_RELEASE1_STRUCTURE_SIZE_ONE_WORD          0x00000001
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#define NVC3C0_QMDV02_02_RELEASE1_PAYLOAD                          MW(927:896)
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#define NVC3C0_QMDV02_02_SHADER_LOCAL_MEMORY_LOW_SIZE              MW(951:928)
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#define NVC3C0_QMDV02_02_QMD_RESERVED_N                            MW(954:952)
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#define NVC3C0_QMDV02_02_BARRIER_COUNT                             MW(959:955)
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#define NVC3C0_QMDV02_02_SHADER_LOCAL_MEMORY_HIGH_SIZE             MW(983:960)
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#define NVC3C0_QMDV02_02_REGISTER_COUNT                            MW(991:984)
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#define NVC3C0_QMDV02_02_SHADER_LOCAL_MEMORY_CRS_SIZE              MW(1015:992)
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#define NVC3C0_QMDV02_02_SASS_VERSION                              MW(1023:1016)
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#define NVC3C0_QMDV02_02_CONSTANT_BUFFER_ADDR_LOWER(i)             MW((1055+(i)*64):(1024+(i)*64))
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#define NVC3C0_QMDV02_02_CONSTANT_BUFFER_ADDR_UPPER(i)             MW((1072+(i)*64):(1056+(i)*64))
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#define NVC3C0_QMDV02_02_CONSTANT_BUFFER_RESERVED_ADDR(i)          MW((1073+(i)*64):(1073+(i)*64))
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#define NVC3C0_QMDV02_02_CONSTANT_BUFFER_INVALIDATE(i)             MW((1074+(i)*64):(1074+(i)*64))
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#define NVC3C0_QMDV02_02_CONSTANT_BUFFER_INVALIDATE_FALSE          0x00000000
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#define NVC3C0_QMDV02_02_CONSTANT_BUFFER_INVALIDATE_TRUE           0x00000001
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#define NVC3C0_QMDV02_02_CONSTANT_BUFFER_SIZE_SHIFTED4(i)          MW((1087+(i)*64):(1075+(i)*64))
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#define NVC3C0_QMDV02_02_PROGRAM_ADDRESS_LOWER                     MW(1567:1536)
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#define NVC3C0_QMDV02_02_PROGRAM_ADDRESS_UPPER                     MW(1584:1568)
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#define NVC3C0_QMDV02_02_QMD_RESERVED_S                            MW(1599:1585)
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#define NVC3C0_QMDV02_02_HW_ONLY_INNER_GET                         MW(1630:1600)
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#define NVC3C0_QMDV02_02_HW_ONLY_REQUIRE_SCHEDULING_PCAS           MW(1631:1631)
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#define NVC3C0_QMDV02_02_HW_ONLY_INNER_PUT                         MW(1662:1632)
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#define NVC3C0_QMDV02_02_HW_ONLY_SCG_TYPE                          MW(1663:1663)
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#define NVC3C0_QMDV02_02_HW_ONLY_SPAN_LIST_HEAD_INDEX              MW(1693:1664)
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#define NVC3C0_QMDV02_02_QMD_RESERVED_Q                            MW(1694:1694)
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#define NVC3C0_QMDV02_02_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID        MW(1695:1695)
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#define NVC3C0_QMDV02_02_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE  0x00000000
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#define NVC3C0_QMDV02_02_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE   0x00000001
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#define NVC3C0_QMDV02_02_HW_ONLY_SKED_NEXT_QMD_POINTER             MW(1727:1696)
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#define NVC3C0_QMDV02_02_QMD_SPARE_G                               MW(1759:1728)
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#define NVC3C0_QMDV02_02_QMD_SPARE_H                               MW(1791:1760)
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#define NVC3C0_QMDV02_02_QMD_SPARE_I                               MW(1823:1792)
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#define NVC3C0_QMDV02_02_QMD_SPARE_J                               MW(1855:1824)
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#define NVC3C0_QMDV02_02_QMD_SPARE_K                               MW(1887:1856)
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#define NVC3C0_QMDV02_02_QMD_SPARE_L                               MW(1919:1888)
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#define NVC3C0_QMDV02_02_QMD_SPARE_M                               MW(1951:1920)
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#define NVC3C0_QMDV02_02_QMD_SPARE_N                               MW(1983:1952)
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#define NVC3C0_QMDV02_02_DEBUG_ID_UPPER                            MW(2015:1984)
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#define NVC3C0_QMDV02_02_DEBUG_ID_LOWER                            MW(2047:2016)
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#endif // #ifndef __CLC3C0QMD_H__
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