Path: blob/21.2-virgl/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h
4574 views
#ifndef __NVC0_SCREEN_H__1#define __NVC0_SCREEN_H__23#include "nouveau_screen.h"4#include "nouveau_mm.h"5#include "nouveau_fence.h"6#include "nouveau_heap.h"78#include "nv_object.xml.h"910#include "nvc0/nvc0_winsys.h"11#include "nvc0/nvc0_stateobj.h"1213#define NVC0_TIC_MAX_ENTRIES 204814#define NVC0_TSC_MAX_ENTRIES 204815#define NVE4_IMG_MAX_HANDLES 5121617/* doesn't count driver-reserved slot */18#define NVC0_MAX_PIPE_CONSTBUFS 1519#define NVC0_MAX_CONST_BUFFERS 1620#define NVC0_MAX_CONSTBUF_SIZE 655362122#define NVC0_MAX_SURFACE_SLOTS 162324#define NVC0_MAX_VIEWPORTS 162526#define NVC0_MAX_BUFFERS 322728#define NVC0_MAX_IMAGES 82930#define NVC0_MAX_WINDOW_RECTANGLES 83132struct nvc0_context;3334struct nvc0_blitter;3536struct nvc0_graph_state {37bool flushed;38bool rasterizer_discard;39bool early_z_forced;40bool prim_restart;41uint32_t instance_elts; /* bitmask of per-instance elements */42uint32_t instance_base;43uint32_t constant_vbos;44uint32_t constant_elts;45int32_t index_bias;46uint16_t scissor;47bool flatshade;48uint8_t patch_vertices;49uint8_t vbo_mode; /* 0 = normal, 1 = translate, 3 = translate, forced */50uint8_t num_vtxbufs;51uint8_t num_vtxelts;52uint8_t num_textures[6];53uint8_t num_samplers[6];54uint8_t tls_required; /* bitmask of shader types using l[] */55uint8_t clip_enable;56uint32_t clip_mode;57bool uniform_buffer_bound[6];58struct nvc0_transform_feedback_state *tfb;59bool seamless_cube_map;60bool post_depth_coverage;61};6263struct nvc0_cb_binding {64uint64_t addr;65int size;66};6768struct nvc0_screen {69struct nouveau_screen base;7071struct nvc0_context *cur_ctx;72struct nvc0_graph_state save_state;7374int num_occlusion_queries_active;7576struct nouveau_bo *text;77struct nouveau_bo *uniform_bo;78struct nouveau_bo *tls;79struct nouveau_bo *txc; /* TIC (offset 0) and TSC (65536) */80struct nouveau_bo *poly_cache;8182uint8_t gpc_count;83uint16_t mp_count;84uint16_t mp_count_compute; /* magic reg can make compute use fewer MPs */8586struct nouveau_heap *text_heap;87struct nouveau_heap *lib_code; /* allocated from text_heap */8889struct nvc0_blitter *blitter;9091struct {92void **entries;93int next;94uint32_t lock[NVC0_TIC_MAX_ENTRIES / 32];95bool maxwell;96} tic;9798struct {99void **entries;100int next;101uint32_t lock[NVC0_TSC_MAX_ENTRIES / 32];102} tsc;103104struct {105struct pipe_image_view **entries;106int next;107} img;108109struct {110struct nouveau_bo *bo;111uint32_t *map;112} fence;113114struct {115struct nvc0_program *prog; /* compute state object to read MP counters */116struct nvc0_hw_sm_query *mp_counter[8]; /* counter to query allocation */117uint8_t num_hw_sm_active[2];118bool mp_counters_enabled;119} pm;120121/* only maintained on Maxwell+ */122struct nvc0_cb_binding cb_bindings[5][NVC0_MAX_CONST_BUFFERS];123124struct nouveau_object *eng3d; /* sqrt(1/2)|kepler> + sqrt(1/2)|fermi> */125struct nouveau_object *eng2d;126struct nouveau_object *m2mf;127struct nouveau_object *compute;128struct nouveau_object *nvsw;129};130131static inline struct nvc0_screen *132nvc0_screen(struct pipe_screen *screen)133{134return (struct nvc0_screen *)screen;135}136137int nvc0_screen_get_driver_query_info(struct pipe_screen *, unsigned,138struct pipe_driver_query_info *);139140int nvc0_screen_get_driver_query_group_info(struct pipe_screen *, unsigned,141struct pipe_driver_query_group_info *);142143bool nvc0_blitter_create(struct nvc0_screen *);144void nvc0_blitter_destroy(struct nvc0_screen *);145146void nvc0_screen_make_buffers_resident(struct nvc0_screen *);147148int nvc0_screen_tic_alloc(struct nvc0_screen *, void *);149int nvc0_screen_tsc_alloc(struct nvc0_screen *, void *);150151int nve4_screen_compute_setup(struct nvc0_screen *, struct nouveau_pushbuf *);152int nvc0_screen_compute_setup(struct nvc0_screen *, struct nouveau_pushbuf *);153154int nvc0_screen_resize_text_area(struct nvc0_screen *, uint64_t);155156// 3D Only157void nvc0_screen_bind_cb_3d(struct nvc0_screen *, bool *, int, int, int, uint64_t);158159static inline void160nvc0_resource_fence(struct nv04_resource *res, uint32_t flags)161{162struct nvc0_screen *screen = nvc0_screen(res->base.screen);163164if (res->mm) {165nouveau_fence_ref(screen->base.fence.current, &res->fence);166if (flags & NOUVEAU_BO_WR)167nouveau_fence_ref(screen->base.fence.current, &res->fence_wr);168}169}170171static inline void172nvc0_resource_validate(struct nv04_resource *res, uint32_t flags)173{174if (likely(res->bo)) {175if (flags & NOUVEAU_BO_WR)176res->status |= NOUVEAU_BUFFER_STATUS_GPU_WRITING |177NOUVEAU_BUFFER_STATUS_DIRTY;178if (flags & NOUVEAU_BO_RD)179res->status |= NOUVEAU_BUFFER_STATUS_GPU_READING;180181nvc0_resource_fence(res, flags);182}183}184185struct nvc0_format {186uint32_t rt;187struct {188unsigned format:7;189unsigned type_r:3;190unsigned type_g:3;191unsigned type_b:3;192unsigned type_a:3;193unsigned src_x:3;194unsigned src_y:3;195unsigned src_z:3;196unsigned src_w:3;197} tic;198uint32_t usage;199};200201struct nvc0_vertex_format {202uint32_t vtx;203uint32_t usage;204};205206extern const struct nvc0_format nvc0_format_table[];207extern const struct nvc0_vertex_format nvc0_vertex_format[];208209static inline void210nvc0_screen_tic_unlock(struct nvc0_screen *screen, struct nv50_tic_entry *tic)211{212if (tic->bindless)213return;214if (tic->id >= 0)215screen->tic.lock[tic->id / 32] &= ~(1 << (tic->id % 32));216}217218static inline void219nvc0_screen_tsc_unlock(struct nvc0_screen *screen, struct nv50_tsc_entry *tsc)220{221if (tsc->id >= 0)222screen->tsc.lock[tsc->id / 32] &= ~(1 << (tsc->id % 32));223}224225static inline void226nvc0_screen_tic_free(struct nvc0_screen *screen, struct nv50_tic_entry *tic)227{228if (tic->id >= 0) {229screen->tic.entries[tic->id] = NULL;230screen->tic.lock[tic->id / 32] &= ~(1 << (tic->id % 32));231}232}233234static inline void235nvc0_screen_tsc_free(struct nvc0_screen *screen, struct nv50_tsc_entry *tsc)236{237if (tsc->id >= 0) {238screen->tsc.entries[tsc->id] = NULL;239screen->tsc.lock[tsc->id / 32] &= ~(1 << (tsc->id % 32));240}241}242243#endif244245246