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PojavLauncherTeam
GitHub Repository: PojavLauncherTeam/mesa
Path: blob/21.2-virgl/src/gallium/drivers/nouveau/nvc0/nvc0_state.c
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/*
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* Copyright 2010 Christoph Bumiller
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "pipe/p_defines.h"
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#include "util/u_framebuffer.h"
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#include "util/u_helpers.h"
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#include "util/u_inlines.h"
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#include "util/u_transfer.h"
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#include "tgsi/tgsi_parse.h"
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#include "compiler/nir/nir.h"
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#include "compiler/nir/nir_serialize.h"
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#include "nvc0/nvc0_stateobj.h"
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#include "nvc0/nvc0_context.h"
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#include "nvc0/nvc0_query_hw.h"
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#include "nvc0/nvc0_3d.xml.h"
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#include "nouveau_gldefs.h"
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static inline uint32_t
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nvc0_colormask(unsigned mask)
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{
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uint32_t ret = 0;
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if (mask & PIPE_MASK_R)
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ret |= 0x0001;
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if (mask & PIPE_MASK_G)
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ret |= 0x0010;
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if (mask & PIPE_MASK_B)
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ret |= 0x0100;
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if (mask & PIPE_MASK_A)
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ret |= 0x1000;
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return ret;
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}
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#define NVC0_BLEND_FACTOR_CASE(a, b) \
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case PIPE_BLENDFACTOR_##a: return NV50_BLEND_FACTOR_##b
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static inline uint32_t
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nvc0_blend_fac(unsigned factor)
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{
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switch (factor) {
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NVC0_BLEND_FACTOR_CASE(ONE, ONE);
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NVC0_BLEND_FACTOR_CASE(SRC_COLOR, SRC_COLOR);
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NVC0_BLEND_FACTOR_CASE(SRC_ALPHA, SRC_ALPHA);
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NVC0_BLEND_FACTOR_CASE(DST_ALPHA, DST_ALPHA);
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NVC0_BLEND_FACTOR_CASE(DST_COLOR, DST_COLOR);
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NVC0_BLEND_FACTOR_CASE(SRC_ALPHA_SATURATE, SRC_ALPHA_SATURATE);
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NVC0_BLEND_FACTOR_CASE(CONST_COLOR, CONSTANT_COLOR);
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NVC0_BLEND_FACTOR_CASE(CONST_ALPHA, CONSTANT_ALPHA);
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NVC0_BLEND_FACTOR_CASE(SRC1_COLOR, SRC1_COLOR);
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NVC0_BLEND_FACTOR_CASE(SRC1_ALPHA, SRC1_ALPHA);
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NVC0_BLEND_FACTOR_CASE(ZERO, ZERO);
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NVC0_BLEND_FACTOR_CASE(INV_SRC_COLOR, ONE_MINUS_SRC_COLOR);
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NVC0_BLEND_FACTOR_CASE(INV_SRC_ALPHA, ONE_MINUS_SRC_ALPHA);
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NVC0_BLEND_FACTOR_CASE(INV_DST_ALPHA, ONE_MINUS_DST_ALPHA);
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NVC0_BLEND_FACTOR_CASE(INV_DST_COLOR, ONE_MINUS_DST_COLOR);
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NVC0_BLEND_FACTOR_CASE(INV_CONST_COLOR, ONE_MINUS_CONSTANT_COLOR);
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NVC0_BLEND_FACTOR_CASE(INV_CONST_ALPHA, ONE_MINUS_CONSTANT_ALPHA);
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NVC0_BLEND_FACTOR_CASE(INV_SRC1_COLOR, ONE_MINUS_SRC1_COLOR);
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NVC0_BLEND_FACTOR_CASE(INV_SRC1_ALPHA, ONE_MINUS_SRC1_ALPHA);
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default:
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return NV50_BLEND_FACTOR_ZERO;
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}
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}
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static void *
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nvc0_blend_state_create(struct pipe_context *pipe,
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const struct pipe_blend_state *cso)
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{
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struct nvc0_blend_stateobj *so = CALLOC_STRUCT(nvc0_blend_stateobj);
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int i;
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int r; /* reference */
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uint32_t ms;
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uint8_t blend_en = 0;
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bool indep_masks = false;
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bool indep_funcs = false;
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so->pipe = *cso;
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/* check which states actually have differing values */
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if (cso->independent_blend_enable) {
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for (r = 0; r < 8 && !cso->rt[r].blend_enable; ++r);
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blend_en |= 1 << r;
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for (i = r + 1; i < 8; ++i) {
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if (!cso->rt[i].blend_enable)
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continue;
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blend_en |= 1 << i;
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if (cso->rt[i].rgb_func != cso->rt[r].rgb_func ||
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cso->rt[i].rgb_src_factor != cso->rt[r].rgb_src_factor ||
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cso->rt[i].rgb_dst_factor != cso->rt[r].rgb_dst_factor ||
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cso->rt[i].alpha_func != cso->rt[r].alpha_func ||
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cso->rt[i].alpha_src_factor != cso->rt[r].alpha_src_factor ||
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cso->rt[i].alpha_dst_factor != cso->rt[r].alpha_dst_factor) {
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indep_funcs = true;
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break;
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}
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}
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for (; i < 8; ++i)
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blend_en |= (cso->rt[i].blend_enable ? 1 : 0) << i;
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for (i = 1; i < 8; ++i) {
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if (cso->rt[i].colormask != cso->rt[0].colormask) {
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indep_masks = true;
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break;
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}
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}
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} else {
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r = 0;
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if (cso->rt[0].blend_enable)
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blend_en = 0xff;
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}
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if (cso->logicop_enable) {
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SB_BEGIN_3D(so, LOGIC_OP_ENABLE, 2);
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SB_DATA (so, 1);
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SB_DATA (so, nvgl_logicop_func(cso->logicop_func));
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SB_IMMED_3D(so, MACRO_BLEND_ENABLES, 0);
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} else {
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SB_IMMED_3D(so, LOGIC_OP_ENABLE, 0);
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SB_IMMED_3D(so, BLEND_INDEPENDENT, indep_funcs);
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SB_IMMED_3D(so, MACRO_BLEND_ENABLES, blend_en);
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if (indep_funcs) {
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for (i = 0; i < 8; ++i) {
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if (cso->rt[i].blend_enable) {
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SB_BEGIN_3D(so, IBLEND_EQUATION_RGB(i), 6);
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SB_DATA (so, nvgl_blend_eqn(cso->rt[i].rgb_func));
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SB_DATA (so, nvc0_blend_fac(cso->rt[i].rgb_src_factor));
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SB_DATA (so, nvc0_blend_fac(cso->rt[i].rgb_dst_factor));
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SB_DATA (so, nvgl_blend_eqn(cso->rt[i].alpha_func));
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SB_DATA (so, nvc0_blend_fac(cso->rt[i].alpha_src_factor));
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SB_DATA (so, nvc0_blend_fac(cso->rt[i].alpha_dst_factor));
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}
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}
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} else
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if (blend_en) {
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SB_BEGIN_3D(so, BLEND_EQUATION_RGB, 5);
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SB_DATA (so, nvgl_blend_eqn(cso->rt[r].rgb_func));
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SB_DATA (so, nvc0_blend_fac(cso->rt[r].rgb_src_factor));
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SB_DATA (so, nvc0_blend_fac(cso->rt[r].rgb_dst_factor));
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SB_DATA (so, nvgl_blend_eqn(cso->rt[r].alpha_func));
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SB_DATA (so, nvc0_blend_fac(cso->rt[r].alpha_src_factor));
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SB_BEGIN_3D(so, BLEND_FUNC_DST_ALPHA, 1);
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SB_DATA (so, nvc0_blend_fac(cso->rt[r].alpha_dst_factor));
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}
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SB_IMMED_3D(so, COLOR_MASK_COMMON, !indep_masks);
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if (indep_masks) {
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SB_BEGIN_3D(so, COLOR_MASK(0), 8);
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for (i = 0; i < 8; ++i)
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SB_DATA(so, nvc0_colormask(cso->rt[i].colormask));
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} else {
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SB_BEGIN_3D(so, COLOR_MASK(0), 1);
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SB_DATA (so, nvc0_colormask(cso->rt[0].colormask));
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}
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}
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ms = 0;
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if (cso->alpha_to_coverage)
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ms |= NVC0_3D_MULTISAMPLE_CTRL_ALPHA_TO_COVERAGE;
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if (cso->alpha_to_one)
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ms |= NVC0_3D_MULTISAMPLE_CTRL_ALPHA_TO_ONE;
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SB_BEGIN_3D(so, MULTISAMPLE_CTRL, 1);
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SB_DATA (so, ms);
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assert(so->size <= ARRAY_SIZE(so->state));
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return so;
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}
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static void
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nvc0_blend_state_bind(struct pipe_context *pipe, void *hwcso)
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{
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struct nvc0_context *nvc0 = nvc0_context(pipe);
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nvc0->blend = hwcso;
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nvc0->dirty_3d |= NVC0_NEW_3D_BLEND;
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}
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static void
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nvc0_blend_state_delete(struct pipe_context *pipe, void *hwcso)
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{
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FREE(hwcso);
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}
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/* NOTE: ignoring line_last_pixel */
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static void *
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nvc0_rasterizer_state_create(struct pipe_context *pipe,
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const struct pipe_rasterizer_state *cso)
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{
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struct nvc0_rasterizer_stateobj *so;
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uint16_t class_3d = nouveau_screen(pipe->screen)->class_3d;
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uint32_t reg;
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so = CALLOC_STRUCT(nvc0_rasterizer_stateobj);
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if (!so)
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return NULL;
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so->pipe = *cso;
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/* Scissor enables are handled in scissor state, we will not want to
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* always emit 16 commands, one for each scissor rectangle, here.
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*/
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SB_IMMED_3D(so, PROVOKING_VERTEX_LAST, !cso->flatshade_first);
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SB_IMMED_3D(so, VERTEX_TWO_SIDE_ENABLE, cso->light_twoside);
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SB_IMMED_3D(so, VERT_COLOR_CLAMP_EN, cso->clamp_vertex_color);
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SB_BEGIN_3D(so, FRAG_COLOR_CLAMP_EN, 1);
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SB_DATA (so, cso->clamp_fragment_color ? 0x11111111 : 0x00000000);
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SB_IMMED_3D(so, MULTISAMPLE_ENABLE, cso->multisample);
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SB_IMMED_3D(so, LINE_SMOOTH_ENABLE, cso->line_smooth);
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if (cso->line_smooth || cso->multisample)
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SB_BEGIN_3D(so, LINE_WIDTH_SMOOTH, 1);
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else
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SB_BEGIN_3D(so, LINE_WIDTH_ALIASED, 1);
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SB_DATA (so, fui(cso->line_width));
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SB_IMMED_3D(so, LINE_STIPPLE_ENABLE, cso->line_stipple_enable);
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if (cso->line_stipple_enable) {
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SB_BEGIN_3D(so, LINE_STIPPLE_PATTERN, 1);
247
SB_DATA (so, (cso->line_stipple_pattern << 8) |
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cso->line_stipple_factor);
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250
}
251
252
SB_IMMED_3D(so, VP_POINT_SIZE, cso->point_size_per_vertex);
253
if (!cso->point_size_per_vertex) {
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SB_BEGIN_3D(so, POINT_SIZE, 1);
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SB_DATA (so, fui(cso->point_size));
256
}
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reg = (cso->sprite_coord_mode == PIPE_SPRITE_COORD_UPPER_LEFT) ?
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NVC0_3D_POINT_COORD_REPLACE_COORD_ORIGIN_UPPER_LEFT :
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NVC0_3D_POINT_COORD_REPLACE_COORD_ORIGIN_LOWER_LEFT;
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262
SB_BEGIN_3D(so, POINT_COORD_REPLACE, 1);
263
SB_DATA (so, ((cso->sprite_coord_enable & 0xff) << 3) | reg);
264
SB_IMMED_3D(so, POINT_SPRITE_ENABLE, cso->point_quad_rasterization);
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SB_IMMED_3D(so, POINT_SMOOTH_ENABLE, cso->point_smooth);
266
267
if (class_3d >= GM200_3D_CLASS) {
268
SB_IMMED_3D(so, FILL_RECTANGLE,
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cso->fill_front == PIPE_POLYGON_MODE_FILL_RECTANGLE ?
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NVC0_3D_FILL_RECTANGLE_ENABLE : 0);
271
}
272
273
SB_BEGIN_3D(so, MACRO_POLYGON_MODE_FRONT, 1);
274
SB_DATA (so, nvgl_polygon_mode(cso->fill_front));
275
SB_BEGIN_3D(so, MACRO_POLYGON_MODE_BACK, 1);
276
SB_DATA (so, nvgl_polygon_mode(cso->fill_back));
277
SB_IMMED_3D(so, POLYGON_SMOOTH_ENABLE, cso->poly_smooth);
278
279
SB_BEGIN_3D(so, CULL_FACE_ENABLE, 3);
280
SB_DATA (so, cso->cull_face != PIPE_FACE_NONE);
281
SB_DATA (so, cso->front_ccw ? NVC0_3D_FRONT_FACE_CCW :
282
NVC0_3D_FRONT_FACE_CW);
283
switch (cso->cull_face) {
284
case PIPE_FACE_FRONT_AND_BACK:
285
SB_DATA(so, NVC0_3D_CULL_FACE_FRONT_AND_BACK);
286
break;
287
case PIPE_FACE_FRONT:
288
SB_DATA(so, NVC0_3D_CULL_FACE_FRONT);
289
break;
290
case PIPE_FACE_BACK:
291
default:
292
SB_DATA(so, NVC0_3D_CULL_FACE_BACK);
293
break;
294
}
295
296
SB_IMMED_3D(so, POLYGON_STIPPLE_ENABLE, cso->poly_stipple_enable);
297
SB_BEGIN_3D(so, POLYGON_OFFSET_POINT_ENABLE, 3);
298
SB_DATA (so, cso->offset_point);
299
SB_DATA (so, cso->offset_line);
300
SB_DATA (so, cso->offset_tri);
301
302
if (cso->offset_point || cso->offset_line || cso->offset_tri) {
303
SB_BEGIN_3D(so, POLYGON_OFFSET_FACTOR, 1);
304
SB_DATA (so, fui(cso->offset_scale));
305
if (!cso->offset_units_unscaled) {
306
SB_BEGIN_3D(so, POLYGON_OFFSET_UNITS, 1);
307
SB_DATA (so, fui(cso->offset_units * 2.0f));
308
}
309
SB_BEGIN_3D(so, POLYGON_OFFSET_CLAMP, 1);
310
SB_DATA (so, fui(cso->offset_clamp));
311
}
312
313
if (cso->depth_clip_near)
314
reg = NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1;
315
else
316
reg =
317
NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1 |
318
NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_CLAMP_NEAR |
319
NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_CLAMP_FAR |
320
NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK12_UNK2;
321
322
SB_BEGIN_3D(so, VIEW_VOLUME_CLIP_CTRL, 1);
323
SB_DATA (so, reg);
324
325
SB_IMMED_3D(so, DEPTH_CLIP_NEGATIVE_Z, cso->clip_halfz);
326
327
SB_IMMED_3D(so, PIXEL_CENTER_INTEGER, !cso->half_pixel_center);
328
329
if (class_3d >= GM200_3D_CLASS) {
330
if (cso->conservative_raster_mode != PIPE_CONSERVATIVE_RASTER_OFF) {
331
bool post_snap = cso->conservative_raster_mode ==
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PIPE_CONSERVATIVE_RASTER_POST_SNAP;
333
uint32_t state = cso->subpixel_precision_x;
334
state |= cso->subpixel_precision_y << 4;
335
state |= (uint32_t)(cso->conservative_raster_dilate * 4) << 8;
336
state |= (post_snap || class_3d < GP100_3D_CLASS) ? 1 << 10 : 0;
337
SB_IMMED_3D(so, MACRO_CONSERVATIVE_RASTER_STATE, state);
338
} else {
339
SB_IMMED_3D(so, CONSERVATIVE_RASTER, 0);
340
}
341
}
342
343
assert(so->size <= ARRAY_SIZE(so->state));
344
return (void *)so;
345
}
346
347
static void
348
nvc0_rasterizer_state_bind(struct pipe_context *pipe, void *hwcso)
349
{
350
struct nvc0_context *nvc0 = nvc0_context(pipe);
351
352
nvc0->rast = hwcso;
353
nvc0->dirty_3d |= NVC0_NEW_3D_RASTERIZER;
354
}
355
356
static void
357
nvc0_rasterizer_state_delete(struct pipe_context *pipe, void *hwcso)
358
{
359
FREE(hwcso);
360
}
361
362
static void *
363
nvc0_zsa_state_create(struct pipe_context *pipe,
364
const struct pipe_depth_stencil_alpha_state *cso)
365
{
366
struct nvc0_zsa_stateobj *so = CALLOC_STRUCT(nvc0_zsa_stateobj);
367
368
so->pipe = *cso;
369
370
SB_IMMED_3D(so, DEPTH_TEST_ENABLE, cso->depth_enabled);
371
if (cso->depth_enabled) {
372
SB_IMMED_3D(so, DEPTH_WRITE_ENABLE, cso->depth_writemask);
373
SB_BEGIN_3D(so, DEPTH_TEST_FUNC, 1);
374
SB_DATA (so, nvgl_comparison_op(cso->depth_func));
375
}
376
377
SB_IMMED_3D(so, DEPTH_BOUNDS_EN, cso->depth_bounds_test);
378
if (cso->depth_bounds_test) {
379
SB_BEGIN_3D(so, DEPTH_BOUNDS(0), 2);
380
SB_DATA (so, fui(cso->depth_bounds_min));
381
SB_DATA (so, fui(cso->depth_bounds_max));
382
}
383
384
if (cso->stencil[0].enabled) {
385
SB_BEGIN_3D(so, STENCIL_ENABLE, 5);
386
SB_DATA (so, 1);
387
SB_DATA (so, nvgl_stencil_op(cso->stencil[0].fail_op));
388
SB_DATA (so, nvgl_stencil_op(cso->stencil[0].zfail_op));
389
SB_DATA (so, nvgl_stencil_op(cso->stencil[0].zpass_op));
390
SB_DATA (so, nvgl_comparison_op(cso->stencil[0].func));
391
SB_BEGIN_3D(so, STENCIL_FRONT_FUNC_MASK, 2);
392
SB_DATA (so, cso->stencil[0].valuemask);
393
SB_DATA (so, cso->stencil[0].writemask);
394
} else {
395
SB_IMMED_3D(so, STENCIL_ENABLE, 0);
396
}
397
398
if (cso->stencil[1].enabled) {
399
assert(cso->stencil[0].enabled);
400
SB_BEGIN_3D(so, STENCIL_TWO_SIDE_ENABLE, 5);
401
SB_DATA (so, 1);
402
SB_DATA (so, nvgl_stencil_op(cso->stencil[1].fail_op));
403
SB_DATA (so, nvgl_stencil_op(cso->stencil[1].zfail_op));
404
SB_DATA (so, nvgl_stencil_op(cso->stencil[1].zpass_op));
405
SB_DATA (so, nvgl_comparison_op(cso->stencil[1].func));
406
SB_BEGIN_3D(so, STENCIL_BACK_MASK, 2);
407
SB_DATA (so, cso->stencil[1].writemask);
408
SB_DATA (so, cso->stencil[1].valuemask);
409
} else
410
if (cso->stencil[0].enabled) {
411
SB_IMMED_3D(so, STENCIL_TWO_SIDE_ENABLE, 0);
412
}
413
414
SB_IMMED_3D(so, ALPHA_TEST_ENABLE, cso->alpha_enabled);
415
if (cso->alpha_enabled) {
416
SB_BEGIN_3D(so, ALPHA_TEST_REF, 2);
417
SB_DATA (so, fui(cso->alpha_ref_value));
418
SB_DATA (so, nvgl_comparison_op(cso->alpha_func));
419
}
420
421
assert(so->size <= ARRAY_SIZE(so->state));
422
return (void *)so;
423
}
424
425
static void
426
nvc0_zsa_state_bind(struct pipe_context *pipe, void *hwcso)
427
{
428
struct nvc0_context *nvc0 = nvc0_context(pipe);
429
430
nvc0->zsa = hwcso;
431
nvc0->dirty_3d |= NVC0_NEW_3D_ZSA;
432
}
433
434
static void
435
nvc0_zsa_state_delete(struct pipe_context *pipe, void *hwcso)
436
{
437
FREE(hwcso);
438
}
439
440
/* ====================== SAMPLERS AND TEXTURES ================================
441
*/
442
443
#define NV50_TSC_WRAP_CASE(n) \
444
case PIPE_TEX_WRAP_##n: return NV50_TSC_WRAP_##n
445
446
static void
447
nvc0_sampler_state_delete(struct pipe_context *pipe, void *hwcso)
448
{
449
unsigned s, i;
450
451
for (s = 0; s < 6; ++s)
452
for (i = 0; i < nvc0_context(pipe)->num_samplers[s]; ++i)
453
if (nvc0_context(pipe)->samplers[s][i] == hwcso)
454
nvc0_context(pipe)->samplers[s][i] = NULL;
455
456
nvc0_screen_tsc_free(nvc0_context(pipe)->screen, nv50_tsc_entry(hwcso));
457
458
FREE(hwcso);
459
}
460
461
static inline void
462
nvc0_stage_sampler_states_bind(struct nvc0_context *nvc0,
463
unsigned s,
464
unsigned nr, void **hwcsos)
465
{
466
unsigned highest_found = 0;
467
unsigned i;
468
469
for (i = 0; i < nr; ++i) {
470
struct nv50_tsc_entry *hwcso = hwcsos ? nv50_tsc_entry(hwcsos[i]) : NULL;
471
struct nv50_tsc_entry *old = nvc0->samplers[s][i];
472
473
if (hwcso)
474
highest_found = i;
475
476
if (hwcso == old)
477
continue;
478
nvc0->samplers_dirty[s] |= 1 << i;
479
480
nvc0->samplers[s][i] = hwcso;
481
if (old)
482
nvc0_screen_tsc_unlock(nvc0->screen, old);
483
}
484
if (nr >= nvc0->num_samplers[s])
485
nvc0->num_samplers[s] = highest_found + 1;
486
}
487
488
static void
489
nvc0_bind_sampler_states(struct pipe_context *pipe,
490
enum pipe_shader_type shader,
491
unsigned start, unsigned nr, void **samplers)
492
{
493
const unsigned s = nvc0_shader_stage(shader);
494
495
assert(start == 0);
496
nvc0_stage_sampler_states_bind(nvc0_context(pipe), s, nr, samplers);
497
498
if (s == 5)
499
nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_SAMPLERS;
500
else
501
nvc0_context(pipe)->dirty_3d |= NVC0_NEW_3D_SAMPLERS;
502
}
503
504
505
/* NOTE: only called when not referenced anywhere, won't be bound */
506
static void
507
nvc0_sampler_view_destroy(struct pipe_context *pipe,
508
struct pipe_sampler_view *view)
509
{
510
pipe_resource_reference(&view->texture, NULL);
511
512
nvc0_screen_tic_free(nvc0_context(pipe)->screen, nv50_tic_entry(view));
513
514
FREE(nv50_tic_entry(view));
515
}
516
517
static inline void
518
nvc0_stage_set_sampler_views(struct nvc0_context *nvc0, int s,
519
unsigned nr,
520
struct pipe_sampler_view **views)
521
{
522
unsigned i;
523
524
for (i = 0; i < nr; ++i) {
525
struct pipe_sampler_view *view = views ? views[i] : NULL;
526
struct nv50_tic_entry *old = nv50_tic_entry(nvc0->textures[s][i]);
527
528
if (view == nvc0->textures[s][i])
529
continue;
530
nvc0->textures_dirty[s] |= 1 << i;
531
532
if (view && view->texture) {
533
struct pipe_resource *res = view->texture;
534
if (res->target == PIPE_BUFFER &&
535
(res->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT))
536
nvc0->textures_coherent[s] |= 1 << i;
537
else
538
nvc0->textures_coherent[s] &= ~(1 << i);
539
} else {
540
nvc0->textures_coherent[s] &= ~(1 << i);
541
}
542
543
if (old) {
544
if (s == 5)
545
nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_TEX(i));
546
else
547
nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TEX(s, i));
548
nvc0_screen_tic_unlock(nvc0->screen, old);
549
}
550
551
pipe_sampler_view_reference(&nvc0->textures[s][i], view);
552
}
553
554
for (i = nr; i < nvc0->num_textures[s]; ++i) {
555
struct nv50_tic_entry *old = nv50_tic_entry(nvc0->textures[s][i]);
556
if (old) {
557
if (s == 5)
558
nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_TEX(i));
559
else
560
nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TEX(s, i));
561
nvc0_screen_tic_unlock(nvc0->screen, old);
562
pipe_sampler_view_reference(&nvc0->textures[s][i], NULL);
563
}
564
}
565
566
nvc0->num_textures[s] = nr;
567
}
568
569
static void
570
nvc0_set_sampler_views(struct pipe_context *pipe, enum pipe_shader_type shader,
571
unsigned start, unsigned nr,
572
unsigned unbind_num_trailing_slots,
573
struct pipe_sampler_view **views)
574
{
575
const unsigned s = nvc0_shader_stage(shader);
576
577
assert(start == 0);
578
nvc0_stage_set_sampler_views(nvc0_context(pipe), s, nr, views);
579
580
if (s == 5)
581
nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_TEXTURES;
582
else
583
nvc0_context(pipe)->dirty_3d |= NVC0_NEW_3D_TEXTURES;
584
}
585
586
/* ============================= SHADERS =======================================
587
*/
588
589
static void *
590
nvc0_sp_state_create(struct pipe_context *pipe,
591
const struct pipe_shader_state *cso, unsigned type)
592
{
593
struct nvc0_program *prog;
594
595
prog = CALLOC_STRUCT(nvc0_program);
596
if (!prog)
597
return NULL;
598
599
prog->type = type;
600
prog->pipe.type = cso->type;
601
602
switch(cso->type) {
603
case PIPE_SHADER_IR_TGSI:
604
prog->pipe.tokens = tgsi_dup_tokens(cso->tokens);
605
break;
606
case PIPE_SHADER_IR_NIR:
607
prog->pipe.ir.nir = cso->ir.nir;
608
break;
609
default:
610
assert(!"unsupported IR!");
611
free(prog);
612
return NULL;
613
}
614
615
if (cso->stream_output.num_outputs)
616
prog->pipe.stream_output = cso->stream_output;
617
618
prog->translated = nvc0_program_translate(
619
prog, nvc0_context(pipe)->screen->base.device->chipset,
620
nvc0_context(pipe)->screen->base.disk_shader_cache,
621
&nouveau_context(pipe)->debug);
622
623
return (void *)prog;
624
}
625
626
static void
627
nvc0_sp_state_delete(struct pipe_context *pipe, void *hwcso)
628
{
629
struct nvc0_program *prog = (struct nvc0_program *)hwcso;
630
631
nvc0_program_destroy(nvc0_context(pipe), prog);
632
633
if (prog->pipe.type == PIPE_SHADER_IR_TGSI)
634
FREE((void *)prog->pipe.tokens);
635
else if (prog->pipe.type == PIPE_SHADER_IR_NIR)
636
ralloc_free(prog->pipe.ir.nir);
637
FREE(prog);
638
}
639
640
static void *
641
nvc0_vp_state_create(struct pipe_context *pipe,
642
const struct pipe_shader_state *cso)
643
{
644
return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_VERTEX);
645
}
646
647
static void
648
nvc0_vp_state_bind(struct pipe_context *pipe, void *hwcso)
649
{
650
struct nvc0_context *nvc0 = nvc0_context(pipe);
651
652
nvc0->vertprog = hwcso;
653
nvc0->dirty_3d |= NVC0_NEW_3D_VERTPROG;
654
}
655
656
static void *
657
nvc0_fp_state_create(struct pipe_context *pipe,
658
const struct pipe_shader_state *cso)
659
{
660
return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_FRAGMENT);
661
}
662
663
static void
664
nvc0_fp_state_bind(struct pipe_context *pipe, void *hwcso)
665
{
666
struct nvc0_context *nvc0 = nvc0_context(pipe);
667
668
nvc0->fragprog = hwcso;
669
nvc0->dirty_3d |= NVC0_NEW_3D_FRAGPROG;
670
}
671
672
static void *
673
nvc0_gp_state_create(struct pipe_context *pipe,
674
const struct pipe_shader_state *cso)
675
{
676
return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_GEOMETRY);
677
}
678
679
static void
680
nvc0_gp_state_bind(struct pipe_context *pipe, void *hwcso)
681
{
682
struct nvc0_context *nvc0 = nvc0_context(pipe);
683
684
nvc0->gmtyprog = hwcso;
685
nvc0->dirty_3d |= NVC0_NEW_3D_GMTYPROG;
686
}
687
688
static void *
689
nvc0_tcp_state_create(struct pipe_context *pipe,
690
const struct pipe_shader_state *cso)
691
{
692
return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_TESS_CTRL);
693
}
694
695
static void
696
nvc0_tcp_state_bind(struct pipe_context *pipe, void *hwcso)
697
{
698
struct nvc0_context *nvc0 = nvc0_context(pipe);
699
700
nvc0->tctlprog = hwcso;
701
nvc0->dirty_3d |= NVC0_NEW_3D_TCTLPROG;
702
}
703
704
static void *
705
nvc0_tep_state_create(struct pipe_context *pipe,
706
const struct pipe_shader_state *cso)
707
{
708
return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_TESS_EVAL);
709
}
710
711
static void
712
nvc0_tep_state_bind(struct pipe_context *pipe, void *hwcso)
713
{
714
struct nvc0_context *nvc0 = nvc0_context(pipe);
715
716
nvc0->tevlprog = hwcso;
717
nvc0->dirty_3d |= NVC0_NEW_3D_TEVLPROG;
718
}
719
720
static void *
721
nvc0_cp_state_create(struct pipe_context *pipe,
722
const struct pipe_compute_state *cso)
723
{
724
struct nvc0_program *prog;
725
726
prog = CALLOC_STRUCT(nvc0_program);
727
if (!prog)
728
return NULL;
729
prog->type = PIPE_SHADER_COMPUTE;
730
prog->pipe.type = cso->ir_type;
731
732
prog->cp.smem_size = cso->req_local_mem;
733
prog->cp.lmem_size = cso->req_private_mem;
734
prog->parm_size = cso->req_input_mem;
735
736
switch(cso->ir_type) {
737
case PIPE_SHADER_IR_TGSI:
738
prog->pipe.tokens = tgsi_dup_tokens((const struct tgsi_token *)cso->prog);
739
break;
740
case PIPE_SHADER_IR_NIR:
741
prog->pipe.ir.nir = (nir_shader *)cso->prog;
742
break;
743
case PIPE_SHADER_IR_NIR_SERIALIZED: {
744
struct blob_reader reader;
745
const struct pipe_binary_program_header *hdr = cso->prog;
746
747
blob_reader_init(&reader, hdr->blob, hdr->num_bytes);
748
prog->pipe.ir.nir = nir_deserialize(NULL, pipe->screen->get_compiler_options(pipe->screen, PIPE_SHADER_IR_NIR, PIPE_SHADER_COMPUTE), &reader);
749
prog->pipe.type = PIPE_SHADER_IR_NIR;
750
break;
751
}
752
default:
753
assert(!"unsupported IR!");
754
free(prog);
755
return NULL;
756
}
757
758
prog->translated = nvc0_program_translate(
759
prog, nvc0_context(pipe)->screen->base.device->chipset,
760
nvc0_context(pipe)->screen->base.disk_shader_cache,
761
&nouveau_context(pipe)->debug);
762
763
return (void *)prog;
764
}
765
766
static void
767
nvc0_cp_state_bind(struct pipe_context *pipe, void *hwcso)
768
{
769
struct nvc0_context *nvc0 = nvc0_context(pipe);
770
771
nvc0->compprog = hwcso;
772
nvc0->dirty_cp |= NVC0_NEW_CP_PROGRAM;
773
}
774
775
static void
776
nvc0_set_constant_buffer(struct pipe_context *pipe,
777
enum pipe_shader_type shader, uint index,
778
bool take_ownership,
779
const struct pipe_constant_buffer *cb)
780
{
781
struct nvc0_context *nvc0 = nvc0_context(pipe);
782
struct pipe_resource *res = cb ? cb->buffer : NULL;
783
const unsigned s = nvc0_shader_stage(shader);
784
const unsigned i = index;
785
786
if (unlikely(shader == PIPE_SHADER_COMPUTE)) {
787
if (nvc0->constbuf[s][i].user)
788
nvc0->constbuf[s][i].u.buf = NULL;
789
else
790
if (nvc0->constbuf[s][i].u.buf)
791
nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_CB(i));
792
793
nvc0->dirty_cp |= NVC0_NEW_CP_CONSTBUF;
794
} else {
795
if (nvc0->constbuf[s][i].user)
796
nvc0->constbuf[s][i].u.buf = NULL;
797
else
798
if (nvc0->constbuf[s][i].u.buf)
799
nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_CB(s, i));
800
801
nvc0->dirty_3d |= NVC0_NEW_3D_CONSTBUF;
802
}
803
nvc0->constbuf_dirty[s] |= 1 << i;
804
805
if (nvc0->constbuf[s][i].u.buf)
806
nv04_resource(nvc0->constbuf[s][i].u.buf)->cb_bindings[s] &= ~(1 << i);
807
808
if (take_ownership) {
809
pipe_resource_reference(&nvc0->constbuf[s][i].u.buf, NULL);
810
nvc0->constbuf[s][i].u.buf = res;
811
} else {
812
pipe_resource_reference(&nvc0->constbuf[s][i].u.buf, res);
813
}
814
815
nvc0->constbuf[s][i].user = (cb && cb->user_buffer) ? true : false;
816
if (nvc0->constbuf[s][i].user) {
817
nvc0->constbuf[s][i].u.data = cb->user_buffer;
818
nvc0->constbuf[s][i].size = MIN2(cb->buffer_size, 0x10000);
819
nvc0->constbuf_valid[s] |= 1 << i;
820
nvc0->constbuf_coherent[s] &= ~(1 << i);
821
} else
822
if (cb) {
823
nvc0->constbuf[s][i].offset = cb->buffer_offset;
824
nvc0->constbuf[s][i].size = MIN2(align(cb->buffer_size, 0x100), 0x10000);
825
nvc0->constbuf_valid[s] |= 1 << i;
826
if (res && res->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT)
827
nvc0->constbuf_coherent[s] |= 1 << i;
828
else
829
nvc0->constbuf_coherent[s] &= ~(1 << i);
830
}
831
else {
832
nvc0->constbuf_valid[s] &= ~(1 << i);
833
nvc0->constbuf_coherent[s] &= ~(1 << i);
834
}
835
}
836
837
/* =============================================================================
838
*/
839
840
static void
841
nvc0_set_blend_color(struct pipe_context *pipe,
842
const struct pipe_blend_color *bcol)
843
{
844
struct nvc0_context *nvc0 = nvc0_context(pipe);
845
846
nvc0->blend_colour = *bcol;
847
nvc0->dirty_3d |= NVC0_NEW_3D_BLEND_COLOUR;
848
}
849
850
static void
851
nvc0_set_stencil_ref(struct pipe_context *pipe,
852
const struct pipe_stencil_ref sr)
853
{
854
struct nvc0_context *nvc0 = nvc0_context(pipe);
855
856
nvc0->stencil_ref = sr;
857
nvc0->dirty_3d |= NVC0_NEW_3D_STENCIL_REF;
858
}
859
860
static void
861
nvc0_set_clip_state(struct pipe_context *pipe,
862
const struct pipe_clip_state *clip)
863
{
864
struct nvc0_context *nvc0 = nvc0_context(pipe);
865
866
memcpy(nvc0->clip.ucp, clip->ucp, sizeof(clip->ucp));
867
868
nvc0->dirty_3d |= NVC0_NEW_3D_CLIP;
869
}
870
871
static void
872
nvc0_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
873
{
874
struct nvc0_context *nvc0 = nvc0_context(pipe);
875
876
nvc0->sample_mask = sample_mask;
877
nvc0->dirty_3d |= NVC0_NEW_3D_SAMPLE_MASK;
878
}
879
880
static void
881
nvc0_set_min_samples(struct pipe_context *pipe, unsigned min_samples)
882
{
883
struct nvc0_context *nvc0 = nvc0_context(pipe);
884
885
if (nvc0->min_samples != min_samples) {
886
nvc0->min_samples = min_samples;
887
nvc0->dirty_3d |= NVC0_NEW_3D_MIN_SAMPLES;
888
}
889
}
890
891
static void
892
nvc0_set_framebuffer_state(struct pipe_context *pipe,
893
const struct pipe_framebuffer_state *fb)
894
{
895
struct nvc0_context *nvc0 = nvc0_context(pipe);
896
897
nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_FB);
898
899
util_copy_framebuffer_state(&nvc0->framebuffer, fb);
900
901
nvc0->dirty_3d |= NVC0_NEW_3D_FRAMEBUFFER | NVC0_NEW_3D_SAMPLE_LOCATIONS |
902
NVC0_NEW_3D_TEXTURES;
903
nvc0->dirty_cp |= NVC0_NEW_CP_TEXTURES;
904
}
905
906
static void
907
nvc0_set_sample_locations(struct pipe_context *pipe,
908
size_t size, const uint8_t *locations)
909
{
910
struct nvc0_context *nvc0 = nvc0_context(pipe);
911
912
nvc0->sample_locations_enabled = size && locations;
913
if (size > sizeof(nvc0->sample_locations))
914
size = sizeof(nvc0->sample_locations);
915
memcpy(nvc0->sample_locations, locations, size);
916
917
nvc0->dirty_3d |= NVC0_NEW_3D_SAMPLE_LOCATIONS;
918
}
919
920
static void
921
nvc0_set_polygon_stipple(struct pipe_context *pipe,
922
const struct pipe_poly_stipple *stipple)
923
{
924
struct nvc0_context *nvc0 = nvc0_context(pipe);
925
926
nvc0->stipple = *stipple;
927
nvc0->dirty_3d |= NVC0_NEW_3D_STIPPLE;
928
}
929
930
static void
931
nvc0_set_scissor_states(struct pipe_context *pipe,
932
unsigned start_slot,
933
unsigned num_scissors,
934
const struct pipe_scissor_state *scissor)
935
{
936
struct nvc0_context *nvc0 = nvc0_context(pipe);
937
int i;
938
939
assert(start_slot + num_scissors <= NVC0_MAX_VIEWPORTS);
940
for (i = 0; i < num_scissors; i++) {
941
if (!memcmp(&nvc0->scissors[start_slot + i], &scissor[i], sizeof(*scissor)))
942
continue;
943
nvc0->scissors[start_slot + i] = scissor[i];
944
nvc0->scissors_dirty |= 1 << (start_slot + i);
945
nvc0->dirty_3d |= NVC0_NEW_3D_SCISSOR;
946
}
947
}
948
949
static void
950
nvc0_set_viewport_states(struct pipe_context *pipe,
951
unsigned start_slot,
952
unsigned num_viewports,
953
const struct pipe_viewport_state *vpt)
954
{
955
struct nvc0_context *nvc0 = nvc0_context(pipe);
956
int i;
957
958
assert(start_slot + num_viewports <= NVC0_MAX_VIEWPORTS);
959
for (i = 0; i < num_viewports; i++) {
960
if (!memcmp(&nvc0->viewports[start_slot + i], &vpt[i], sizeof(*vpt)))
961
continue;
962
nvc0->viewports[start_slot + i] = vpt[i];
963
nvc0->viewports_dirty |= 1 << (start_slot + i);
964
nvc0->dirty_3d |= NVC0_NEW_3D_VIEWPORT;
965
}
966
967
}
968
969
static void
970
nvc0_set_window_rectangles(struct pipe_context *pipe,
971
bool include,
972
unsigned num_rectangles,
973
const struct pipe_scissor_state *rectangles)
974
{
975
struct nvc0_context *nvc0 = nvc0_context(pipe);
976
977
nvc0->window_rect.inclusive = include;
978
nvc0->window_rect.rects = MIN2(num_rectangles, NVC0_MAX_WINDOW_RECTANGLES);
979
memcpy(nvc0->window_rect.rect, rectangles,
980
sizeof(struct pipe_scissor_state) * nvc0->window_rect.rects);
981
982
nvc0->dirty_3d |= NVC0_NEW_3D_WINDOW_RECTS;
983
}
984
985
static void
986
nvc0_set_tess_state(struct pipe_context *pipe,
987
const float default_tess_outer[4],
988
const float default_tess_inner[2])
989
{
990
struct nvc0_context *nvc0 = nvc0_context(pipe);
991
992
memcpy(nvc0->default_tess_outer, default_tess_outer, 4 * sizeof(float));
993
memcpy(nvc0->default_tess_inner, default_tess_inner, 2 * sizeof(float));
994
nvc0->dirty_3d |= NVC0_NEW_3D_TESSFACTOR;
995
}
996
997
static void
998
nvc0_set_vertex_buffers(struct pipe_context *pipe,
999
unsigned start_slot, unsigned count,
1000
unsigned unbind_num_trailing_slots,
1001
bool take_ownership,
1002
const struct pipe_vertex_buffer *vb)
1003
{
1004
struct nvc0_context *nvc0 = nvc0_context(pipe);
1005
unsigned i;
1006
1007
nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_VTX);
1008
nvc0->dirty_3d |= NVC0_NEW_3D_ARRAYS;
1009
1010
util_set_vertex_buffers_count(nvc0->vtxbuf, &nvc0->num_vtxbufs, vb,
1011
start_slot, count,
1012
unbind_num_trailing_slots,
1013
take_ownership);
1014
1015
unsigned clear_mask = ~u_bit_consecutive(start_slot + count, unbind_num_trailing_slots);
1016
nvc0->vbo_user &= clear_mask;
1017
nvc0->constant_vbos &= clear_mask;
1018
nvc0->vtxbufs_coherent &= clear_mask;
1019
1020
if (!vb) {
1021
clear_mask = ~u_bit_consecutive(start_slot, count);
1022
nvc0->vbo_user &= clear_mask;
1023
nvc0->constant_vbos &= clear_mask;
1024
nvc0->vtxbufs_coherent &= clear_mask;
1025
return;
1026
}
1027
1028
for (i = 0; i < count; ++i) {
1029
unsigned dst_index = start_slot + i;
1030
1031
if (vb[i].is_user_buffer) {
1032
nvc0->vbo_user |= 1 << dst_index;
1033
if (!vb[i].stride && nvc0->screen->eng3d->oclass < GM107_3D_CLASS)
1034
nvc0->constant_vbos |= 1 << dst_index;
1035
else
1036
nvc0->constant_vbos &= ~(1 << dst_index);
1037
nvc0->vtxbufs_coherent &= ~(1 << dst_index);
1038
} else {
1039
nvc0->vbo_user &= ~(1 << dst_index);
1040
nvc0->constant_vbos &= ~(1 << dst_index);
1041
1042
if (vb[i].buffer.resource &&
1043
vb[i].buffer.resource->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT)
1044
nvc0->vtxbufs_coherent |= (1 << dst_index);
1045
else
1046
nvc0->vtxbufs_coherent &= ~(1 << dst_index);
1047
}
1048
}
1049
}
1050
1051
static void
1052
nvc0_vertex_state_bind(struct pipe_context *pipe, void *hwcso)
1053
{
1054
struct nvc0_context *nvc0 = nvc0_context(pipe);
1055
1056
nvc0->vertex = hwcso;
1057
nvc0->dirty_3d |= NVC0_NEW_3D_VERTEX;
1058
}
1059
1060
static struct pipe_stream_output_target *
1061
nvc0_so_target_create(struct pipe_context *pipe,
1062
struct pipe_resource *res,
1063
unsigned offset, unsigned size)
1064
{
1065
struct nv04_resource *buf = (struct nv04_resource *)res;
1066
struct nvc0_so_target *targ = MALLOC_STRUCT(nvc0_so_target);
1067
if (!targ)
1068
return NULL;
1069
1070
targ->pq = pipe->create_query(pipe, NVC0_HW_QUERY_TFB_BUFFER_OFFSET, 0);
1071
if (!targ->pq) {
1072
FREE(targ);
1073
return NULL;
1074
}
1075
targ->clean = true;
1076
1077
targ->pipe.buffer_size = size;
1078
targ->pipe.buffer_offset = offset;
1079
targ->pipe.context = pipe;
1080
targ->pipe.buffer = NULL;
1081
pipe_resource_reference(&targ->pipe.buffer, res);
1082
pipe_reference_init(&targ->pipe.reference, 1);
1083
1084
assert(buf->base.target == PIPE_BUFFER);
1085
util_range_add(&buf->base, &buf->valid_buffer_range, offset, offset + size);
1086
1087
return &targ->pipe;
1088
}
1089
1090
static void
1091
nvc0_so_target_save_offset(struct pipe_context *pipe,
1092
struct pipe_stream_output_target *ptarg,
1093
unsigned index, bool *serialize)
1094
{
1095
struct nvc0_so_target *targ = nvc0_so_target(ptarg);
1096
1097
if (*serialize) {
1098
*serialize = false;
1099
PUSH_SPACE(nvc0_context(pipe)->base.pushbuf, 1);
1100
IMMED_NVC0(nvc0_context(pipe)->base.pushbuf, NVC0_3D(SERIALIZE), 0);
1101
1102
NOUVEAU_DRV_STAT(nouveau_screen(pipe->screen), gpu_serialize_count, 1);
1103
}
1104
1105
nvc0_query(targ->pq)->index = index;
1106
pipe->end_query(pipe, targ->pq);
1107
}
1108
1109
static void
1110
nvc0_so_target_destroy(struct pipe_context *pipe,
1111
struct pipe_stream_output_target *ptarg)
1112
{
1113
struct nvc0_so_target *targ = nvc0_so_target(ptarg);
1114
pipe->destroy_query(pipe, targ->pq);
1115
pipe_resource_reference(&targ->pipe.buffer, NULL);
1116
FREE(targ);
1117
}
1118
1119
static void
1120
nvc0_set_transform_feedback_targets(struct pipe_context *pipe,
1121
unsigned num_targets,
1122
struct pipe_stream_output_target **targets,
1123
const unsigned *offsets)
1124
{
1125
struct nvc0_context *nvc0 = nvc0_context(pipe);
1126
unsigned i;
1127
bool serialize = true;
1128
1129
assert(num_targets <= 4);
1130
1131
for (i = 0; i < num_targets; ++i) {
1132
const bool changed = nvc0->tfbbuf[i] != targets[i];
1133
const bool append = (offsets[i] == ((unsigned)-1));
1134
if (!changed && append)
1135
continue;
1136
nvc0->tfbbuf_dirty |= 1 << i;
1137
1138
if (nvc0->tfbbuf[i] && changed)
1139
nvc0_so_target_save_offset(pipe, nvc0->tfbbuf[i], i, &serialize);
1140
1141
if (targets[i] && !append)
1142
nvc0_so_target(targets[i])->clean = true;
1143
1144
pipe_so_target_reference(&nvc0->tfbbuf[i], targets[i]);
1145
}
1146
for (; i < nvc0->num_tfbbufs; ++i) {
1147
if (nvc0->tfbbuf[i]) {
1148
nvc0->tfbbuf_dirty |= 1 << i;
1149
nvc0_so_target_save_offset(pipe, nvc0->tfbbuf[i], i, &serialize);
1150
pipe_so_target_reference(&nvc0->tfbbuf[i], NULL);
1151
}
1152
}
1153
nvc0->num_tfbbufs = num_targets;
1154
1155
if (nvc0->tfbbuf_dirty) {
1156
nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TFB);
1157
nvc0->dirty_3d |= NVC0_NEW_3D_TFB_TARGETS;
1158
}
1159
}
1160
1161
static void
1162
nvc0_bind_surfaces_range(struct nvc0_context *nvc0, const unsigned t,
1163
unsigned start, unsigned nr,
1164
struct pipe_surface **psurfaces)
1165
{
1166
const unsigned end = start + nr;
1167
const unsigned mask = ((1 << nr) - 1) << start;
1168
unsigned i;
1169
1170
if (psurfaces) {
1171
for (i = start; i < end; ++i) {
1172
const unsigned p = i - start;
1173
if (psurfaces[p])
1174
nvc0->surfaces_valid[t] |= (1 << i);
1175
else
1176
nvc0->surfaces_valid[t] &= ~(1 << i);
1177
pipe_surface_reference(&nvc0->surfaces[t][i], psurfaces[p]);
1178
}
1179
} else {
1180
for (i = start; i < end; ++i)
1181
pipe_surface_reference(&nvc0->surfaces[t][i], NULL);
1182
nvc0->surfaces_valid[t] &= ~mask;
1183
}
1184
nvc0->surfaces_dirty[t] |= mask;
1185
1186
if (t == 0)
1187
nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_SUF);
1188
else
1189
nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_SUF);
1190
}
1191
1192
static void
1193
nvc0_set_compute_resources(struct pipe_context *pipe,
1194
unsigned start, unsigned nr,
1195
struct pipe_surface **resources)
1196
{
1197
nvc0_bind_surfaces_range(nvc0_context(pipe), 1, start, nr, resources);
1198
1199
nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_SURFACES;
1200
}
1201
1202
static bool
1203
nvc0_bind_images_range(struct nvc0_context *nvc0, const unsigned s,
1204
unsigned start, unsigned nr,
1205
const struct pipe_image_view *pimages)
1206
{
1207
const unsigned end = start + nr;
1208
unsigned mask = 0;
1209
unsigned i;
1210
1211
assert(s < 6);
1212
1213
if (pimages) {
1214
for (i = start; i < end; ++i) {
1215
struct pipe_image_view *img = &nvc0->images[s][i];
1216
const unsigned p = i - start;
1217
1218
if (img->resource == pimages[p].resource &&
1219
img->format == pimages[p].format &&
1220
img->access == pimages[p].access) {
1221
if (img->resource == NULL)
1222
continue;
1223
if (img->resource->target == PIPE_BUFFER &&
1224
img->u.buf.offset == pimages[p].u.buf.offset &&
1225
img->u.buf.size == pimages[p].u.buf.size)
1226
continue;
1227
if (img->resource->target != PIPE_BUFFER &&
1228
img->u.tex.first_layer == pimages[p].u.tex.first_layer &&
1229
img->u.tex.last_layer == pimages[p].u.tex.last_layer &&
1230
img->u.tex.level == pimages[p].u.tex.level)
1231
continue;
1232
}
1233
1234
mask |= (1 << i);
1235
if (pimages[p].resource)
1236
nvc0->images_valid[s] |= (1 << i);
1237
else
1238
nvc0->images_valid[s] &= ~(1 << i);
1239
1240
img->format = pimages[p].format;
1241
img->access = pimages[p].access;
1242
if (pimages[p].resource && pimages[p].resource->target == PIPE_BUFFER)
1243
img->u.buf = pimages[p].u.buf;
1244
else
1245
img->u.tex = pimages[p].u.tex;
1246
1247
pipe_resource_reference(
1248
&img->resource, pimages[p].resource);
1249
1250
if (nvc0->screen->base.class_3d >= GM107_3D_CLASS) {
1251
if (nvc0->images_tic[s][i]) {
1252
struct nv50_tic_entry *old =
1253
nv50_tic_entry(nvc0->images_tic[s][i]);
1254
nvc0_screen_tic_unlock(nvc0->screen, old);
1255
pipe_sampler_view_reference(&nvc0->images_tic[s][i], NULL);
1256
}
1257
1258
nvc0->images_tic[s][i] =
1259
gm107_create_texture_view_from_image(&nvc0->base.pipe,
1260
&pimages[p]);
1261
}
1262
}
1263
if (!mask)
1264
return false;
1265
} else {
1266
mask = ((1 << nr) - 1) << start;
1267
if (!(nvc0->images_valid[s] & mask))
1268
return false;
1269
for (i = start; i < end; ++i) {
1270
pipe_resource_reference(&nvc0->images[s][i].resource, NULL);
1271
if (nvc0->screen->base.class_3d >= GM107_3D_CLASS) {
1272
struct nv50_tic_entry *old = nv50_tic_entry(nvc0->images_tic[s][i]);
1273
if (old) {
1274
nvc0_screen_tic_unlock(nvc0->screen, old);
1275
pipe_sampler_view_reference(&nvc0->images_tic[s][i], NULL);
1276
}
1277
}
1278
}
1279
nvc0->images_valid[s] &= ~mask;
1280
}
1281
nvc0->images_dirty[s] |= mask;
1282
1283
if (s == 5)
1284
nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_SUF);
1285
else
1286
nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_SUF);
1287
1288
return true;
1289
}
1290
1291
static void
1292
nvc0_set_shader_images(struct pipe_context *pipe,
1293
enum pipe_shader_type shader,
1294
unsigned start, unsigned nr,
1295
unsigned unbind_num_trailing_slots,
1296
const struct pipe_image_view *images)
1297
{
1298
const unsigned s = nvc0_shader_stage(shader);
1299
1300
nvc0_bind_images_range(nvc0_context(pipe), s, start + nr,
1301
unbind_num_trailing_slots, NULL);
1302
1303
if (!nvc0_bind_images_range(nvc0_context(pipe), s, start, nr, images))
1304
return;
1305
1306
if (s == 5)
1307
nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_SURFACES;
1308
else
1309
nvc0_context(pipe)->dirty_3d |= NVC0_NEW_3D_SURFACES;
1310
}
1311
1312
static bool
1313
nvc0_bind_buffers_range(struct nvc0_context *nvc0, const unsigned t,
1314
unsigned start, unsigned nr,
1315
const struct pipe_shader_buffer *pbuffers)
1316
{
1317
const unsigned end = start + nr;
1318
unsigned mask = 0;
1319
unsigned i;
1320
1321
assert(t < 6);
1322
1323
if (pbuffers) {
1324
for (i = start; i < end; ++i) {
1325
struct pipe_shader_buffer *buf = &nvc0->buffers[t][i];
1326
const unsigned p = i - start;
1327
if (buf->buffer == pbuffers[p].buffer &&
1328
buf->buffer_offset == pbuffers[p].buffer_offset &&
1329
buf->buffer_size == pbuffers[p].buffer_size)
1330
continue;
1331
1332
mask |= (1 << i);
1333
if (pbuffers[p].buffer)
1334
nvc0->buffers_valid[t] |= (1 << i);
1335
else
1336
nvc0->buffers_valid[t] &= ~(1 << i);
1337
buf->buffer_offset = pbuffers[p].buffer_offset;
1338
buf->buffer_size = pbuffers[p].buffer_size;
1339
pipe_resource_reference(&buf->buffer, pbuffers[p].buffer);
1340
}
1341
if (!mask)
1342
return false;
1343
} else {
1344
mask = ((1 << nr) - 1) << start;
1345
if (!(nvc0->buffers_valid[t] & mask))
1346
return false;
1347
for (i = start; i < end; ++i)
1348
pipe_resource_reference(&nvc0->buffers[t][i].buffer, NULL);
1349
nvc0->buffers_valid[t] &= ~mask;
1350
}
1351
nvc0->buffers_dirty[t] |= mask;
1352
1353
if (t == 5)
1354
nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_BUF);
1355
else
1356
nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_BUF);
1357
1358
return true;
1359
}
1360
1361
static void
1362
nvc0_set_shader_buffers(struct pipe_context *pipe,
1363
enum pipe_shader_type shader,
1364
unsigned start, unsigned nr,
1365
const struct pipe_shader_buffer *buffers,
1366
unsigned writable_bitmask)
1367
{
1368
const unsigned s = nvc0_shader_stage(shader);
1369
if (!nvc0_bind_buffers_range(nvc0_context(pipe), s, start, nr, buffers))
1370
return;
1371
1372
if (s == 5)
1373
nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_BUFFERS;
1374
else
1375
nvc0_context(pipe)->dirty_3d |= NVC0_NEW_3D_BUFFERS;
1376
}
1377
1378
static inline void
1379
nvc0_set_global_handle(uint32_t *phandle, struct pipe_resource *res)
1380
{
1381
struct nv04_resource *buf = nv04_resource(res);
1382
if (buf) {
1383
uint64_t address = buf->address + *phandle;
1384
/* even though it's a pointer to uint32_t that's fine */
1385
memcpy(phandle, &address, 8);
1386
} else {
1387
*phandle = 0;
1388
}
1389
}
1390
1391
static void
1392
nvc0_set_global_bindings(struct pipe_context *pipe,
1393
unsigned start, unsigned nr,
1394
struct pipe_resource **resources,
1395
uint32_t **handles)
1396
{
1397
struct nvc0_context *nvc0 = nvc0_context(pipe);
1398
struct pipe_resource **ptr;
1399
unsigned i;
1400
const unsigned end = start + nr;
1401
1402
if (!nr)
1403
return;
1404
1405
if (nvc0->global_residents.size <= (end * sizeof(struct pipe_resource *))) {
1406
const unsigned old_size = nvc0->global_residents.size;
1407
if (util_dynarray_resize(&nvc0->global_residents, struct pipe_resource *, end)) {
1408
memset((uint8_t *)nvc0->global_residents.data + old_size, 0,
1409
nvc0->global_residents.size - old_size);
1410
} else {
1411
NOUVEAU_ERR("Could not resize global residents array\n");
1412
return;
1413
}
1414
}
1415
1416
if (resources) {
1417
ptr = util_dynarray_element(
1418
&nvc0->global_residents, struct pipe_resource *, start);
1419
for (i = 0; i < nr; ++i) {
1420
pipe_resource_reference(&ptr[i], resources[i]);
1421
nvc0_set_global_handle(handles[i], resources[i]);
1422
}
1423
} else {
1424
ptr = util_dynarray_element(
1425
&nvc0->global_residents, struct pipe_resource *, start);
1426
for (i = 0; i < nr; ++i)
1427
pipe_resource_reference(&ptr[i], NULL);
1428
}
1429
1430
nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_GLOBAL);
1431
1432
nvc0->dirty_cp |= NVC0_NEW_CP_GLOBALS;
1433
}
1434
1435
void
1436
nvc0_init_state_functions(struct nvc0_context *nvc0)
1437
{
1438
struct pipe_context *pipe = &nvc0->base.pipe;
1439
1440
pipe->create_blend_state = nvc0_blend_state_create;
1441
pipe->bind_blend_state = nvc0_blend_state_bind;
1442
pipe->delete_blend_state = nvc0_blend_state_delete;
1443
1444
pipe->create_rasterizer_state = nvc0_rasterizer_state_create;
1445
pipe->bind_rasterizer_state = nvc0_rasterizer_state_bind;
1446
pipe->delete_rasterizer_state = nvc0_rasterizer_state_delete;
1447
1448
pipe->create_depth_stencil_alpha_state = nvc0_zsa_state_create;
1449
pipe->bind_depth_stencil_alpha_state = nvc0_zsa_state_bind;
1450
pipe->delete_depth_stencil_alpha_state = nvc0_zsa_state_delete;
1451
1452
pipe->create_sampler_state = nv50_sampler_state_create;
1453
pipe->delete_sampler_state = nvc0_sampler_state_delete;
1454
pipe->bind_sampler_states = nvc0_bind_sampler_states;
1455
1456
pipe->create_sampler_view = nvc0_create_sampler_view;
1457
pipe->sampler_view_destroy = nvc0_sampler_view_destroy;
1458
pipe->set_sampler_views = nvc0_set_sampler_views;
1459
1460
pipe->create_vs_state = nvc0_vp_state_create;
1461
pipe->create_fs_state = nvc0_fp_state_create;
1462
pipe->create_gs_state = nvc0_gp_state_create;
1463
pipe->create_tcs_state = nvc0_tcp_state_create;
1464
pipe->create_tes_state = nvc0_tep_state_create;
1465
pipe->bind_vs_state = nvc0_vp_state_bind;
1466
pipe->bind_fs_state = nvc0_fp_state_bind;
1467
pipe->bind_gs_state = nvc0_gp_state_bind;
1468
pipe->bind_tcs_state = nvc0_tcp_state_bind;
1469
pipe->bind_tes_state = nvc0_tep_state_bind;
1470
pipe->delete_vs_state = nvc0_sp_state_delete;
1471
pipe->delete_fs_state = nvc0_sp_state_delete;
1472
pipe->delete_gs_state = nvc0_sp_state_delete;
1473
pipe->delete_tcs_state = nvc0_sp_state_delete;
1474
pipe->delete_tes_state = nvc0_sp_state_delete;
1475
1476
pipe->create_compute_state = nvc0_cp_state_create;
1477
pipe->bind_compute_state = nvc0_cp_state_bind;
1478
pipe->delete_compute_state = nvc0_sp_state_delete;
1479
1480
pipe->set_blend_color = nvc0_set_blend_color;
1481
pipe->set_stencil_ref = nvc0_set_stencil_ref;
1482
pipe->set_clip_state = nvc0_set_clip_state;
1483
pipe->set_sample_mask = nvc0_set_sample_mask;
1484
pipe->set_min_samples = nvc0_set_min_samples;
1485
pipe->set_constant_buffer = nvc0_set_constant_buffer;
1486
pipe->set_framebuffer_state = nvc0_set_framebuffer_state;
1487
pipe->set_sample_locations = nvc0_set_sample_locations;
1488
pipe->set_polygon_stipple = nvc0_set_polygon_stipple;
1489
pipe->set_scissor_states = nvc0_set_scissor_states;
1490
pipe->set_viewport_states = nvc0_set_viewport_states;
1491
pipe->set_window_rectangles = nvc0_set_window_rectangles;
1492
pipe->set_tess_state = nvc0_set_tess_state;
1493
1494
pipe->create_vertex_elements_state = nvc0_vertex_state_create;
1495
pipe->delete_vertex_elements_state = nvc0_vertex_state_delete;
1496
pipe->bind_vertex_elements_state = nvc0_vertex_state_bind;
1497
1498
pipe->set_vertex_buffers = nvc0_set_vertex_buffers;
1499
1500
pipe->create_stream_output_target = nvc0_so_target_create;
1501
pipe->stream_output_target_destroy = nvc0_so_target_destroy;
1502
pipe->set_stream_output_targets = nvc0_set_transform_feedback_targets;
1503
1504
pipe->set_global_binding = nvc0_set_global_bindings;
1505
pipe->set_compute_resources = nvc0_set_compute_resources;
1506
pipe->set_shader_images = nvc0_set_shader_images;
1507
pipe->set_shader_buffers = nvc0_set_shader_buffers;
1508
1509
nvc0->sample_mask = ~0;
1510
nvc0->min_samples = 1;
1511
nvc0->default_tess_outer[0] =
1512
nvc0->default_tess_outer[1] =
1513
nvc0->default_tess_outer[2] =
1514
nvc0->default_tess_outer[3] = 1.0;
1515
nvc0->default_tess_inner[0] =
1516
nvc0->default_tess_inner[1] = 1.0;
1517
}
1518
1519