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PojavLauncherTeam
GitHub Repository: PojavLauncherTeam/mesa
Path: blob/21.2-virgl/src/gallium/drivers/nouveau/nvc0/nvc0_video_bsp.c
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/*
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* Copyright 2011-2013 Maarten Lankhorst
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "nvc0/nvc0_video.h"
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#if NOUVEAU_VP3_DEBUG_FENCE
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static void dump_comm_bsp(struct comm *comm)
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{
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unsigned idx = comm->bsp_cur_index & 0xf;
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debug_printf("Cur seq: %x, bsp byte ofs: %x\n", comm->bsp_cur_index, comm->byte_ofs);
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debug_printf("Status: %08x, pos: %08x\n", comm->status[idx], comm->pos[idx]);
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}
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#endif
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unsigned
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nvc0_decoder_bsp_begin(struct nouveau_vp3_decoder *dec, unsigned comm_seq)
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{
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struct nouveau_bo *bsp_bo = dec->bsp_bo[comm_seq % NOUVEAU_VP3_VIDEO_QDEPTH];
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unsigned ret = 0;
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ret = nouveau_bo_map(bsp_bo, NOUVEAU_BO_WR, dec->client);
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if (ret) {
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debug_printf("map failed: %i %s\n", ret, strerror(-ret));
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return -1;
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}
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nouveau_vp3_bsp_begin(dec);
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return 2;
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}
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unsigned
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nvc0_decoder_bsp_next(struct nouveau_vp3_decoder *dec,
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unsigned comm_seq, unsigned num_buffers,
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const void *const *data, const unsigned *num_bytes)
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{
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struct nouveau_bo *bsp_bo = dec->bsp_bo[comm_seq % NOUVEAU_VP3_VIDEO_QDEPTH];
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struct nouveau_bo *inter_bo = dec->inter_bo[comm_seq & 1];
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uint32_t bsp_size = 0;
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uint32_t i = 0;
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unsigned ret = 0;
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bsp_size = dec->bsp_ptr - (char *)bsp_bo->map;
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for (i = 0; i < num_buffers; i++)
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bsp_size += num_bytes[i];
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bsp_size += 256; /* the 4 end markers */
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if (bsp_size > bsp_bo->size) {
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union nouveau_bo_config cfg;
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struct nouveau_bo *tmp_bo = NULL;
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cfg.nvc0.tile_mode = 0x10;
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cfg.nvc0.memtype = 0xfe;
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/* round up to the nearest mb */
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bsp_size += (1 << 20) - 1;
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bsp_size &= ~((1 << 20) - 1);
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ret = nouveau_bo_new(dec->client->device, NOUVEAU_BO_VRAM, 0, bsp_size, &cfg, &tmp_bo);
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if (ret) {
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debug_printf("reallocating bsp %u -> %u failed with %i\n",
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(unsigned)bsp_bo->size, bsp_size, ret);
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return -1;
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}
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ret = nouveau_bo_map(tmp_bo, NOUVEAU_BO_WR, dec->client);
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if (ret) {
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debug_printf("map failed: %i %s\n", ret, strerror(-ret));
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return -1;
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}
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/* Preserve previous buffer. */
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/* TODO: offload this copy to the GPU, as otherwise we're reading and
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* writing to VRAM. */
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memcpy(tmp_bo->map, bsp_bo->map, bsp_bo->size);
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/* update position to current chunk */
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dec->bsp_ptr = tmp_bo->map + (dec->bsp_ptr - (char *)bsp_bo->map);
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nouveau_bo_ref(NULL, &bsp_bo);
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dec->bsp_bo[comm_seq % NOUVEAU_VP3_VIDEO_QDEPTH] = bsp_bo = tmp_bo;
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}
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if (!inter_bo || bsp_bo->size * 4 > inter_bo->size) {
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union nouveau_bo_config cfg;
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struct nouveau_bo *tmp_bo = NULL;
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cfg.nvc0.tile_mode = 0x10;
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cfg.nvc0.memtype = 0xfe;
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ret = nouveau_bo_new(dec->client->device, NOUVEAU_BO_VRAM, 0, bsp_bo->size * 4, &cfg, &tmp_bo);
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if (ret) {
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debug_printf("reallocating inter %u -> %u failed with %i\n",
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inter_bo ? (unsigned)inter_bo->size : 0, (unsigned)bsp_bo->size * 4, ret);
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return -1;
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}
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ret = nouveau_bo_map(tmp_bo, NOUVEAU_BO_WR, dec->client);
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if (ret) {
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debug_printf("map failed: %i %s\n", ret, strerror(-ret));
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return -1;
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}
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nouveau_bo_ref(NULL, &inter_bo);
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dec->inter_bo[comm_seq & 1] = inter_bo = tmp_bo;
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}
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nouveau_vp3_bsp_next(dec, num_buffers, data, num_bytes);
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return 2;
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}
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unsigned
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nvc0_decoder_bsp_end(struct nouveau_vp3_decoder *dec, union pipe_desc desc,
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struct nouveau_vp3_video_buffer *target, unsigned comm_seq,
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unsigned *vp_caps, unsigned *is_ref,
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struct nouveau_vp3_video_buffer *refs[16])
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{
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struct nouveau_pushbuf *push = dec->pushbuf[0];
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enum pipe_video_format codec = u_reduce_video_profile(dec->base.profile);
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uint32_t bsp_addr, comm_addr, inter_addr;
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uint32_t slice_size, bucket_size, ring_size;
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uint32_t caps;
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struct nouveau_bo *bsp_bo = dec->bsp_bo[comm_seq % NOUVEAU_VP3_VIDEO_QDEPTH];
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struct nouveau_bo *inter_bo = dec->inter_bo[comm_seq & 1];
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struct nouveau_pushbuf_refn bo_refs[] = {
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{ bsp_bo, NOUVEAU_BO_RD | NOUVEAU_BO_VRAM },
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{ inter_bo, NOUVEAU_BO_WR | NOUVEAU_BO_VRAM },
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#if NOUVEAU_VP3_DEBUG_FENCE
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{ dec->fence_bo, NOUVEAU_BO_WR | NOUVEAU_BO_GART },
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#endif
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{ dec->bitplane_bo, NOUVEAU_BO_RDWR | NOUVEAU_BO_VRAM },
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};
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int num_refs = ARRAY_SIZE(bo_refs);
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if (!dec->bitplane_bo)
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num_refs--;
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caps = nouveau_vp3_bsp_end(dec, desc);
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nouveau_vp3_vp_caps(dec, desc, target, comm_seq, vp_caps, is_ref, refs);
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nouveau_pushbuf_space(push, 32, num_refs, 0);
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nouveau_pushbuf_refn(push, bo_refs, num_refs);
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bsp_addr = bsp_bo->offset >> 8;
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inter_addr = inter_bo->offset >> 8;
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#if NOUVEAU_VP3_DEBUG_FENCE
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memset(dec->comm, 0, 0x200);
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comm_addr = (dec->fence_bo->offset + COMM_OFFSET) >> 8;
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#else
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comm_addr = bsp_addr + (COMM_OFFSET>>8);
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#endif
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BEGIN_NVC0(push, SUBC_BSP(0x700), 5);
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PUSH_DATA (push, caps); // 700 cmd
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PUSH_DATA (push, bsp_addr + 1); // 704 strparm_bsp
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PUSH_DATA (push, bsp_addr + 7); // 708 str addr
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PUSH_DATA (push, comm_addr); // 70c comm
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PUSH_DATA (push, comm_seq); // 710 seq
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if (codec != PIPE_VIDEO_FORMAT_MPEG4_AVC) {
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u32 bitplane_addr;
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bitplane_addr = dec->bitplane_bo->offset >> 8;
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nouveau_vp3_inter_sizes(dec, 1, &slice_size, &bucket_size, &ring_size);
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BEGIN_NVC0(push, SUBC_BSP(0x400), 6);
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PUSH_DATA (push, bsp_addr); // 400 picparm addr
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PUSH_DATA (push, inter_addr); // 404 interparm addr
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PUSH_DATA (push, inter_addr + slice_size + bucket_size); // 408 interdata addr
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PUSH_DATA (push, ring_size << 8); // 40c interdata_size
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PUSH_DATA (push, bitplane_addr); // 410 BITPLANE_DATA
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PUSH_DATA (push, 0x400); // 414 BITPLANE_DATA_SIZE
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} else {
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nouveau_vp3_inter_sizes(dec, desc.h264->slice_count, &slice_size, &bucket_size, &ring_size);
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BEGIN_NVC0(push, SUBC_BSP(0x400), 8);
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PUSH_DATA (push, bsp_addr); // 400 picparm addr
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PUSH_DATA (push, inter_addr); // 404 interparm addr
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PUSH_DATA (push, slice_size << 8); // 408 interparm size?
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PUSH_DATA (push, inter_addr + slice_size + bucket_size); // 40c interdata addr
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PUSH_DATA (push, ring_size << 8); // 410 interdata size
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PUSH_DATA (push, inter_addr + slice_size); // 414 bucket?
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PUSH_DATA (push, bucket_size << 8); // 418 bucket size? unshifted..
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PUSH_DATA (push, 0); // 41c targets
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// TODO: Double check 414 / 418 with nvidia trace
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}
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#if NOUVEAU_VP3_DEBUG_FENCE
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BEGIN_NVC0(push, SUBC_BSP(0x240), 3);
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PUSH_DATAh(push, dec->fence_bo->offset);
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PUSH_DATA (push, dec->fence_bo->offset);
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PUSH_DATA (push, dec->fence_seq);
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BEGIN_NVC0(push, SUBC_BSP(0x300), 1);
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PUSH_DATA (push, 1);
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PUSH_KICK (push);
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{
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unsigned spin = 0;
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do {
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usleep(100);
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if ((spin++ & 0xff) == 0xff) {
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debug_printf("b%u: %u\n", dec->fence_seq, dec->fence_map[0]);
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dump_comm_bsp(dec->comm);
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}
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} while (dec->fence_seq > dec->fence_map[0]);
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}
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dump_comm_bsp(dec->comm);
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return dec->comm->status[comm_seq & 0xf];
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#else
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BEGIN_NVC0(push, SUBC_BSP(0x300), 1);
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PUSH_DATA (push, 0);
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PUSH_KICK (push);
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return 2;
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#endif
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}
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