CoCalc -- radeon

GitHub Repository: PojavLauncherTeam/mesa
Path: blob/21.2-virgl/src/gallium/drivers/r300/compiler/radeon_opcodes.c
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/*
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 * Copyright (C) 2009 Nicolai Haehnle.
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 *
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 * All Rights Reserved.
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining
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 * a copy of this software and associated documentation files (the
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 * "Software"), to deal in the Software without restriction, including
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 * without limitation the rights to use, copy, modify, merge, publish,
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 * distribute, sublicense, and/or sell copies of the Software, and to
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 * permit persons to whom the Software is furnished to do so, subject to
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 * the following conditions:
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 *
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 * The above copyright notice and this permission notice (including the
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 * next paragraph) shall be included in all copies or substantial
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 * portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
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 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
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 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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 *
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 */
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#include "radeon_opcodes.h"
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#include "radeon_program.h"
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#include "radeon_program_constants.h"
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33
#include "util/compiler.h"
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35
struct rc_opcode_info rc_opcodes[MAX_RC_OPCODE] = {
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	{
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		.Opcode = RC_OPCODE_NOP,
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		.Name = "NOP"
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	},
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	{
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		.Opcode = RC_OPCODE_ILLEGAL_OPCODE,
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		.Name = "ILLEGAL OPCODE"
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	},
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	{
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		.Opcode = RC_OPCODE_ABS,
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		.Name = "ABS",
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		.NumSrcRegs = 1,
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		.HasDstReg = 1,
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		.IsComponentwise = 1
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	},
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	{
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		.Opcode = RC_OPCODE_ADD,
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		.Name = "ADD",
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		.NumSrcRegs = 2,
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		.HasDstReg = 1,
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		.IsComponentwise = 1
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	},
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	{
59
		.Opcode = RC_OPCODE_ARL,
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		.Name = "ARL",
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		.NumSrcRegs = 1,
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		.HasDstReg = 1
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	},
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	{
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		.Opcode = RC_OPCODE_ARR,
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		.Name = "ARR",
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		.NumSrcRegs = 1,
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		.HasDstReg = 1
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	},
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	{
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		.Opcode = RC_OPCODE_CEIL,
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		.Name = "CEIL",
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		.NumSrcRegs = 1,
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		.HasDstReg = 1,
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		.IsComponentwise = 1
76
	},
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	{
78
		.Opcode = RC_OPCODE_CLAMP,
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		.Name = "CLAMP",
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		.NumSrcRegs = 3,
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		.HasDstReg = 1,
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		.IsComponentwise = 1
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	},
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	{
85
		.Opcode = RC_OPCODE_CMP,
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		.Name = "CMP",
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		.NumSrcRegs = 3,
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		.HasDstReg = 1,
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		.IsComponentwise = 1
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	},
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	{
92
		.Opcode = RC_OPCODE_CND,
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		.Name = "CND",
94
		.NumSrcRegs = 3,
95
		.HasDstReg = 1,
96
		.IsComponentwise = 1
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	},
98
	{
99
		.Opcode = RC_OPCODE_COS,
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		.Name = "COS",
101
		.NumSrcRegs = 1,
102
		.HasDstReg = 1,
103
		.IsStandardScalar = 1
104
	},
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	{
106
		.Opcode = RC_OPCODE_DDX,
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		.Name = "DDX",
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		.NumSrcRegs = 2,
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		.HasDstReg = 1,
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		.IsComponentwise = 1
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	},
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	{
113
		.Opcode = RC_OPCODE_DDY,
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		.Name = "DDY",
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		.NumSrcRegs = 2,
116
		.HasDstReg = 1,
117
		.IsComponentwise = 1
118
	},
119
	{
120
		.Opcode = RC_OPCODE_DP2,
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		.Name = "DP2",
122
		.NumSrcRegs = 2,
123
		.HasDstReg = 1
124
	},
125
	{
126
		.Opcode = RC_OPCODE_DP3,
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		.Name = "DP3",
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		.NumSrcRegs = 2,
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		.HasDstReg = 1
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	},
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	{
132
		.Opcode = RC_OPCODE_DP4,
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		.Name = "DP4",
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		.NumSrcRegs = 2,
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		.HasDstReg = 1
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	},
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	{
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		.Opcode = RC_OPCODE_DPH,
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		.Name = "DPH",
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		.NumSrcRegs = 2,
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		.HasDstReg = 1
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	},
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	{
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		.Opcode = RC_OPCODE_DST,
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		.Name = "DST",
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		.NumSrcRegs = 2,
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		.HasDstReg = 1
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	},
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	{
150
		.Opcode = RC_OPCODE_EX2,
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		.Name = "EX2",
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		.NumSrcRegs = 1,
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		.HasDstReg = 1,
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		.IsStandardScalar = 1
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	},
156
	{
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		.Opcode = RC_OPCODE_EXP,
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		.Name = "EXP",
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		.NumSrcRegs = 1,
160
		.HasDstReg = 1
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	},
162
	{
163
		.Opcode = RC_OPCODE_FLR,
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		.Name = "FLR",
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		.NumSrcRegs = 1,
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		.HasDstReg = 1,
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		.IsComponentwise = 1
168
	},
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	{
170
		.Opcode = RC_OPCODE_FRC,
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		.Name = "FRC",
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		.NumSrcRegs = 1,
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		.HasDstReg = 1,
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		.IsComponentwise = 1
175
	},
176
	{
177
		.Opcode = RC_OPCODE_KIL,
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		.Name = "KIL",
179
		.NumSrcRegs = 1
180
	},
181
	{
182
		.Opcode = RC_OPCODE_LG2,
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		.Name = "LG2",
184
		.NumSrcRegs = 1,
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		.HasDstReg = 1,
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		.IsStandardScalar = 1
187
	},
188
	{
189
		.Opcode = RC_OPCODE_LIT,
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		.Name = "LIT",
191
		.NumSrcRegs = 1,
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		.HasDstReg = 1
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	},
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	{
195
		.Opcode = RC_OPCODE_LOG,
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		.Name = "LOG",
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		.NumSrcRegs = 1,
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		.HasDstReg = 1
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	},
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	{
201
		.Opcode = RC_OPCODE_LRP,
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		.Name = "LRP",
203
		.NumSrcRegs = 3,
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		.HasDstReg = 1,
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		.IsComponentwise = 1
206
	},
207
	{
208
		.Opcode = RC_OPCODE_MAD,
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		.Name = "MAD",
210
		.NumSrcRegs = 3,
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		.HasDstReg = 1,
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		.IsComponentwise = 1
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	},
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	{
215
		.Opcode = RC_OPCODE_MAX,
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		.Name = "MAX",
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		.NumSrcRegs = 2,
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		.HasDstReg = 1,
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		.IsComponentwise = 1
220
	},
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	{
222
		.Opcode = RC_OPCODE_MIN,
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		.Name = "MIN",
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		.NumSrcRegs = 2,
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		.HasDstReg = 1,
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		.IsComponentwise = 1
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	},
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	{
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		.Opcode = RC_OPCODE_MOV,
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		.Name = "MOV",
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		.NumSrcRegs = 1,
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		.HasDstReg = 1,
233
		.IsComponentwise = 1
234
	},
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	{
236
		.Opcode = RC_OPCODE_MUL,
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		.Name = "MUL",
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		.NumSrcRegs = 2,
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		.HasDstReg = 1,
240
		.IsComponentwise = 1
241
	},
242
	{
243
		.Opcode = RC_OPCODE_POW,
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		.Name = "POW",
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		.NumSrcRegs = 2,
246
		.HasDstReg = 1,
247
		.IsStandardScalar = 1
248
	},
249
	{
250
		.Opcode = RC_OPCODE_RCP,
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		.Name = "RCP",
252
		.NumSrcRegs = 1,
253
		.HasDstReg = 1,
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		.IsStandardScalar = 1
255
	},
256
	{
257
		.Opcode = RC_OPCODE_ROUND,
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		.Name = "ROUND",
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		.NumSrcRegs = 1,
260
		.HasDstReg = 1,
261
		.IsComponentwise = 1
262
	},
263
	{
264
		.Opcode = RC_OPCODE_RSQ,
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		.Name = "RSQ",
266
		.NumSrcRegs = 1,
267
		.HasDstReg = 1,
268
		.IsStandardScalar = 1
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	},
270
	{
271
		.Opcode = RC_OPCODE_SCS,
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		.Name = "SCS",
273
		.NumSrcRegs = 1,
274
		.HasDstReg = 1
275
	},
276
	{
277
		.Opcode = RC_OPCODE_SEQ,
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		.Name = "SEQ",
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		.NumSrcRegs = 2,
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		.HasDstReg = 1,
281
		.IsComponentwise = 1
282
	},
283
	{
284
		.Opcode = RC_OPCODE_SFL,
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		.Name = "SFL",
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		.NumSrcRegs = 0,
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		.HasDstReg = 1,
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		.IsComponentwise = 1
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	},
290
	{
291
		.Opcode = RC_OPCODE_SGE,
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		.Name = "SGE",
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		.NumSrcRegs = 2,
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		.HasDstReg = 1,
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		.IsComponentwise = 1
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	},
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	{
298
		.Opcode = RC_OPCODE_SGT,
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		.Name = "SGT",
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		.NumSrcRegs = 2,
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		.HasDstReg = 1,
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		.IsComponentwise = 1
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	},
304
	{
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		.Opcode = RC_OPCODE_SIN,
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		.Name = "SIN",
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		.NumSrcRegs = 1,
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		.HasDstReg = 1,
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		.IsStandardScalar = 1
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	},
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	{
312
		.Opcode = RC_OPCODE_SLE,
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		.Name = "SLE",
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		.NumSrcRegs = 2,
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		.HasDstReg = 1,
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		.IsComponentwise = 1
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	},
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	{
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		.Opcode = RC_OPCODE_SLT,
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		.Name = "SLT",
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		.NumSrcRegs = 2,
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		.HasDstReg = 1,
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		.IsComponentwise = 1
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	},
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	{
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		.Opcode = RC_OPCODE_SNE,
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		.Name = "SNE",
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		.NumSrcRegs = 2,
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		.HasDstReg = 1,
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		.IsComponentwise = 1
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	},
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	{
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		.Opcode = RC_OPCODE_SSG,
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		.Name = "SSG",
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		.NumSrcRegs = 1,
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		.HasDstReg = 1,
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		.IsComponentwise = 1
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	},
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	{
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		.Opcode = RC_OPCODE_SUB,
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		.Name = "SUB",
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		.NumSrcRegs = 2,
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		.HasDstReg = 1,
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		.IsComponentwise = 1
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	},
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	{
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		.Opcode = RC_OPCODE_SWZ,
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		.Name = "SWZ",
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		.NumSrcRegs = 1,
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		.HasDstReg = 1,
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		.IsComponentwise = 1
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	},
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	{
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		.Opcode = RC_OPCODE_TRUNC,
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		.Name = "TRUNC",
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		.NumSrcRegs = 1,
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		.HasDstReg = 1,
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		.IsComponentwise = 1
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	},
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	{
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		.Opcode = RC_OPCODE_XPD,
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		.Name = "XPD",
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		.NumSrcRegs = 2,
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		.HasDstReg = 1
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	},
366
	{
367
		.Opcode = RC_OPCODE_TEX,
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		.Name = "TEX",
369
		.HasTexture = 1,
370
		.NumSrcRegs = 1,
371
		.HasDstReg = 1
372
	},
373
	{
374
		.Opcode = RC_OPCODE_TXB,
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		.Name = "TXB",
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		.HasTexture = 1,
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		.NumSrcRegs = 1,
378
		.HasDstReg = 1
379
	},
380
	{
381
		.Opcode = RC_OPCODE_TXD,
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		.Name = "TXD",
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		.HasTexture = 1,
384
		.NumSrcRegs = 3,
385
		.HasDstReg = 1
386
	},
387
	{
388
		.Opcode = RC_OPCODE_TXL,
389
		.Name = "TXL",
390
		.HasTexture = 1,
391
		.NumSrcRegs = 1,
392
		.HasDstReg = 1
393
	},
394
	{
395
		.Opcode = RC_OPCODE_TXP,
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		.Name = "TXP",
397
		.HasTexture = 1,
398
		.NumSrcRegs = 1,
399
		.HasDstReg = 1
400
	},
401
	{
402
		.Opcode = RC_OPCODE_IF,
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		.Name = "IF",
404
		.IsFlowControl = 1,
405
		.NumSrcRegs = 1
406
	},
407
	{
408
		.Opcode = RC_OPCODE_ELSE,
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		.Name = "ELSE",
410
		.IsFlowControl = 1,
411
		.NumSrcRegs = 0
412
	},
413
	{
414
		.Opcode = RC_OPCODE_ENDIF,
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		.Name = "ENDIF",
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		.IsFlowControl = 1,
417
		.NumSrcRegs = 0
418
	},
419
	{
420
		.Opcode = RC_OPCODE_BGNLOOP,
421
		.Name = "BGNLOOP",
422
		.IsFlowControl = 1,
423
		.NumSrcRegs = 0
424
	},
425
	{
426
		.Opcode = RC_OPCODE_BRK,
427
		.Name = "BRK",
428
		.IsFlowControl = 1,
429
		.NumSrcRegs = 0
430
	},
431
	{
432
		.Opcode = RC_OPCODE_ENDLOOP,
433
		.Name = "ENDLOOP",
434
		.IsFlowControl = 1,
435
		.NumSrcRegs = 0,
436
	},
437
	{
438
		.Opcode = RC_OPCODE_CONT,
439
		.Name = "CONT",
440
		.IsFlowControl = 1,
441
		.NumSrcRegs = 0
442
	},
443
	{
444
		.Opcode = RC_OPCODE_REPL_ALPHA,
445
		.Name = "REPL_ALPHA",
446
		.HasDstReg = 1
447
	},
448
	{
449
		.Opcode = RC_OPCODE_BEGIN_TEX,
450
		.Name = "BEGIN_TEX"
451
	},
452
	{
453
		.Opcode = RC_OPCODE_KILP,
454
		.Name = "KILP",
455
	},
456
	{
457
		.Opcode = RC_ME_PRED_SEQ,
458
		.Name = "ME_PRED_SEQ",
459
		.NumSrcRegs = 1,
460
		.HasDstReg = 1
461
	},
462
	{
463
		.Opcode = RC_ME_PRED_SGT,
464
		.Name = "ME_PRED_SGT",
465
		.NumSrcRegs = 1,
466
		.HasDstReg = 1
467
	},
468
	{
469
		.Opcode = RC_ME_PRED_SGE,
470
		.Name = "ME_PRED_SGE",
471
		.NumSrcRegs = 1,
472
		.HasDstReg = 1
473
	},
474
	{
475
		.Opcode = RC_ME_PRED_SNEQ,
476
		.Name = "ME_PRED_SNEQ",
477
		.NumSrcRegs = 1,
478
		.HasDstReg = 1
479
	},
480
	{
481
		.Opcode = RC_ME_PRED_SET_CLR,
482
		.Name = "ME_PRED_SET_CLEAR",
483
		.NumSrcRegs = 1,
484
		.HasDstReg = 1
485
	},
486
	{
487
		.Opcode = RC_ME_PRED_SET_INV,
488
		.Name = "ME_PRED_SET_INV",
489
		.NumSrcRegs = 1,
490
		.HasDstReg = 1
491
	},
492
	{
493
		.Opcode = RC_ME_PRED_SET_POP,
494
		.Name = "ME_PRED_SET_POP",
495
		.NumSrcRegs = 1,
496
		.HasDstReg = 1
497
	},
498
	{
499
		.Opcode = RC_ME_PRED_SET_RESTORE,
500
		.Name = "ME_PRED_SET_RESTORE",
501
		.NumSrcRegs = 1,
502
		.HasDstReg = 1
503
	},
504
	{
505
		.Opcode = RC_VE_PRED_SEQ_PUSH,
506
		.Name = "VE_PRED_SEQ_PUSH",
507
		.NumSrcRegs = 2,
508
		.HasDstReg = 1
509
	},
510
	{
511
		.Opcode = RC_VE_PRED_SGT_PUSH,
512
		.Name = "VE_PRED_SGT_PUSH",
513
		.NumSrcRegs = 2,
514
		.HasDstReg = 1
515
	},
516
	{
517
		.Opcode = RC_VE_PRED_SGE_PUSH,
518
		.Name = "VE_PRED_SGE_PUSH",
519
		.NumSrcRegs = 2,
520
		.HasDstReg = 1
521
	},
522
	{
523
		.Opcode = RC_VE_PRED_SNEQ_PUSH,
524
		.Name = "VE_PRED_SNEQ_PUSH",
525
		.NumSrcRegs = 2,
526
		.HasDstReg = 1
527
	}
528
};
529

530
void rc_compute_sources_for_writemask(
531
		const struct rc_instruction *inst,
532
		unsigned int writemask,
533
		unsigned int *srcmasks)
534
{
535
	const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode);
536
	srcmasks[0] = 0;
537
	srcmasks[1] = 0;
538
	srcmasks[2] = 0;
539

540
	if (opcode->Opcode == RC_OPCODE_KIL)
541
		srcmasks[0] |= RC_MASK_XYZW;
542
	else if (opcode->Opcode == RC_OPCODE_IF)
543
		srcmasks[0] |= RC_MASK_X;
544

545
	if (!writemask)
546
		return;
547

548
	if (opcode->IsComponentwise) {
549
		for(unsigned int src = 0; src < opcode->NumSrcRegs; ++src)
550
			srcmasks[src] |= writemask;
551
	} else if (opcode->IsStandardScalar) {
552
		for(unsigned int src = 0; src < opcode->NumSrcRegs; ++src)
553
			srcmasks[src] |= writemask;
554
	} else {
555
		switch(opcode->Opcode) {
556
		case RC_OPCODE_ARL:
557
		case RC_OPCODE_ARR:
558
			srcmasks[0] |= RC_MASK_X;
559
			break;
560
		case RC_OPCODE_DP2:
561
			srcmasks[0] |= RC_MASK_XY;
562
			srcmasks[1] |= RC_MASK_XY;
563
			break;
564
		case RC_OPCODE_DP3:
565
		case RC_OPCODE_XPD:
566
			srcmasks[0] |= RC_MASK_XYZ;
567
			srcmasks[1] |= RC_MASK_XYZ;
568
			break;
569
		case RC_OPCODE_DP4:
570
			srcmasks[0] |= RC_MASK_XYZW;
571
			srcmasks[1] |= RC_MASK_XYZW;
572
			break;
573
		case RC_OPCODE_DPH:
574
			srcmasks[0] |= RC_MASK_XYZ;
575
			srcmasks[1] |= RC_MASK_XYZW;
576
			break;
577
		case RC_OPCODE_TXB:
578
		case RC_OPCODE_TXP:
579
		case RC_OPCODE_TXL:
580
			srcmasks[0] |= RC_MASK_W;
581
			FALLTHROUGH;
582
		case RC_OPCODE_TEX:
583
			switch (inst->U.I.TexSrcTarget) {
584
				case RC_TEXTURE_1D:
585
					srcmasks[0] |= RC_MASK_X;
586
					break;
587
				case RC_TEXTURE_2D:
588
				case RC_TEXTURE_RECT:
589
				case RC_TEXTURE_1D_ARRAY:
590
					srcmasks[0] |= RC_MASK_XY;
591
					break;
592
				case RC_TEXTURE_3D:
593
				case RC_TEXTURE_CUBE:
594
				case RC_TEXTURE_2D_ARRAY:
595
					srcmasks[0] |= RC_MASK_XYZ;
596
					break;
597
			}
598
			break;
599
		case RC_OPCODE_TXD:
600
			switch (inst->U.I.TexSrcTarget) {
601
				case RC_TEXTURE_1D_ARRAY:
602
					srcmasks[0] |= RC_MASK_Y;
603
					FALLTHROUGH;
604
				case RC_TEXTURE_1D:
605
					srcmasks[0] |= RC_MASK_X;
606
					srcmasks[1] |= RC_MASK_X;
607
					srcmasks[2] |= RC_MASK_X;
608
					break;
609
				case RC_TEXTURE_2D_ARRAY:
610
					srcmasks[0] |= RC_MASK_Z;
611
					FALLTHROUGH;
612
				case RC_TEXTURE_2D:
613
				case RC_TEXTURE_RECT:
614
					srcmasks[0] |= RC_MASK_XY;
615
					srcmasks[1] |= RC_MASK_XY;
616
					srcmasks[2] |= RC_MASK_XY;
617
					break;
618
				case RC_TEXTURE_3D:
619
				case RC_TEXTURE_CUBE:
620
					srcmasks[0] |= RC_MASK_XYZ;
621
					srcmasks[1] |= RC_MASK_XYZ;
622
					srcmasks[2] |= RC_MASK_XYZ;
623
					break;
624
			}
625
			break;
626
		case RC_OPCODE_DST:
627
			srcmasks[0] |= RC_MASK_Y | RC_MASK_Z;
628
			srcmasks[1] |= RC_MASK_Y | RC_MASK_W;
629
			break;
630
		case RC_OPCODE_EXP:
631
		case RC_OPCODE_LOG:
632
			srcmasks[0] |= RC_MASK_XY;
633
			break;
634
		case RC_OPCODE_LIT:
635
			srcmasks[0] |= RC_MASK_X | RC_MASK_Y | RC_MASK_W;
636
			break;
637
		default:
638
			break;
639
		}
640
	}
641
}
642

643
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