Book a Demo!
CoCalc Logo Icon
StoreFeaturesDocsShareSupportNewsAboutPoliciesSign UpSign In
PojavLauncherTeam
GitHub Repository: PojavLauncherTeam/mesa
Path: blob/21.2-virgl/src/gallium/drivers/r300/r300_screen.c
4570 views
1
/*
2
* Copyright 2008 Corbin Simpson <[email protected]>
3
* Copyright 2010 Marek Olšák <[email protected]>
4
*
5
* Permission is hereby granted, free of charge, to any person obtaining a
6
* copy of this software and associated documentation files (the "Software"),
7
* to deal in the Software without restriction, including without limitation
8
* on the rights to use, copy, modify, merge, publish, distribute, sub
9
* license, and/or sell copies of the Software, and to permit persons to whom
10
* the Software is furnished to do so, subject to the following conditions:
11
*
12
* The above copyright notice and this permission notice (including the next
13
* paragraph) shall be included in all copies or substantial portions of the
14
* Software.
15
*
16
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18
* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19
* THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21
* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22
* USE OR OTHER DEALINGS IN THE SOFTWARE. */
23
24
#include "util/format/u_format.h"
25
#include "util/format/u_format_s3tc.h"
26
#include "util/u_screen.h"
27
#include "util/u_memory.h"
28
#include "util/os_time.h"
29
#include "vl/vl_decoder.h"
30
#include "vl/vl_video_buffer.h"
31
32
#include "r300_context.h"
33
#include "r300_texture.h"
34
#include "r300_screen_buffer.h"
35
#include "r300_state_inlines.h"
36
#include "r300_public.h"
37
38
#include "draw/draw_context.h"
39
40
/* Return the identifier behind whom the brave coders responsible for this
41
* amalgamation of code, sweat, and duct tape, routinely obscure their names.
42
*
43
* ...I should have just put "Corbin Simpson", but I'm not that cool.
44
*
45
* (Or egotistical. Yet.) */
46
static const char* r300_get_vendor(struct pipe_screen* pscreen)
47
{
48
return "X.Org R300 Project";
49
}
50
51
static const char* r300_get_device_vendor(struct pipe_screen* pscreen)
52
{
53
return "ATI";
54
}
55
56
static const char* chip_families[] = {
57
"unknown",
58
"ATI R300",
59
"ATI R350",
60
"ATI RV350",
61
"ATI RV370",
62
"ATI RV380",
63
"ATI RS400",
64
"ATI RC410",
65
"ATI RS480",
66
"ATI R420",
67
"ATI R423",
68
"ATI R430",
69
"ATI R480",
70
"ATI R481",
71
"ATI RV410",
72
"ATI RS600",
73
"ATI RS690",
74
"ATI RS740",
75
"ATI RV515",
76
"ATI R520",
77
"ATI RV530",
78
"ATI R580",
79
"ATI RV560",
80
"ATI RV570"
81
};
82
83
static const char* r300_get_family_name(struct r300_screen* r300screen)
84
{
85
return chip_families[r300screen->caps.family];
86
}
87
88
static const char* r300_get_name(struct pipe_screen* pscreen)
89
{
90
struct r300_screen* r300screen = r300_screen(pscreen);
91
92
return r300_get_family_name(r300screen);
93
}
94
95
static void r300_disk_cache_create(struct r300_screen* r300screen)
96
{
97
struct mesa_sha1 ctx;
98
unsigned char sha1[20];
99
char cache_id[20 * 2 + 1];
100
101
_mesa_sha1_init(&ctx);
102
if (!disk_cache_get_function_identifier(r300_disk_cache_create,
103
&ctx))
104
return;
105
106
_mesa_sha1_final(&ctx, sha1);
107
disk_cache_format_hex_id(cache_id, sha1, 20 * 2);
108
109
r300screen->disk_shader_cache =
110
disk_cache_create(r300_get_family_name(r300screen),
111
cache_id,
112
r300screen->debug);
113
}
114
115
static struct disk_cache* r300_get_disk_shader_cache(struct pipe_screen* pscreen)
116
{
117
struct r300_screen* r300screen = r300_screen(pscreen);
118
return r300screen->disk_shader_cache;
119
}
120
121
static int r300_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
122
{
123
struct r300_screen* r300screen = r300_screen(pscreen);
124
boolean is_r500 = r300screen->caps.is_r500;
125
126
switch (param) {
127
/* Supported features (boolean caps). */
128
case PIPE_CAP_NPOT_TEXTURES:
129
case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
130
case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
131
case PIPE_CAP_ANISOTROPIC_FILTER:
132
case PIPE_CAP_POINT_SPRITE:
133
case PIPE_CAP_OCCLUSION_QUERY:
134
case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
135
case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
136
case PIPE_CAP_BLEND_EQUATION_SEPARATE:
137
case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
138
case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
139
case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
140
case PIPE_CAP_CONDITIONAL_RENDER:
141
case PIPE_CAP_TEXTURE_BARRIER:
142
case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
143
case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
144
case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
145
case PIPE_CAP_CLIP_HALFZ:
146
case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
147
return 1;
148
149
case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
150
return R300_BUFFER_ALIGNMENT;
151
152
case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
153
return 16;
154
155
case PIPE_CAP_GLSL_FEATURE_LEVEL:
156
case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
157
return 120;
158
159
/* r300 cannot do swizzling of compressed textures. Supported otherwise. */
160
case PIPE_CAP_TEXTURE_SWIZZLE:
161
return r300screen->caps.dxtc_swizzle;
162
163
/* We don't support color clamping on r500, so that we can use color
164
* interpolators for generic varyings. */
165
case PIPE_CAP_VERTEX_COLOR_CLAMPED:
166
return !is_r500;
167
168
/* Supported on r500 only. */
169
case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
170
case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
171
case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
172
case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
173
case PIPE_CAP_VERTEX_SHADER_SATURATE:
174
return is_r500 ? 1 : 0;
175
176
case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
177
return 0;
178
case PIPE_CAP_SHAREABLE_SHADERS:
179
return 0;
180
181
case PIPE_CAP_MAX_GS_INVOCATIONS:
182
return 32;
183
case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
184
return 1 << 27;
185
186
/* SWTCL-only features. */
187
case PIPE_CAP_PRIMITIVE_RESTART:
188
case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX:
189
case PIPE_CAP_USER_VERTEX_BUFFERS:
190
case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
191
return !r300screen->caps.has_tcl;
192
193
/* HWTCL-only features / limitations. */
194
case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
195
case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
196
case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
197
return r300screen->caps.has_tcl;
198
199
/* Texturing. */
200
case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
201
return is_r500 ? 4096 : 2048;
202
case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
203
case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
204
/* 13 == 4096, 12 == 2048 */
205
return is_r500 ? 13 : 12;
206
207
/* Render targets. */
208
case PIPE_CAP_MAX_RENDER_TARGETS:
209
return 4;
210
case PIPE_CAP_ENDIANNESS:
211
return PIPE_ENDIAN_LITTLE;
212
213
case PIPE_CAP_MAX_VIEWPORTS:
214
return 1;
215
216
case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
217
return 2048;
218
219
case PIPE_CAP_MAX_VARYINGS:
220
return 10;
221
222
case PIPE_CAP_VENDOR_ID:
223
return 0x1002;
224
case PIPE_CAP_DEVICE_ID:
225
return r300screen->info.pci_id;
226
case PIPE_CAP_ACCELERATED:
227
return 1;
228
case PIPE_CAP_VIDEO_MEMORY:
229
return r300screen->info.vram_size >> 20;
230
case PIPE_CAP_UMA:
231
return 0;
232
case PIPE_CAP_PCI_GROUP:
233
return r300screen->info.pci_domain;
234
case PIPE_CAP_PCI_BUS:
235
return r300screen->info.pci_bus;
236
case PIPE_CAP_PCI_DEVICE:
237
return r300screen->info.pci_dev;
238
case PIPE_CAP_PCI_FUNCTION:
239
return r300screen->info.pci_func;
240
default:
241
return u_pipe_screen_get_param_defaults(pscreen, param);
242
}
243
}
244
245
static int r300_get_shader_param(struct pipe_screen *pscreen,
246
enum pipe_shader_type shader,
247
enum pipe_shader_cap param)
248
{
249
struct r300_screen* r300screen = r300_screen(pscreen);
250
boolean is_r400 = r300screen->caps.is_r400;
251
boolean is_r500 = r300screen->caps.is_r500;
252
253
switch (shader) {
254
case PIPE_SHADER_FRAGMENT:
255
switch (param)
256
{
257
case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
258
return is_r500 || is_r400 ? 512 : 96;
259
case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
260
return is_r500 || is_r400 ? 512 : 64;
261
case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
262
return is_r500 || is_r400 ? 512 : 32;
263
case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
264
return is_r500 ? 511 : 4;
265
case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
266
return is_r500 ? 64 : 0; /* Actually unlimited on r500. */
267
/* Fragment shader limits. */
268
case PIPE_SHADER_CAP_MAX_INPUTS:
269
/* 2 colors + 8 texcoords are always supported
270
* (minus fog and wpos).
271
*
272
* R500 has the ability to turn 3rd and 4th color into
273
* additional texcoords but there is no two-sided color
274
* selection then. However the facing bit can be used instead. */
275
return 10;
276
case PIPE_SHADER_CAP_MAX_OUTPUTS:
277
return 4;
278
case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
279
return (is_r500 ? 256 : 32) * sizeof(float[4]);
280
case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
281
case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
282
return 1;
283
case PIPE_SHADER_CAP_MAX_TEMPS:
284
return is_r500 ? 128 : is_r400 ? 64 : 32;
285
case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
286
case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
287
return r300screen->caps.num_tex_units;
288
case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
289
case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
290
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
291
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
292
case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
293
case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
294
case PIPE_SHADER_CAP_SUBROUTINES:
295
case PIPE_SHADER_CAP_INTEGERS:
296
case PIPE_SHADER_CAP_INT64_ATOMICS:
297
case PIPE_SHADER_CAP_FP16:
298
case PIPE_SHADER_CAP_FP16_DERIVATIVES:
299
case PIPE_SHADER_CAP_FP16_CONST_BUFFERS:
300
case PIPE_SHADER_CAP_INT16:
301
case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
302
case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
303
case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
304
case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
305
case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
306
case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
307
case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
308
case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
309
case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
310
case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
311
case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
312
return 0;
313
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
314
return 32;
315
case PIPE_SHADER_CAP_PREFERRED_IR:
316
return PIPE_SHADER_IR_TGSI;
317
case PIPE_SHADER_CAP_SUPPORTED_IRS:
318
return 1 << PIPE_SHADER_IR_TGSI;
319
}
320
break;
321
case PIPE_SHADER_VERTEX:
322
switch (param)
323
{
324
case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
325
case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
326
case PIPE_SHADER_CAP_SUBROUTINES:
327
return 0;
328
default:;
329
}
330
331
if (!r300screen->caps.has_tcl) {
332
switch (param) {
333
case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
334
case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
335
return 0;
336
default:
337
return draw_get_shader_param(shader, param);
338
}
339
}
340
341
switch (param)
342
{
343
case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
344
case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
345
return is_r500 ? 1024 : 256;
346
case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
347
return is_r500 ? 4 : 0; /* For loops; not sure about conditionals. */
348
case PIPE_SHADER_CAP_MAX_INPUTS:
349
return 16;
350
case PIPE_SHADER_CAP_MAX_OUTPUTS:
351
return 10;
352
case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
353
return 256 * sizeof(float[4]);
354
case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
355
return 1;
356
case PIPE_SHADER_CAP_MAX_TEMPS:
357
return 32;
358
case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
359
case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
360
return 1;
361
case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
362
case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
363
case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
364
case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
365
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
366
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
367
case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
368
case PIPE_SHADER_CAP_SUBROUTINES:
369
case PIPE_SHADER_CAP_INTEGERS:
370
case PIPE_SHADER_CAP_FP16:
371
case PIPE_SHADER_CAP_FP16_CONST_BUFFERS:
372
case PIPE_SHADER_CAP_FP16_DERIVATIVES:
373
case PIPE_SHADER_CAP_INT16:
374
case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
375
case PIPE_SHADER_CAP_INT64_ATOMICS:
376
case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
377
case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
378
case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
379
case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
380
case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
381
case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
382
case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
383
case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
384
case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
385
case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
386
case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
387
case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
388
return 0;
389
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
390
return 32;
391
case PIPE_SHADER_CAP_PREFERRED_IR:
392
return PIPE_SHADER_IR_TGSI;
393
case PIPE_SHADER_CAP_SUPPORTED_IRS:
394
return 1 << PIPE_SHADER_IR_TGSI;
395
}
396
break;
397
default:
398
; /* nothing */
399
}
400
return 0;
401
}
402
403
static float r300_get_paramf(struct pipe_screen* pscreen,
404
enum pipe_capf param)
405
{
406
struct r300_screen* r300screen = r300_screen(pscreen);
407
408
switch (param) {
409
case PIPE_CAPF_MAX_LINE_WIDTH:
410
case PIPE_CAPF_MAX_LINE_WIDTH_AA:
411
case PIPE_CAPF_MAX_POINT_WIDTH:
412
case PIPE_CAPF_MAX_POINT_WIDTH_AA:
413
/* The maximum dimensions of the colorbuffer are our practical
414
* rendering limits. 2048 pixels should be enough for anybody. */
415
if (r300screen->caps.is_r500) {
416
return 4096.0f;
417
} else if (r300screen->caps.is_r400) {
418
return 4021.0f;
419
} else {
420
return 2560.0f;
421
}
422
case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
423
return 16.0f;
424
case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
425
return 16.0f;
426
case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
427
case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
428
case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
429
return 0.0f;
430
default:
431
debug_printf("r300: Warning: Unknown CAP %d in get_paramf.\n",
432
param);
433
return 0.0f;
434
}
435
}
436
437
static int r300_get_video_param(struct pipe_screen *screen,
438
enum pipe_video_profile profile,
439
enum pipe_video_entrypoint entrypoint,
440
enum pipe_video_cap param)
441
{
442
switch (param) {
443
case PIPE_VIDEO_CAP_SUPPORTED:
444
return vl_profile_supported(screen, profile, entrypoint);
445
case PIPE_VIDEO_CAP_NPOT_TEXTURES:
446
return 0;
447
case PIPE_VIDEO_CAP_MAX_WIDTH:
448
case PIPE_VIDEO_CAP_MAX_HEIGHT:
449
return vl_video_buffer_max_size(screen);
450
case PIPE_VIDEO_CAP_PREFERED_FORMAT:
451
return PIPE_FORMAT_NV12;
452
case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
453
return false;
454
case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
455
return false;
456
case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
457
return true;
458
case PIPE_VIDEO_CAP_MAX_LEVEL:
459
return vl_level_supported(screen, profile);
460
default:
461
return 0;
462
}
463
}
464
465
/**
466
* Whether the format matches:
467
* PIPE_FORMAT_?10?10?10?2_UNORM
468
*/
469
static inline boolean
470
util_format_is_rgba1010102_variant(const struct util_format_description *desc)
471
{
472
static const unsigned size[4] = {10, 10, 10, 2};
473
unsigned chan;
474
475
if (desc->block.width != 1 ||
476
desc->block.height != 1 ||
477
desc->block.bits != 32)
478
return FALSE;
479
480
for (chan = 0; chan < 4; ++chan) {
481
if(desc->channel[chan].type != UTIL_FORMAT_TYPE_UNSIGNED &&
482
desc->channel[chan].type != UTIL_FORMAT_TYPE_VOID)
483
return FALSE;
484
if (desc->channel[chan].size != size[chan])
485
return FALSE;
486
}
487
488
return TRUE;
489
}
490
491
static bool r300_is_blending_supported(struct r300_screen *rscreen,
492
enum pipe_format format)
493
{
494
int c;
495
const struct util_format_description *desc =
496
util_format_description(format);
497
498
if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
499
return false;
500
501
c = util_format_get_first_non_void_channel(format);
502
503
/* RGBA16F */
504
if (rscreen->caps.is_r500 &&
505
desc->nr_channels == 4 &&
506
desc->channel[c].size == 16 &&
507
desc->channel[c].type == UTIL_FORMAT_TYPE_FLOAT)
508
return true;
509
510
if (desc->channel[c].normalized &&
511
desc->channel[c].type == UTIL_FORMAT_TYPE_UNSIGNED &&
512
desc->channel[c].size >= 4 &&
513
desc->channel[c].size <= 10) {
514
/* RGB10_A2, RGBA8, RGB5_A1, RGBA4, RGB565 */
515
if (desc->nr_channels >= 3)
516
return true;
517
518
if (format == PIPE_FORMAT_R8G8_UNORM)
519
return true;
520
521
/* R8, I8, L8, A8 */
522
if (desc->nr_channels == 1)
523
return true;
524
}
525
526
return false;
527
}
528
529
static bool r300_is_format_supported(struct pipe_screen* screen,
530
enum pipe_format format,
531
enum pipe_texture_target target,
532
unsigned sample_count,
533
unsigned storage_sample_count,
534
unsigned usage)
535
{
536
uint32_t retval = 0;
537
boolean is_r500 = r300_screen(screen)->caps.is_r500;
538
boolean is_r400 = r300_screen(screen)->caps.is_r400;
539
boolean is_color2101010 = format == PIPE_FORMAT_R10G10B10A2_UNORM ||
540
format == PIPE_FORMAT_R10G10B10X2_SNORM ||
541
format == PIPE_FORMAT_B10G10R10A2_UNORM ||
542
format == PIPE_FORMAT_B10G10R10X2_UNORM ||
543
format == PIPE_FORMAT_R10SG10SB10SA2U_NORM;
544
boolean is_ati1n = format == PIPE_FORMAT_RGTC1_UNORM ||
545
format == PIPE_FORMAT_RGTC1_SNORM ||
546
format == PIPE_FORMAT_LATC1_UNORM ||
547
format == PIPE_FORMAT_LATC1_SNORM;
548
boolean is_ati2n = format == PIPE_FORMAT_RGTC2_UNORM ||
549
format == PIPE_FORMAT_RGTC2_SNORM ||
550
format == PIPE_FORMAT_LATC2_UNORM ||
551
format == PIPE_FORMAT_LATC2_SNORM;
552
boolean is_half_float = format == PIPE_FORMAT_R16_FLOAT ||
553
format == PIPE_FORMAT_R16G16_FLOAT ||
554
format == PIPE_FORMAT_R16G16B16_FLOAT ||
555
format == PIPE_FORMAT_R16G16B16A16_FLOAT ||
556
format == PIPE_FORMAT_R16G16B16X16_FLOAT;
557
const struct util_format_description *desc;
558
559
if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
560
return false;
561
562
/* Check multisampling support. */
563
switch (sample_count) {
564
case 0:
565
case 1:
566
break;
567
case 2:
568
case 4:
569
case 6:
570
/* No texturing and scanout. */
571
if (usage & (PIPE_BIND_SAMPLER_VIEW |
572
PIPE_BIND_DISPLAY_TARGET |
573
PIPE_BIND_SCANOUT)) {
574
return false;
575
}
576
577
desc = util_format_description(format);
578
579
if (is_r500) {
580
/* Only allow depth/stencil, RGBA8, RGBA1010102, RGBA16F. */
581
if (!util_format_is_depth_or_stencil(format) &&
582
!util_format_is_rgba8_variant(desc) &&
583
!util_format_is_rgba1010102_variant(desc) &&
584
format != PIPE_FORMAT_R16G16B16A16_FLOAT &&
585
format != PIPE_FORMAT_R16G16B16X16_FLOAT) {
586
return false;
587
}
588
} else {
589
/* Only allow depth/stencil, RGBA8. */
590
if (!util_format_is_depth_or_stencil(format) &&
591
!util_format_is_rgba8_variant(desc)) {
592
return false;
593
}
594
}
595
break;
596
default:
597
return false;
598
}
599
600
/* Check sampler format support. */
601
if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
602
/* these two are broken for an unknown reason */
603
format != PIPE_FORMAT_R8G8B8X8_SNORM &&
604
format != PIPE_FORMAT_R16G16B16X16_SNORM &&
605
/* ATI1N is r5xx-only. */
606
(is_r500 || !is_ati1n) &&
607
/* ATI2N is supported on r4xx-r5xx. */
608
(is_r400 || is_r500 || !is_ati2n) &&
609
r300_is_sampler_format_supported(format)) {
610
retval |= PIPE_BIND_SAMPLER_VIEW;
611
}
612
613
/* Check colorbuffer format support. */
614
if ((usage & (PIPE_BIND_RENDER_TARGET |
615
PIPE_BIND_DISPLAY_TARGET |
616
PIPE_BIND_SCANOUT |
617
PIPE_BIND_SHARED |
618
PIPE_BIND_BLENDABLE)) &&
619
/* 2101010 cannot be rendered to on non-r5xx. */
620
(!is_color2101010 || is_r500) &&
621
r300_is_colorbuffer_format_supported(format)) {
622
retval |= usage &
623
(PIPE_BIND_RENDER_TARGET |
624
PIPE_BIND_DISPLAY_TARGET |
625
PIPE_BIND_SCANOUT |
626
PIPE_BIND_SHARED);
627
628
if (r300_is_blending_supported(r300_screen(screen), format)) {
629
retval |= usage & PIPE_BIND_BLENDABLE;
630
}
631
}
632
633
/* Check depth-stencil format support. */
634
if (usage & PIPE_BIND_DEPTH_STENCIL &&
635
r300_is_zs_format_supported(format)) {
636
retval |= PIPE_BIND_DEPTH_STENCIL;
637
}
638
639
/* Check vertex buffer format support. */
640
if (usage & PIPE_BIND_VERTEX_BUFFER) {
641
if (r300_screen(screen)->caps.has_tcl) {
642
/* Half float is supported on >= R400. */
643
if ((is_r400 || is_r500 || !is_half_float) &&
644
r300_translate_vertex_data_type(format) != R300_INVALID_FORMAT) {
645
retval |= PIPE_BIND_VERTEX_BUFFER;
646
}
647
} else {
648
/* SW TCL */
649
if (!util_format_is_pure_integer(format)) {
650
retval |= PIPE_BIND_VERTEX_BUFFER;
651
}
652
}
653
}
654
655
if (usage & PIPE_BIND_INDEX_BUFFER) {
656
if (format == PIPE_FORMAT_R8_UINT ||
657
format == PIPE_FORMAT_R16_UINT ||
658
format == PIPE_FORMAT_R32_UINT)
659
retval |= PIPE_BIND_INDEX_BUFFER;
660
}
661
662
return retval == usage;
663
}
664
665
static void r300_destroy_screen(struct pipe_screen* pscreen)
666
{
667
struct r300_screen* r300screen = r300_screen(pscreen);
668
struct radeon_winsys *rws = radeon_winsys(pscreen);
669
670
if (rws && !rws->unref(rws))
671
return;
672
673
mtx_destroy(&r300screen->cmask_mutex);
674
slab_destroy_parent(&r300screen->pool_transfers);
675
676
disk_cache_destroy(r300screen->disk_shader_cache);
677
678
if (rws)
679
rws->destroy(rws);
680
681
FREE(r300screen);
682
}
683
684
static void r300_fence_reference(struct pipe_screen *screen,
685
struct pipe_fence_handle **ptr,
686
struct pipe_fence_handle *fence)
687
{
688
struct radeon_winsys *rws = r300_screen(screen)->rws;
689
690
rws->fence_reference(ptr, fence);
691
}
692
693
static bool r300_fence_finish(struct pipe_screen *screen,
694
struct pipe_context *ctx,
695
struct pipe_fence_handle *fence,
696
uint64_t timeout)
697
{
698
struct radeon_winsys *rws = r300_screen(screen)->rws;
699
700
return rws->fence_wait(rws, fence, timeout);
701
}
702
703
struct pipe_screen* r300_screen_create(struct radeon_winsys *rws,
704
const struct pipe_screen_config *config)
705
{
706
struct r300_screen *r300screen = CALLOC_STRUCT(r300_screen);
707
708
if (!r300screen) {
709
FREE(r300screen);
710
return NULL;
711
}
712
713
rws->query_info(rws, &r300screen->info, false, false);
714
715
r300_init_debug(r300screen);
716
r300_parse_chipset(r300screen->info.pci_id, &r300screen->caps);
717
718
if (SCREEN_DBG_ON(r300screen, DBG_NO_ZMASK))
719
r300screen->caps.zmask_ram = 0;
720
if (SCREEN_DBG_ON(r300screen, DBG_NO_HIZ))
721
r300screen->caps.hiz_ram = 0;
722
723
r300screen->rws = rws;
724
r300screen->screen.destroy = r300_destroy_screen;
725
r300screen->screen.get_name = r300_get_name;
726
r300screen->screen.get_vendor = r300_get_vendor;
727
r300screen->screen.get_device_vendor = r300_get_device_vendor;
728
r300screen->screen.get_disk_shader_cache = r300_get_disk_shader_cache;
729
r300screen->screen.get_param = r300_get_param;
730
r300screen->screen.get_shader_param = r300_get_shader_param;
731
r300screen->screen.get_paramf = r300_get_paramf;
732
r300screen->screen.get_video_param = r300_get_video_param;
733
r300screen->screen.is_format_supported = r300_is_format_supported;
734
r300screen->screen.is_video_format_supported = vl_video_buffer_is_format_supported;
735
r300screen->screen.context_create = r300_create_context;
736
r300screen->screen.fence_reference = r300_fence_reference;
737
r300screen->screen.fence_finish = r300_fence_finish;
738
739
r300_init_screen_resource_functions(r300screen);
740
741
r300_disk_cache_create(r300screen);
742
743
slab_create_parent(&r300screen->pool_transfers, sizeof(struct pipe_transfer), 64);
744
745
(void) mtx_init(&r300screen->cmask_mutex, mtx_plain);
746
747
return &r300screen->screen;
748
}
749
750