Path: blob/21.2-virgl/src/gallium/drivers/r600/r600_asm.h
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/*1* Copyright 2010 Jerome Glisse <[email protected]>2*3* Permission is hereby granted, free of charge, to any person obtaining a4* copy of this software and associated documentation files (the "Software"),5* to deal in the Software without restriction, including without limitation6* on the rights to use, copy, modify, merge, publish, distribute, sub7* license, and/or sell copies of the Software, and to permit persons to whom8* the Software is furnished to do so, subject to the following conditions:9*10* The above copyright notice and this permission notice (including the next11* paragraph) shall be included in all copies or substantial portions of the12* Software.13*14* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL17* THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,18* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR19* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE20* USE OR OTHER DEALINGS IN THE SOFTWARE.21*/22#ifndef R600_ASM_H23#define R600_ASM_H2425#include "r600_pipe.h"26#include "r600_isa.h"27#include "tgsi/tgsi_exec.h"2829#ifdef __cplusplus30extern "C" {31#endif3233struct r600_bytecode_alu_src {34unsigned sel;35unsigned chan;36unsigned neg;37unsigned abs;38unsigned rel;39unsigned kc_bank;40unsigned kc_rel;41uint32_t value;42};4344struct r600_bytecode_alu_dst {45unsigned sel;46unsigned chan;47unsigned clamp;48unsigned write;49unsigned rel;50};5152struct r600_bytecode_alu {53struct list_head list;54struct r600_bytecode_alu_src src[3];55struct r600_bytecode_alu_dst dst;56unsigned op;57unsigned last;58unsigned is_op3;59unsigned is_lds_idx_op;60unsigned execute_mask;61unsigned update_pred;62unsigned pred_sel;63unsigned bank_swizzle;64unsigned bank_swizzle_force;65unsigned omod;66unsigned index_mode;67unsigned lds_idx;68};6970struct r600_bytecode_tex {71struct list_head list;72unsigned op;73unsigned inst_mod;74unsigned resource_id;75unsigned src_gpr;76unsigned src_rel;77unsigned dst_gpr;78unsigned dst_rel;79unsigned dst_sel_x;80unsigned dst_sel_y;81unsigned dst_sel_z;82unsigned dst_sel_w;83unsigned lod_bias;84unsigned coord_type_x;85unsigned coord_type_y;86unsigned coord_type_z;87unsigned coord_type_w;88int offset_x;89int offset_y;90int offset_z;91unsigned sampler_id;92unsigned src_sel_x;93unsigned src_sel_y;94unsigned src_sel_z;95unsigned src_sel_w;96/* indexed samplers/resources only on evergreen/cayman */97unsigned sampler_index_mode;98unsigned resource_index_mode;99};100101struct r600_bytecode_vtx {102struct list_head list;103unsigned op;104unsigned fetch_type;105unsigned buffer_id;106unsigned src_gpr;107unsigned src_sel_x;108unsigned mega_fetch_count;109unsigned dst_gpr;110unsigned dst_sel_x;111unsigned dst_sel_y;112unsigned dst_sel_z;113unsigned dst_sel_w;114unsigned use_const_fields;115unsigned data_format;116unsigned num_format_all;117unsigned format_comp_all;118unsigned srf_mode_all;119unsigned offset;120unsigned endian;121unsigned buffer_index_mode;122123// READ_SCRATCH fields124unsigned uncached;125unsigned indexed;126unsigned src_sel_y;127unsigned src_rel;128unsigned elem_size;129unsigned array_size;130unsigned array_base;131unsigned burst_count;132unsigned dst_rel;133};134135struct r600_bytecode_gds {136struct list_head list;137unsigned op;138unsigned src_gpr;139unsigned src_rel;140unsigned src_sel_x;141unsigned src_sel_y;142unsigned src_sel_z;143unsigned src_gpr2;144unsigned dst_gpr;145unsigned dst_rel;146unsigned dst_sel_x;147unsigned dst_sel_y;148unsigned dst_sel_z;149unsigned dst_sel_w;150unsigned uav_index_mode;151unsigned uav_id;152unsigned alloc_consume;153unsigned bcast_first_req;154};155156struct r600_bytecode_output {157unsigned array_base;158unsigned array_size;159unsigned comp_mask;160unsigned type;161162unsigned op;163164unsigned elem_size;165unsigned gpr;166unsigned swizzle_x;167unsigned swizzle_y;168unsigned swizzle_z;169unsigned swizzle_w;170unsigned burst_count;171unsigned index_gpr;172unsigned mark; /* used by MEM_SCRATCH */173};174175struct r600_bytecode_rat {176unsigned id;177unsigned inst;178unsigned index_mode;179};180181struct r600_bytecode_kcache {182unsigned bank;183unsigned mode;184unsigned addr;185unsigned index_mode;186};187188struct r600_bytecode_cf {189struct list_head list;190191unsigned op;192unsigned addr;193unsigned ndw;194unsigned id;195unsigned cond;196unsigned pop_count;197unsigned count;198unsigned cf_addr; /* control flow addr */199struct r600_bytecode_kcache kcache[4];200unsigned r6xx_uses_waterfall;201unsigned eg_alu_extended;202unsigned barrier;203unsigned end_of_program;204unsigned mark;205unsigned vpm;206struct list_head alu;207struct list_head tex;208struct list_head vtx;209struct list_head gds;210struct r600_bytecode_output output;211struct r600_bytecode_rat rat;212struct r600_bytecode_alu *curr_bs_head;213struct r600_bytecode_alu *prev_bs_head;214struct r600_bytecode_alu *prev2_bs_head;215unsigned isa[2];216unsigned nlds_read;217unsigned nqueue_read;218};219220#define FC_NONE 0221#define FC_IF 1222#define FC_LOOP 2223#define FC_REP 3224#define FC_PUSH_VPM 4225#define FC_PUSH_WQM 5226227struct r600_cf_stack_entry {228int type;229struct r600_bytecode_cf *start;230struct r600_bytecode_cf **mid; /* used to store the else point */231int num_mid;232};233234#define SQ_MAX_CALL_DEPTH 0x00000020235236#define AR_HANDLE_NORMAL 0237#define AR_HANDLE_RV6XX 1 /* except RV670 */238239struct r600_stack_info {240/* current level of non-WQM PUSH operations241* (PUSH, PUSH_ELSE, ALU_PUSH_BEFORE) */242int push;243/* current level of WQM PUSH operations244* (PUSH, PUSH_ELSE, PUSH_WQM) */245int push_wqm;246/* current loop level */247int loop;248249/* required depth */250int max_entries;251/* subentries per entry */252int entry_size;253};254255struct r600_bytecode {256enum chip_class chip_class;257enum radeon_family family;258bool has_compressed_msaa_texturing;259int type;260struct list_head cf;261struct r600_bytecode_cf *cf_last;262unsigned ndw;263unsigned ncf;264unsigned ngpr;265unsigned nstack;266unsigned nlds_dw;267unsigned nresource;268unsigned force_add_cf;269uint32_t *bytecode;270uint32_t fc_sp;271struct r600_cf_stack_entry fc_stack[TGSI_EXEC_MAX_NESTING];272struct r600_stack_info stack;273unsigned ar_loaded;274unsigned ar_reg;275unsigned ar_chan;276unsigned ar_handling;277unsigned r6xx_nop_after_rel_dst;278bool index_loaded[2];279unsigned index_reg[2]; /* indexing register CF_INDEX_[01] */280unsigned index_reg_chan[2]; /* indexing register chanel CF_INDEX_[01] */281unsigned debug_id;282struct r600_isa* isa;283struct r600_bytecode_output pending_outputs[5];284int n_pending_outputs;285boolean need_wait_ack; /* emit a pending WAIT_ACK prior to control flow */286boolean precise;287};288289/* eg_asm.c */290int eg_bytecode_cf_build(struct r600_bytecode *bc, struct r600_bytecode_cf *cf);291int egcm_load_index_reg(struct r600_bytecode *bc, unsigned id, bool inside_alu_clause);292int eg_bytecode_gds_build(struct r600_bytecode *bc, struct r600_bytecode_gds *gds, unsigned id);293int eg_bytecode_alu_build(struct r600_bytecode *bc,294struct r600_bytecode_alu *alu, unsigned id);295/* r600_asm.c */296void r600_bytecode_init(struct r600_bytecode *bc,297enum chip_class chip_class,298enum radeon_family family,299bool has_compressed_msaa_texturing);300void r600_bytecode_clear(struct r600_bytecode *bc);301int r600_bytecode_add_alu(struct r600_bytecode *bc,302const struct r600_bytecode_alu *alu);303int r600_bytecode_add_vtx(struct r600_bytecode *bc,304const struct r600_bytecode_vtx *vtx);305int r600_bytecode_add_vtx_tc(struct r600_bytecode *bc,306const struct r600_bytecode_vtx *vtx);307int r600_bytecode_add_tex(struct r600_bytecode *bc,308const struct r600_bytecode_tex *tex);309int r600_bytecode_add_gds(struct r600_bytecode *bc,310const struct r600_bytecode_gds *gds);311int r600_bytecode_add_output(struct r600_bytecode *bc,312const struct r600_bytecode_output *output);313int r600_bytecode_add_pending_output(struct r600_bytecode *bc,314const struct r600_bytecode_output *output);315void r600_bytecode_need_wait_ack(struct r600_bytecode *bc, boolean needed);316boolean r600_bytecode_get_need_wait_ack(struct r600_bytecode *bc);317int r600_bytecode_build(struct r600_bytecode *bc);318int r600_bytecode_add_cf(struct r600_bytecode *bc);319int r600_bytecode_add_cfinst(struct r600_bytecode *bc,320unsigned op);321int r600_bytecode_add_alu_type(struct r600_bytecode *bc,322const struct r600_bytecode_alu *alu, unsigned type);323void r600_bytecode_special_constants(uint32_t value, unsigned *sel);324void r600_bytecode_disasm(struct r600_bytecode *bc);325void r600_bytecode_alu_read(struct r600_bytecode *bc,326struct r600_bytecode_alu *alu, uint32_t word0, uint32_t word1);327328int cm_bytecode_add_cf_end(struct r600_bytecode *bc);329330void *r600_create_vertex_fetch_shader(struct pipe_context *ctx,331unsigned count,332const struct pipe_vertex_element *elements);333334/* r700_asm.c */335void r700_bytecode_cf_vtx_build(uint32_t *bytecode,336const struct r600_bytecode_cf *cf);337int r700_bytecode_alu_build(struct r600_bytecode *bc,338struct r600_bytecode_alu *alu, unsigned id);339void r700_bytecode_alu_read(struct r600_bytecode *bc,340struct r600_bytecode_alu *alu, uint32_t word0, uint32_t word1);341int r700_bytecode_fetch_mem_build(struct r600_bytecode *bc,342struct r600_bytecode_vtx *mem, unsigned id);343344void r600_bytecode_export_read(struct r600_bytecode *bc,345struct r600_bytecode_output *output, uint32_t word0, uint32_t word1);346void eg_bytecode_export_read(struct r600_bytecode *bc,347struct r600_bytecode_output *output, uint32_t word0, uint32_t word1);348349void r600_vertex_data_type(enum pipe_format pformat, unsigned *format,350unsigned *num_format, unsigned *format_comp, unsigned *endian);351352static inline int fp64_switch(int i)353{354switch (i) {355case 0:356return 1;357case 1:358return 0;359case 2:360return 3;361case 3:362return 2;363}364return 0;365}366367#ifdef __cplusplus368}369#endif370371#endif372373374