Path: blob/21.2-virgl/src/gallium/drivers/r600/r600_isa.h
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/*1* Copyright 2012 Vadim Girlin <[email protected]>2*3* Permission is hereby granted, free of charge, to any person obtaining a4* copy of this software and associated documentation files (the "Software"),5* to deal in the Software without restriction, including without limitation6* on the rights to use, copy, modify, merge, publish, distribute, sub7* license, and/or sell copies of the Software, and to permit persons to whom8* the Software is furnished to do so, subject to the following conditions:9*10* The above copyright notice and this permission notice (including the next11* paragraph) shall be included in all copies or substantial portions of the12* Software.13*14* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL17* THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,18* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR19* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE20* USE OR OTHER DEALINGS IN THE SOFTWARE.21*22* Authors:23* Vadim Girlin24*/2526#ifndef R600_ISA_H_27#define R600_ISA_H_2829#include "util/u_debug.h"3031#ifdef __cplusplus32extern "C" {33#endif3435/* ALU flags */36enum alu_op_flags37{38AF_NONE = 0,39AF_V = (1<<0), /* allowed in vector slots */4041/* allowed in scalar(trans) slot (slots xyz on cayman, may be replicated42* to w) */43AF_S = (1<<1),4445AF_4SLOT = (1<<2), /* uses four vector slots (e.g. DOT4) */46AF_4V = (AF_V | AF_4SLOT),47AF_VS = (AF_V | AF_S), /* allowed in any slot */4849AF_2SLOT = (1 << 3),50AF_2V = AF_V | AF_2SLOT, /* XY or ZW */5152AF_KILL = (1<<4),53AF_PRED = (1<<5),54AF_SET = (1<<6),5556/* e.g. MUL_PREV instructions, allowed in x/y, depends on z/w */57AF_PREV_INTERLEAVE = (1<<7),5859AF_MOVA = (1<<8), /* all MOVA instructions */6061AF_IEEE = (1<<10),6263AF_DST_TYPE_MASK = (3<<11),64AF_FLOAT_DST = 0,65AF_INT_DST = (1<<11),66AF_UINT_DST = (3<<11),6768/* DP instructions, 2-slot pairs */69AF_64 = (1<<13),70/* 24 bit instructions */71AF_24 = (1<<14),72/* DX10 variants */73AF_DX10 = (1<<15),7475/* result is replicated to all channels (only if AF_4V is also set -76* for special handling of MULLO_INT on CM) */77AF_REPL = (1<<16),7879/* interpolation instructions */80AF_INTERP = (1<<17),8182/* LDS instructions */83AF_LDS = (1<<20),8485/* e.g. DOT - depends on the next slot in the same group (x<=y/y<=z/z<=w) */86AF_PREV_NEXT = (1<<21),8788/* int<->flt conversions */89AF_CVT = (1<<22),9091/* commutative operation on src0 and src1 ( a op b = b op a),92* includes MULADDs (considering the MUL part on src0 and src1 only) */93AF_M_COMM = (1 << 23),9495/* associative operation ((a op b) op c) == (a op (b op c)),96* includes MULADDs (considering the MUL part on src0 and src1 only) */97AF_M_ASSOC = (1 << 24),9899AF_PRED_PUSH = (1 << 25),100101AF_ANY_PRED = (AF_PRED | AF_PRED_PUSH),102103AF_CMOV = (1 << 26),104105// for SETcc, PREDSETcc, ... - type of comparison106AF_CMP_TYPE_MASK = (3 << 27),107AF_FLOAT_CMP = 0,108AF_INT_CMP = (1 << 27),109AF_UINT_CMP = (3 << 27),110111/* condition codes - 3 bits */112AF_CC_SHIFT = 29,113114AF_CC_MASK = (7U << AF_CC_SHIFT),115AF_CC_E = (0U << AF_CC_SHIFT),116AF_CC_GT = (1U << AF_CC_SHIFT),117AF_CC_GE = (2U << AF_CC_SHIFT),118AF_CC_NE = (3U << AF_CC_SHIFT),119AF_CC_LT = (4U << AF_CC_SHIFT),120AF_CC_LE = (5U << AF_CC_SHIFT),121};122123/* flags for FETCH instructions (TEX/VTX/GDS) */124enum fetch_op_flags125{126FF_GDS = (1<<0),127FF_TEX = (1<<1),128129FF_SETGRAD = (1<<2),130FF_GETGRAD = (1<<3),131FF_USEGRAD = (1<<4),132133FF_VTX = (1<<5),134FF_MEM = (1<<6),135136FF_SET_TEXTURE_OFFSETS = (1<<7),137FF_USE_TEXTURE_OFFSETS = (1<<8),138};139140/* flags for CF instructions */141enum cf_op_flags142{143CF_CLAUSE = (1<<0), /* execute clause (alu/fetch ...) */144CF_ACK = (1<<1), /* acked versions of some instructions */145CF_ALU = (1<<2), /* alu clause execution */146CF_ALU_EXT = (1<<3), /* ALU_EXTENDED */147CF_EXP = (1<<4), /* export (CF_ALLOC_EXPORT_WORD1_SWIZ) */148CF_BRANCH = (1<<5), /* branch instructions */149CF_LOOP = (1<<6), /* loop instructions */150CF_CALL = (1<<7), /* call instructions */151CF_MEM = (1<<8), /* export_mem (CF_ALLOC_EXPORT_WORD1_BUF) */152CF_FETCH = (1<<9), /* fetch clause */153154CF_UNCOND = (1<<10), /* COND = ACTIVE required */155CF_EMIT = (1<<11),156CF_STRM = (1<<12), /* MEM_STREAM* */157158CF_RAT = (1<<13), /* MEM_RAT* */159160CF_LOOP_START = (1<<14)161};162163/* ALU instruction info */164struct alu_op_info165{166/* instruction name */167const char *name;168/* number of source operands */169int src_count;170/* opcodes, [0] - for r6xx/r7xx, [1] - for evergreen/cayman171* (-1) if instruction doesn't exist (more precise info in "slots") */172int opcode[2];173/* slots for r6xx, r7xx, evergreen, cayman174* (0 if instruction doesn't exist for chip class) */175int slots[4];176/* flags (mostly autogenerated from instruction name) */177unsigned int flags;178};179180/* FETCH instruction info */181struct fetch_op_info182{183const char * name;184/* for every chip class */185int opcode[4];186int flags;187};188189/* CF instruction info */190struct cf_op_info191{192const char * name;193/* for every chip class */194int opcode[4];195int flags;196};197198199#define ALU_OP2_ADD 0200#define ALU_OP2_MUL 1201#define ALU_OP2_MUL_IEEE 2202#define ALU_OP2_MAX 3203#define ALU_OP2_MIN 4204#define ALU_OP2_MAX_DX10 5205#define ALU_OP2_MIN_DX10 6206#define ALU_OP2_SETE 7207#define ALU_OP2_SETGT 8208#define ALU_OP2_SETGE 9209#define ALU_OP2_SETNE 10210#define ALU_OP2_SETE_DX10 11211#define ALU_OP2_SETGT_DX10 12212#define ALU_OP2_SETGE_DX10 13213#define ALU_OP2_SETNE_DX10 14214#define ALU_OP1_FRACT 15215#define ALU_OP1_TRUNC 16216#define ALU_OP1_CEIL 17217#define ALU_OP1_RNDNE 18218#define ALU_OP1_FLOOR 19219#define ALU_OP2_ASHR_INT 20220#define ALU_OP2_LSHR_INT 21221#define ALU_OP2_LSHL_INT 22222#define ALU_OP1_MOV 23223#define ALU_OP0_NOP 24224#define ALU_OP2_PRED_SETGT_UINT 25225#define ALU_OP2_PRED_SETGE_UINT 26226#define ALU_OP2_PRED_SETE 27227#define ALU_OP2_PRED_SETGT 28228#define ALU_OP2_PRED_SETGE 29229#define ALU_OP2_PRED_SETNE 30230#define ALU_OP1_PRED_SET_INV 31231#define ALU_OP2_PRED_SET_POP 32232#define ALU_OP0_PRED_SET_CLR 33233#define ALU_OP1_PRED_SET_RESTORE 34234#define ALU_OP2_PRED_SETE_PUSH 35235#define ALU_OP2_PRED_SETGT_PUSH 36236#define ALU_OP2_PRED_SETGE_PUSH 37237#define ALU_OP2_PRED_SETNE_PUSH 38238#define ALU_OP2_KILLE 39239#define ALU_OP2_KILLGT 40240#define ALU_OP2_KILLGE 41241#define ALU_OP2_KILLNE 42242#define ALU_OP2_AND_INT 43243#define ALU_OP2_OR_INT 44244#define ALU_OP2_XOR_INT 45245#define ALU_OP1_NOT_INT 46246#define ALU_OP2_ADD_INT 47247#define ALU_OP2_SUB_INT 48248#define ALU_OP2_MAX_INT 49249#define ALU_OP2_MIN_INT 50250#define ALU_OP2_MAX_UINT 51251#define ALU_OP2_MIN_UINT 52252#define ALU_OP2_SETE_INT 53253#define ALU_OP2_SETGT_INT 54254#define ALU_OP2_SETGE_INT 55255#define ALU_OP2_SETNE_INT 56256#define ALU_OP2_SETGT_UINT 57257#define ALU_OP2_SETGE_UINT 58258#define ALU_OP2_KILLGT_UINT 59259#define ALU_OP2_KILLGE_UINT 60260#define ALU_OP2_PRED_SETE_INT 61261#define ALU_OP2_PRED_SETGT_INT 62262#define ALU_OP2_PRED_SETGE_INT 63263#define ALU_OP2_PRED_SETNE_INT 64264#define ALU_OP2_KILLE_INT 65265#define ALU_OP2_KILLGT_INT 66266#define ALU_OP2_KILLGE_INT 67267#define ALU_OP2_KILLNE_INT 68268#define ALU_OP2_PRED_SETE_PUSH_INT 69269#define ALU_OP2_PRED_SETGT_PUSH_INT 70270#define ALU_OP2_PRED_SETGE_PUSH_INT 71271#define ALU_OP2_PRED_SETNE_PUSH_INT 72272#define ALU_OP2_PRED_SETLT_PUSH_INT 73273#define ALU_OP2_PRED_SETLE_PUSH_INT 74274#define ALU_OP1_FLT_TO_INT 75275#define ALU_OP1_BFREV_INT 76276#define ALU_OP2_ADDC_UINT 77277#define ALU_OP2_SUBB_UINT 78278#define ALU_OP0_GROUP_BARRIER 79279#define ALU_OP0_GROUP_SEQ_BEGIN 80280#define ALU_OP0_GROUP_SEQ_END 81281#define ALU_OP2_SET_MODE 82282#define ALU_OP0_SET_CF_IDX0 83283#define ALU_OP0_SET_CF_IDX1 84284#define ALU_OP2_SET_LDS_SIZE 85285#define ALU_OP2_MUL_INT24 86286#define ALU_OP2_MULHI_INT24 87287#define ALU_OP1_FLT_TO_INT_TRUNC 88288#define ALU_OP1_EXP_IEEE 89289#define ALU_OP1_LOG_CLAMPED 90290#define ALU_OP1_LOG_IEEE 91291#define ALU_OP1_RECIP_CLAMPED 92292#define ALU_OP1_RECIP_FF 93293#define ALU_OP1_RECIP_IEEE 94294#define ALU_OP1_RECIPSQRT_CLAMPED 95295#define ALU_OP1_RECIPSQRT_FF 96296#define ALU_OP1_RECIPSQRT_IEEE 97297#define ALU_OP1_SQRT_IEEE 98298#define ALU_OP1_SIN 99299#define ALU_OP1_COS 100300#define ALU_OP2_MULLO_INT 101301#define ALU_OP2_MULHI_INT 102302#define ALU_OP2_MULLO_UINT 103303#define ALU_OP2_MULHI_UINT 104304#define ALU_OP1_RECIP_INT 105305#define ALU_OP1_RECIP_UINT 106306#define ALU_OP2_RECIP_64 107307#define ALU_OP2_RECIP_CLAMPED_64 108308#define ALU_OP2_RECIPSQRT_64 109309#define ALU_OP2_RECIPSQRT_CLAMPED_64 110310#define ALU_OP2_SQRT_64 111311#define ALU_OP1_FLT_TO_UINT 112312#define ALU_OP1_INT_TO_FLT 113313#define ALU_OP1_UINT_TO_FLT 114314#define ALU_OP2_BFM_INT 115315#define ALU_OP1_FLT32_TO_FLT16 116316#define ALU_OP1_FLT16_TO_FLT32 117317#define ALU_OP1_UBYTE0_FLT 118318#define ALU_OP1_UBYTE1_FLT 119319#define ALU_OP1_UBYTE2_FLT 120320#define ALU_OP1_UBYTE3_FLT 121321#define ALU_OP1_BCNT_INT 122322#define ALU_OP1_FFBH_UINT 123323#define ALU_OP1_FFBL_INT 124324#define ALU_OP1_FFBH_INT 125325#define ALU_OP1_FLT_TO_UINT4 126326#define ALU_OP2_DOT_IEEE 127327#define ALU_OP1_FLT_TO_INT_RPI 128328#define ALU_OP1_FLT_TO_INT_FLOOR 129329#define ALU_OP2_MULHI_UINT24 130330#define ALU_OP1_MBCNT_32HI_INT 131331#define ALU_OP1_OFFSET_TO_FLT 132332#define ALU_OP2_MUL_UINT24 133333#define ALU_OP1_BCNT_ACCUM_PREV_INT 134334#define ALU_OP1_MBCNT_32LO_ACCUM_PREV_INT 135335#define ALU_OP2_SETE_64 136336#define ALU_OP2_SETNE_64 137337#define ALU_OP2_SETGT_64 138338#define ALU_OP2_SETGE_64 139339#define ALU_OP2_MIN_64 140340#define ALU_OP2_MAX_64 141341#define ALU_OP2_DOT4 142342#define ALU_OP2_DOT4_IEEE 143343#define ALU_OP2_CUBE 144344#define ALU_OP1_MAX4 145345#define ALU_OP1_FREXP_64 146346#define ALU_OP2_LDEXP_64 147347#define ALU_OP1_FRACT_64 148348#define ALU_OP2_PRED_SETGT_64 149349#define ALU_OP2_PRED_SETE_64 150350#define ALU_OP2_PRED_SETGE_64 151351#define ALU_OP2_MUL_64 152352#define ALU_OP2_ADD_64 153353#define ALU_OP1_MOVA_INT 154354#define ALU_OP1_FLT64_TO_FLT32 155355#define ALU_OP1_FLT32_TO_FLT64 156356#define ALU_OP2_SAD_ACCUM_PREV_UINT 157357#define ALU_OP2_DOT 158358#define ALU_OP1_MUL_PREV 159359#define ALU_OP1_MUL_IEEE_PREV 160360#define ALU_OP1_ADD_PREV 161361#define ALU_OP2_MULADD_PREV 162362#define ALU_OP2_MULADD_IEEE_PREV 163363#define ALU_OP2_INTERP_XY 164364#define ALU_OP2_INTERP_ZW 165365#define ALU_OP2_INTERP_X 166366#define ALU_OP2_INTERP_Z 167367#define ALU_OP1_STORE_FLAGS 168368#define ALU_OP1_LOAD_STORE_FLAGS 169369#define ALU_OP2_LDS_1A 170370#define ALU_OP2_LDS_1A1D 171371#define ALU_OP2_LDS_2A 172372#define ALU_OP1_INTERP_LOAD_P0 173373#define ALU_OP1_INTERP_LOAD_P10 174374#define ALU_OP1_INTERP_LOAD_P20 175375#define ALU_OP3_BFE_UINT 176376#define ALU_OP3_BFE_INT 177377#define ALU_OP3_BFI_INT 178378#define ALU_OP3_FMA 179379#define ALU_OP3_MULADD_INT24 180380#define ALU_OP3_CNDNE_64 181381#define ALU_OP3_FMA_64 182382#define ALU_OP3_LERP_UINT 183383#define ALU_OP3_BIT_ALIGN_INT 184384#define ALU_OP3_BYTE_ALIGN_INT 185385#define ALU_OP3_SAD_ACCUM_UINT 186386#define ALU_OP3_SAD_ACCUM_HI_UINT 187387#define ALU_OP3_MULADD_UINT24 188388#define ALU_OP3_LDS_IDX_OP 189389#define ALU_OP3_MULADD 190390#define ALU_OP3_MULADD_M2 191391#define ALU_OP3_MULADD_M4 192392#define ALU_OP3_MULADD_D2 193393#define ALU_OP3_MULADD_IEEE 194394#define ALU_OP3_CNDE 195395#define ALU_OP3_CNDGT 196396#define ALU_OP3_CNDGE 197397#define ALU_OP3_CNDE_INT 198398#define ALU_OP3_CNDGT_INT 199399#define ALU_OP3_CNDGE_INT 200400#define ALU_OP3_MUL_LIT 201401#define ALU_OP1_MOVA 202402#define ALU_OP1_MOVA_FLOOR 203403#define ALU_OP1_MOVA_GPR_INT 204404#define ALU_OP3_MULADD_64 205405#define ALU_OP3_MULADD_64_M2 206406#define ALU_OP3_MULADD_64_M4 207407#define ALU_OP3_MULADD_64_D2 208408#define ALU_OP3_MUL_LIT_M2 209409#define ALU_OP3_MUL_LIT_M4 210410#define ALU_OP3_MUL_LIT_D2 211411#define ALU_OP3_MULADD_IEEE_M2 212412#define ALU_OP3_MULADD_IEEE_M4 213413#define ALU_OP3_MULADD_IEEE_D2 214414415#define LDS_OP2_LDS_ADD 215416#define LDS_OP2_LDS_SUB 216417#define LDS_OP2_LDS_RSUB 217418#define LDS_OP2_LDS_INC 218419#define LDS_OP2_LDS_DEC 219420#define LDS_OP2_LDS_MIN_INT 220421#define LDS_OP2_LDS_MAX_INT 221422#define LDS_OP2_LDS_MIN_UINT 222423#define LDS_OP2_LDS_MAX_UINT 223424#define LDS_OP2_LDS_AND 224425#define LDS_OP2_LDS_OR 225426#define LDS_OP2_LDS_XOR 226427#define LDS_OP3_LDS_MSKOR 227428#define LDS_OP2_LDS_WRITE 228429#define LDS_OP3_LDS_WRITE_REL 229430#define LDS_OP3_LDS_WRITE2 230431#define LDS_OP3_LDS_CMP_STORE 231432#define LDS_OP3_LDS_CMP_STORE_SPF 232433#define LDS_OP2_LDS_BYTE_WRITE 233434#define LDS_OP2_LDS_SHORT_WRITE 234435#define LDS_OP2_LDS_ADD_RET 235436#define LDS_OP2_LDS_SUB_RET 236437#define LDS_OP2_LDS_RSUB_RET 237438#define LDS_OP2_LDS_INC_RET 238439#define LDS_OP2_LDS_DEC_RET 239440#define LDS_OP2_LDS_MIN_INT_RET 240441#define LDS_OP2_LDS_MAX_INT_RET 241442#define LDS_OP2_LDS_MIN_UINT_RET 242443#define LDS_OP2_LDS_MAX_UINT_RET 243444#define LDS_OP2_LDS_AND_RET 244445#define LDS_OP2_LDS_OR_RET 245446#define LDS_OP2_LDS_XOR_RET 246447#define LDS_OP3_LDS_MSKOR_RET 247448#define LDS_OP2_LDS_XCHG_RET 248449#define LDS_OP3_LDS_XCHG_REL_RET 249450#define LDS_OP3_LDS_XCHG2_RET 250451#define LDS_OP3_LDS_CMP_XCHG_RET 251452#define LDS_OP3_LDS_CMP_XCHG_SPF_RET 252453#define LDS_OP1_LDS_READ_RET 253454#define LDS_OP1_LDS_READ_REL_RET 254455#define LDS_OP2_LDS_READ2_RET 255456#define LDS_OP3_LDS_READWRITE_RET 256457#define LDS_OP1_LDS_BYTE_READ_RET 257458#define LDS_OP1_LDS_UBYTE_READ_RET 258459#define LDS_OP1_LDS_SHORT_READ_RET 259460#define LDS_OP1_LDS_USHORT_READ_RET 260461462#define FETCH_OP_VFETCH 0463#define FETCH_OP_SEMFETCH 1464#define FETCH_OP_READ_SCRATCH 2465#define FETCH_OP_READ_REDUCT 3466#define FETCH_OP_READ_MEM 4467#define FETCH_OP_DS_LOCAL_WRITE 5468#define FETCH_OP_DS_LOCAL_READ 6469#define FETCH_OP_GDS_ADD 7470#define FETCH_OP_GDS_SUB 8471#define FETCH_OP_GDS_RSUB 9472#define FETCH_OP_GDS_INC 10473#define FETCH_OP_GDS_DEC 11474#define FETCH_OP_GDS_MIN_INT 12475#define FETCH_OP_GDS_MAX_INT 13476#define FETCH_OP_GDS_MIN_UINT 14477#define FETCH_OP_GDS_MAX_UINT 15478#define FETCH_OP_GDS_AND 16479#define FETCH_OP_GDS_OR 17480#define FETCH_OP_GDS_XOR 18481#define FETCH_OP_GDS_MSKOR 19482#define FETCH_OP_GDS_WRITE 20483#define FETCH_OP_GDS_WRITE_REL 21484#define FETCH_OP_GDS_WRITE2 22485#define FETCH_OP_GDS_CMP_STORE 23486#define FETCH_OP_GDS_CMP_STORE_SPF 24487#define FETCH_OP_GDS_BYTE_WRITE 25488#define FETCH_OP_GDS_SHORT_WRITE 26489#define FETCH_OP_GDS_ADD_RET 27490#define FETCH_OP_GDS_SUB_RET 28491#define FETCH_OP_GDS_RSUB_RET 29492#define FETCH_OP_GDS_INC_RET 30493#define FETCH_OP_GDS_DEC_RET 31494#define FETCH_OP_GDS_MIN_INT_RET 32495#define FETCH_OP_GDS_MAX_INT_RET 33496#define FETCH_OP_GDS_MIN_UINT_RET 34497#define FETCH_OP_GDS_MAX_UINT_RET 35498#define FETCH_OP_GDS_AND_RET 36499#define FETCH_OP_GDS_OR_RET 37500#define FETCH_OP_GDS_XOR_RET 38501#define FETCH_OP_GDS_MSKOR_RET 39502#define FETCH_OP_GDS_XCHG_RET 40503#define FETCH_OP_GDS_XCHG_REL_RET 41504#define FETCH_OP_GDS_XCHG2_RET 42505#define FETCH_OP_GDS_CMP_XCHG_RET 43506#define FETCH_OP_GDS_CMP_XCHG_SPF_RET 44507#define FETCH_OP_GDS_READ_RET 45508#define FETCH_OP_GDS_READ_REL_RET 46509#define FETCH_OP_GDS_READ2_RET 47510#define FETCH_OP_GDS_READWRITE_RET 48511#define FETCH_OP_GDS_BYTE_READ_RET 49512#define FETCH_OP_GDS_UBYTE_READ_RET 50513#define FETCH_OP_GDS_SHORT_READ_RET 51514#define FETCH_OP_GDS_USHORT_READ_RET 52515#define FETCH_OP_GDS_ATOMIC_ORDERED_ALLOC 53516#define FETCH_OP_TF_WRITE 54517#define FETCH_OP_DS_GLOBAL_WRITE 55518#define FETCH_OP_DS_GLOBAL_READ 56519#define FETCH_OP_LD 57520#define FETCH_OP_LDFPTR 58521#define FETCH_OP_GET_TEXTURE_RESINFO 59522#define FETCH_OP_GET_NUMBER_OF_SAMPLES 60523#define FETCH_OP_GET_LOD 61524#define FETCH_OP_GET_GRADIENTS_H 62525#define FETCH_OP_GET_GRADIENTS_V 63526#define FETCH_OP_GET_GRADIENTS_H_FINE 64527#define FETCH_OP_GET_GRADIENTS_V_FINE 65528#define FETCH_OP_GET_LERP 66529#define FETCH_OP_SET_TEXTURE_OFFSETS 67530#define FETCH_OP_KEEP_GRADIENTS 68531#define FETCH_OP_SET_GRADIENTS_H 69532#define FETCH_OP_SET_GRADIENTS_V 70533#define FETCH_OP_SET_GRADIENTS_H_COARSE 71534#define FETCH_OP_SET_GRADIENTS_V_COARSE 72535#define FETCH_OP_SET_GRADIENTS_H_PACKED_FINE 73536#define FETCH_OP_SET_GRADIENTS_V_PACKED_FINE 74537#define FETCH_OP_SET_GRADIENTS_H_PACKED_COARSE 75538#define FETCH_OP_SET_GRADIENTS_V_PACKED_COARSE 76539#define FETCH_OP_PASS 77540#define FETCH_OP_PASS1 78541#define FETCH_OP_PASS2 79542#define FETCH_OP_PASS3 80543#define FETCH_OP_SET_CUBEMAP_INDEX 81544#define FETCH_OP_GET_BUFFER_RESINFO 82545#define FETCH_OP_FETCH4 83546#define FETCH_OP_SAMPLE 84547#define FETCH_OP_SAMPLE_L 85548#define FETCH_OP_SAMPLE_LB 86549#define FETCH_OP_SAMPLE_LZ 87550#define FETCH_OP_SAMPLE_G 88551#define FETCH_OP_SAMPLE_G_L 89552#define FETCH_OP_GATHER4 90553#define FETCH_OP_SAMPLE_G_LB 91554#define FETCH_OP_SAMPLE_G_LZ 92555#define FETCH_OP_GATHER4_O 93556#define FETCH_OP_SAMPLE_C 94557#define FETCH_OP_SAMPLE_C_L 95558#define FETCH_OP_SAMPLE_C_LB 96559#define FETCH_OP_SAMPLE_C_LZ 97560#define FETCH_OP_SAMPLE_C_G 98561#define FETCH_OP_SAMPLE_C_G_L 99562#define FETCH_OP_GATHER4_C 100563#define FETCH_OP_SAMPLE_C_G_LB 101564#define FETCH_OP_SAMPLE_C_G_LZ 102565#define FETCH_OP_GATHER4_C_O 103566567#define CF_OP_NOP 0568#define CF_OP_TEX 1569#define CF_OP_VTX 2570#define CF_OP_VTX_TC 3571#define CF_OP_GDS 4572#define CF_OP_LOOP_START 5573#define CF_OP_LOOP_END 6574#define CF_OP_LOOP_START_DX10 7575#define CF_OP_LOOP_START_NO_AL 8576#define CF_OP_LOOP_CONTINUE 9577#define CF_OP_LOOP_BREAK 10578#define CF_OP_JUMP 11579#define CF_OP_PUSH 12580#define CF_OP_PUSH_ELSE 13581#define CF_OP_ELSE 14582#define CF_OP_POP 15583#define CF_OP_POP_JUMP 16584#define CF_OP_POP_PUSH 17585#define CF_OP_POP_PUSH_ELSE 18586#define CF_OP_CALL 19587#define CF_OP_CALL_FS 20588#define CF_OP_RET 21589#define CF_OP_EMIT_VERTEX 22590#define CF_OP_EMIT_CUT_VERTEX 23591#define CF_OP_CUT_VERTEX 24592#define CF_OP_KILL 25593#define CF_OP_END_PROGRAM 26594#define CF_OP_WAIT_ACK 27595#define CF_OP_TEX_ACK 28596#define CF_OP_VTX_ACK 29597#define CF_OP_VTX_TC_ACK 30598#define CF_OP_JUMPTABLE 31599#define CF_OP_WAVE_SYNC 32600#define CF_OP_HALT 33601#define CF_OP_CF_END 34602#define CF_OP_LDS_DEALLOC 35603#define CF_OP_PUSH_WQM 36604#define CF_OP_POP_WQM 37605#define CF_OP_ELSE_WQM 38606#define CF_OP_JUMP_ANY 39607#define CF_OP_REACTIVATE 40608#define CF_OP_REACTIVATE_WQM 41609#define CF_OP_INTERRUPT 42610#define CF_OP_INTERRUPT_AND_SLEEP 43611#define CF_OP_SET_PRIORITY 44612#define CF_OP_MEM_STREAM0_BUF0 45613#define CF_OP_MEM_STREAM0_BUF1 46614#define CF_OP_MEM_STREAM0_BUF2 47615#define CF_OP_MEM_STREAM0_BUF3 48616#define CF_OP_MEM_STREAM1_BUF0 49617#define CF_OP_MEM_STREAM1_BUF1 50618#define CF_OP_MEM_STREAM1_BUF2 51619#define CF_OP_MEM_STREAM1_BUF3 52620#define CF_OP_MEM_STREAM2_BUF0 53621#define CF_OP_MEM_STREAM2_BUF1 54622#define CF_OP_MEM_STREAM2_BUF2 55623#define CF_OP_MEM_STREAM2_BUF3 56624#define CF_OP_MEM_STREAM3_BUF0 57625#define CF_OP_MEM_STREAM3_BUF1 58626#define CF_OP_MEM_STREAM3_BUF2 59627#define CF_OP_MEM_STREAM3_BUF3 60628#define CF_OP_MEM_STREAM0 61629#define CF_OP_MEM_STREAM1 62630#define CF_OP_MEM_STREAM2 63631#define CF_OP_MEM_STREAM3 64632#define CF_OP_MEM_SCRATCH 65633#define CF_OP_MEM_REDUCT 66634#define CF_OP_MEM_RING 67635#define CF_OP_EXPORT 68636#define CF_OP_EXPORT_DONE 69637#define CF_OP_MEM_EXPORT 70638#define CF_OP_MEM_RAT 71639#define CF_OP_MEM_RAT_NOCACHE 72640#define CF_OP_MEM_RING1 73641#define CF_OP_MEM_RING2 74642#define CF_OP_MEM_RING3 75643#define CF_OP_MEM_MEM_COMBINED 76644#define CF_OP_MEM_RAT_COMBINED_NOCACHE 77645#define CF_OP_MEM_RAT_COMBINED 78646#define CF_OP_EXPORT_DONE_END 79647#define CF_OP_ALU 80648#define CF_OP_ALU_PUSH_BEFORE 81649#define CF_OP_ALU_POP_AFTER 82650#define CF_OP_ALU_POP2_AFTER 83651#define CF_OP_ALU_EXT 84652#define CF_OP_ALU_CONTINUE 85653#define CF_OP_ALU_BREAK 86654#define CF_OP_ALU_VALID_PIXEL_MODE 87655#define CF_OP_ALU_ELSE_AFTER 88656657/* CF_NATIVE means that r600_bytecode_cf contains pre-encoded native data */658#define CF_NATIVE 89659660enum r600_chip_class {661ISA_CC_R600,662ISA_CC_R700,663ISA_CC_EVERGREEN,664ISA_CC_CAYMAN665};666667struct r600_isa {668enum r600_chip_class hw_class;669670/* these arrays provide reverse mapping - opcode => table_index,671* typically we don't need such lookup, unless we are decoding the native672* bytecode (e.g. when reading the bytestream from llvm backend) */673unsigned *alu_op2_map;674unsigned *alu_op3_map;675unsigned *fetch_map;676unsigned *cf_map;677};678679struct r600_context;680681int r600_isa_init(struct r600_context *ctx, struct r600_isa *isa);682int r600_isa_destroy(struct r600_isa *isa);683684extern const struct alu_op_info r600_alu_op_table[];685686unsigned687r600_alu_op_table_size(void);688689const struct alu_op_info *690r600_isa_alu(unsigned op);691692const struct fetch_op_info *693r600_isa_fetch(unsigned op);694695const struct cf_op_info *696r600_isa_cf(unsigned op);697698static inline unsigned699r600_isa_alu_opcode(enum r600_chip_class chip_class, unsigned op) {700int opc = r600_isa_alu(op)->opcode[chip_class >> 1];701assert(opc != -1);702return opc;703}704705static inline unsigned706r600_isa_alu_slots(enum r600_chip_class chip_class, unsigned op) {707unsigned slots = r600_isa_alu(op)->slots[chip_class];708assert(slots != 0);709return slots;710}711712static inline unsigned713r600_isa_fetch_opcode(enum r600_chip_class chip_class, unsigned op) {714int opc = r600_isa_fetch(op)->opcode[chip_class];715assert(opc != -1);716return opc;717}718719static inline unsigned720r600_isa_cf_opcode(enum r600_chip_class chip_class, unsigned op) {721int opc = r600_isa_cf(op)->opcode[chip_class];722assert(opc != -1);723return opc;724}725726static inline unsigned727r600_isa_alu_by_opcode(struct r600_isa* isa, unsigned opcode, unsigned is_op3) {728unsigned op;729if (is_op3) {730assert(isa->alu_op3_map);731op = isa->alu_op3_map[opcode];732} else {733assert(isa->alu_op2_map);734op = isa->alu_op2_map[opcode];735}736assert(op);737return op - 1;738}739740static inline unsigned741r600_isa_fetch_by_opcode(struct r600_isa* isa, unsigned opcode) {742unsigned op;743assert(isa->fetch_map);744op = isa->fetch_map[opcode];745assert(op);746return op - 1;747}748749static inline unsigned750r600_isa_cf_by_opcode(struct r600_isa* isa, unsigned opcode, unsigned is_alu) {751unsigned op;752assert(isa->cf_map);753/* using offset for CF_ALU_xxx opcodes because they overlap with other754* CF opcodes (they use different encoding in hw) */755op = isa->cf_map[is_alu ? opcode + 0x80 : opcode];756assert(op);757return op - 1;758}759760#ifdef __cplusplus761} /* extern "C" */762#endif763764#endif /* R600_ISA_H_ */765766767