CoCalc -- radeon_uvd_enc_1

GitHub Repository: PojavLauncherTeam/mesa
Path: blob/21.2-virgl/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c
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/**************************************************************************
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 *
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 * Copyright 2018 Advanced Micro Devices, Inc.
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 * All Rights Reserved.
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a
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 * copy of this software and associated documentation files (the
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 * "Software"), to deal in the Software without restriction, including
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 * without limitation the rights to use, copy, modify, merge, publish,
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 * distribute, sub license, and/or sell copies of the Software, and to
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 * permit persons to whom the Software is furnished to do so, subject to
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 * the following conditions:
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 *
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 * The above copyright notice and this permission notice (including the
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 * next paragraph) shall be included in all copies or substantial portions
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 * of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
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 * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
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 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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 *
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 **************************************************************************/
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#include "pipe/p_video_codec.h"
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#include "radeon_uvd_enc.h"
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#include "radeon_video.h"
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#include "radeonsi/si_pipe.h"
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#include "util/u_memory.h"
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#include "util/u_video.h"
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#include "vl/vl_video_buffer.h"
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#include <stdio.h>
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#define RADEON_ENC_CS(value) (enc->cs.current.buf[enc->cs.current.cdw++] = (value))
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#define RADEON_ENC_BEGIN(cmd)                                                                      \
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   {                                                                                               \
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      uint32_t *begin = &enc->cs.current.buf[enc->cs.current.cdw++];                             \
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      RADEON_ENC_CS(cmd)
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#define RADEON_ENC_READ(buf, domain, off)                                                          \
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   radeon_uvd_enc_add_buffer(enc, (buf), RADEON_USAGE_READ, (domain), (off))
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#define RADEON_ENC_WRITE(buf, domain, off)                                                         \
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   radeon_uvd_enc_add_buffer(enc, (buf), RADEON_USAGE_WRITE, (domain), (off))
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#define RADEON_ENC_READWRITE(buf, domain, off)                                                     \
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   radeon_uvd_enc_add_buffer(enc, (buf), RADEON_USAGE_READWRITE, (domain), (off))
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#define RADEON_ENC_END()                                                                           \
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   *begin = (&enc->cs.current.buf[enc->cs.current.cdw] - begin) * 4;                             \
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   enc->total_task_size += *begin;                                                                 \
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   }
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static const unsigned index_to_shifts[4] = {24, 16, 8, 0};
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static void radeon_uvd_enc_add_buffer(struct radeon_uvd_encoder *enc, struct pb_buffer *buf,
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                                      enum radeon_bo_usage usage, enum radeon_bo_domain domain,
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                                      signed offset)
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{
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   enc->ws->cs_add_buffer(&enc->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED, domain, 0);
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   uint64_t addr;
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   addr = enc->ws->buffer_get_virtual_address(buf);
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   addr = addr + offset;
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   RADEON_ENC_CS(addr >> 32);
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   RADEON_ENC_CS(addr);
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}
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static void radeon_uvd_enc_set_emulation_prevention(struct radeon_uvd_encoder *enc, bool set)
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{
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   if (set != enc->emulation_prevention) {
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      enc->emulation_prevention = set;
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      enc->num_zeros = 0;
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   }
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}
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static void radeon_uvd_enc_output_one_byte(struct radeon_uvd_encoder *enc, unsigned char byte)
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{
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   if (enc->byte_index == 0)
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      enc->cs.current.buf[enc->cs.current.cdw] = 0;
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   enc->cs.current.buf[enc->cs.current.cdw] |=
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      ((unsigned int)(byte) << index_to_shifts[enc->byte_index]);
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   enc->byte_index++;
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   if (enc->byte_index >= 4) {
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      enc->byte_index = 0;
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      enc->cs.current.cdw++;
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   }
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}
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static void radeon_uvd_enc_emulation_prevention(struct radeon_uvd_encoder *enc, unsigned char byte)
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{
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   if (enc->emulation_prevention) {
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      if ((enc->num_zeros >= 2) &&
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          ((byte == 0x00) || (byte == 0x01) || (byte == 0x02) || (byte == 0x03))) {
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         radeon_uvd_enc_output_one_byte(enc, 0x03);
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         enc->bits_output += 8;
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         enc->num_zeros = 0;
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      }
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      enc->num_zeros = (byte == 0 ? (enc->num_zeros + 1) : 0);
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   }
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}
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static void radeon_uvd_enc_code_fixed_bits(struct radeon_uvd_encoder *enc, unsigned int value,
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                                           unsigned int num_bits)
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{
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   unsigned int bits_to_pack = 0;
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   while (num_bits > 0) {
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      unsigned int value_to_pack = value & (0xffffffff >> (32 - num_bits));
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      bits_to_pack =
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         num_bits > (32 - enc->bits_in_shifter) ? (32 - enc->bits_in_shifter) : num_bits;
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      if (bits_to_pack < num_bits)
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         value_to_pack = value_to_pack >> (num_bits - bits_to_pack);
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      enc->shifter |= value_to_pack << (32 - enc->bits_in_shifter - bits_to_pack);
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      num_bits -= bits_to_pack;
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      enc->bits_in_shifter += bits_to_pack;
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      while (enc->bits_in_shifter >= 8) {
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         unsigned char output_byte = (unsigned char)(enc->shifter >> 24);
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         enc->shifter <<= 8;
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         radeon_uvd_enc_emulation_prevention(enc, output_byte);
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         radeon_uvd_enc_output_one_byte(enc, output_byte);
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         enc->bits_in_shifter -= 8;
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         enc->bits_output += 8;
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      }
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   }
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}
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static void radeon_uvd_enc_reset(struct radeon_uvd_encoder *enc)
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{
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   enc->emulation_prevention = false;
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   enc->shifter = 0;
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   enc->bits_in_shifter = 0;
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   enc->bits_output = 0;
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   enc->num_zeros = 0;
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   enc->byte_index = 0;
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}
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static void radeon_uvd_enc_byte_align(struct radeon_uvd_encoder *enc)
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{
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   unsigned int num_padding_zeros = (32 - enc->bits_in_shifter) % 8;
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   if (num_padding_zeros > 0)
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      radeon_uvd_enc_code_fixed_bits(enc, 0, num_padding_zeros);
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}
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static void radeon_uvd_enc_flush_headers(struct radeon_uvd_encoder *enc)
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{
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   if (enc->bits_in_shifter != 0) {
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      unsigned char output_byte = (unsigned char)(enc->shifter >> 24);
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      radeon_uvd_enc_emulation_prevention(enc, output_byte);
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      radeon_uvd_enc_output_one_byte(enc, output_byte);
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      enc->bits_output += enc->bits_in_shifter;
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      enc->shifter = 0;
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      enc->bits_in_shifter = 0;
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      enc->num_zeros = 0;
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   }
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   if (enc->byte_index > 0) {
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      enc->cs.current.cdw++;
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      enc->byte_index = 0;
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   }
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}
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static void radeon_uvd_enc_code_ue(struct radeon_uvd_encoder *enc, unsigned int value)
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{
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   int x = -1;
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   unsigned int ue_code = value + 1;
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   value += 1;
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   while (value) {
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      value = (value >> 1);
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      x += 1;
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   }
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   unsigned int ue_length = (x << 1) + 1;
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   radeon_uvd_enc_code_fixed_bits(enc, ue_code, ue_length);
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}
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static void radeon_uvd_enc_code_se(struct radeon_uvd_encoder *enc, int value)
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{
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   unsigned int v = 0;
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   if (value != 0)
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      v = (value < 0 ? ((unsigned int)(0 - value) << 1) : (((unsigned int)(value) << 1) - 1));
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   radeon_uvd_enc_code_ue(enc, v);
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}
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static void radeon_uvd_enc_session_info(struct radeon_uvd_encoder *enc)
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{
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   unsigned int interface_version =
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      ((RENC_UVD_FW_INTERFACE_MAJOR_VERSION << RENC_UVD_IF_MAJOR_VERSION_SHIFT) |
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       (RENC_UVD_FW_INTERFACE_MINOR_VERSION << RENC_UVD_IF_MINOR_VERSION_SHIFT));
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   RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_SESSION_INFO);
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   RADEON_ENC_CS(0x00000000); // reserved
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   RADEON_ENC_CS(interface_version);
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   RADEON_ENC_READWRITE(enc->si->res->buf, enc->si->res->domains, 0x0);
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   RADEON_ENC_END();
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}
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static void radeon_uvd_enc_task_info(struct radeon_uvd_encoder *enc, bool need_feedback)
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{
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   enc->enc_pic.task_info.task_id++;
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   if (need_feedback)
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      enc->enc_pic.task_info.allowed_max_num_feedbacks = 1;
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   else
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      enc->enc_pic.task_info.allowed_max_num_feedbacks = 0;
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   RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_TASK_INFO);
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   enc->p_task_size = &enc->cs.current.buf[enc->cs.current.cdw++];
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   RADEON_ENC_CS(enc->enc_pic.task_info.task_id);
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   RADEON_ENC_CS(enc->enc_pic.task_info.allowed_max_num_feedbacks);
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   RADEON_ENC_END();
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}
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static void radeon_uvd_enc_session_init_hevc(struct radeon_uvd_encoder *enc)
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{
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   enc->enc_pic.session_init.aligned_picture_width = align(enc->base.width, 64);
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   enc->enc_pic.session_init.aligned_picture_height = align(enc->base.height, 16);
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   enc->enc_pic.session_init.padding_width =
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      enc->enc_pic.session_init.aligned_picture_width - enc->base.width;
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   enc->enc_pic.session_init.padding_height =
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      enc->enc_pic.session_init.aligned_picture_height - enc->base.height;
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   enc->enc_pic.session_init.pre_encode_mode = RENC_UVD_PREENCODE_MODE_NONE;
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   enc->enc_pic.session_init.pre_encode_chroma_enabled = false;
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   RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_SESSION_INIT);
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   RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_width);
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   RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_height);
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   RADEON_ENC_CS(enc->enc_pic.session_init.padding_width);
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   RADEON_ENC_CS(enc->enc_pic.session_init.padding_height);
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   RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_mode);
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   RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_chroma_enabled);
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   RADEON_ENC_END();
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}
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static void radeon_uvd_enc_layer_control(struct radeon_uvd_encoder *enc)
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{
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   enc->enc_pic.layer_ctrl.max_num_temporal_layers = 1;
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   enc->enc_pic.layer_ctrl.num_temporal_layers = 1;
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   RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_LAYER_CONTROL);
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   RADEON_ENC_CS(enc->enc_pic.layer_ctrl.max_num_temporal_layers);
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   RADEON_ENC_CS(enc->enc_pic.layer_ctrl.num_temporal_layers);
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   RADEON_ENC_END();
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}
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static void radeon_uvd_enc_layer_select(struct radeon_uvd_encoder *enc)
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{
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   enc->enc_pic.layer_sel.temporal_layer_index = 0;
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   RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_LAYER_SELECT);
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   RADEON_ENC_CS(enc->enc_pic.layer_sel.temporal_layer_index);
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   RADEON_ENC_END();
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}
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static void radeon_uvd_enc_slice_control_hevc(struct radeon_uvd_encoder *enc)
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{
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   enc->enc_pic.hevc_slice_ctrl.slice_control_mode = RENC_UVD_SLICE_CONTROL_MODE_FIXED_CTBS;
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   enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice =
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      align(enc->base.width, 64) / 64 * align(enc->base.height, 64) / 64;
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   enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice_segment =
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      enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice;
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   RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_SLICE_CONTROL);
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   RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.slice_control_mode);
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   RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice);
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   RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice_segment);
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   RADEON_ENC_END();
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}
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static void radeon_uvd_enc_spec_misc_hevc(struct radeon_uvd_encoder *enc,
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                                          struct pipe_picture_desc *picture)
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{
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   struct pipe_h265_enc_picture_desc *pic = (struct pipe_h265_enc_picture_desc *)picture;
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   enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3 =
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      pic->seq.log2_min_luma_coding_block_size_minus3;
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   enc->enc_pic.hevc_spec_misc.amp_disabled = !pic->seq.amp_enabled_flag;
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   enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled =
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      pic->seq.strong_intra_smoothing_enabled_flag;
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   enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag = pic->pic.constrained_intra_pred_flag;
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   enc->enc_pic.hevc_spec_misc.cabac_init_flag = pic->slice.cabac_init_flag;
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   enc->enc_pic.hevc_spec_misc.half_pel_enabled = 1;
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   enc->enc_pic.hevc_spec_misc.quarter_pel_enabled = 1;
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   RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_SPEC_MISC);
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   RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3);
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   RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.amp_disabled);
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   RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled);
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   RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag);
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   RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.cabac_init_flag);
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   RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.half_pel_enabled);
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   RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.quarter_pel_enabled);
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   RADEON_ENC_END();
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}
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static void radeon_uvd_enc_rc_session_init(struct radeon_uvd_encoder *enc,
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                                           struct pipe_picture_desc *picture)
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{
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   struct pipe_h265_enc_picture_desc *pic = (struct pipe_h265_enc_picture_desc *)picture;
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   enc->enc_pic.rc_session_init.vbv_buffer_level = pic->rc.vbv_buf_lv;
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   switch (pic->rc.rate_ctrl_method) {
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   case PIPE_H2645_ENC_RATE_CONTROL_METHOD_DISABLE:
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      enc->enc_pic.rc_session_init.rate_control_method = RENC_UVD_RATE_CONTROL_METHOD_NONE;
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      break;
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   case PIPE_H2645_ENC_RATE_CONTROL_METHOD_CONSTANT_SKIP:
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   case PIPE_H2645_ENC_RATE_CONTROL_METHOD_CONSTANT:
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      enc->enc_pic.rc_session_init.rate_control_method = RENC_UVD_RATE_CONTROL_METHOD_CBR;
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      break;
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   case PIPE_H2645_ENC_RATE_CONTROL_METHOD_VARIABLE_SKIP:
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   case PIPE_H2645_ENC_RATE_CONTROL_METHOD_VARIABLE:
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      enc->enc_pic.rc_session_init.rate_control_method =
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         RENC_UVD_RATE_CONTROL_METHOD_PEAK_CONSTRAINED_VBR;
318
      break;
319
   default:
320
      enc->enc_pic.rc_session_init.rate_control_method = RENC_UVD_RATE_CONTROL_METHOD_NONE;
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   }
322

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   RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_RATE_CONTROL_SESSION_INIT);
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   RADEON_ENC_CS(enc->enc_pic.rc_session_init.rate_control_method);
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   RADEON_ENC_CS(enc->enc_pic.rc_session_init.vbv_buffer_level);
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   RADEON_ENC_END();
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}
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static void radeon_uvd_enc_rc_layer_init(struct radeon_uvd_encoder *enc,
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                                         struct pipe_picture_desc *picture)
331
{
332
   struct pipe_h265_enc_picture_desc *pic = (struct pipe_h265_enc_picture_desc *)picture;
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   enc->enc_pic.rc_layer_init.target_bit_rate = pic->rc.target_bitrate;
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   enc->enc_pic.rc_layer_init.peak_bit_rate = pic->rc.peak_bitrate;
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   enc->enc_pic.rc_layer_init.frame_rate_num = pic->rc.frame_rate_num;
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   enc->enc_pic.rc_layer_init.frame_rate_den = pic->rc.frame_rate_den;
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   enc->enc_pic.rc_layer_init.vbv_buffer_size = pic->rc.vbv_buffer_size;
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   enc->enc_pic.rc_layer_init.avg_target_bits_per_picture = pic->rc.target_bits_picture;
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   enc->enc_pic.rc_layer_init.peak_bits_per_picture_integer = pic->rc.peak_bits_picture_integer;
340
   enc->enc_pic.rc_layer_init.peak_bits_per_picture_fractional = pic->rc.peak_bits_picture_fraction;
341

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   RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_RATE_CONTROL_LAYER_INIT);
343
   RADEON_ENC_CS(enc->enc_pic.rc_layer_init.target_bit_rate);
344
   RADEON_ENC_CS(enc->enc_pic.rc_layer_init.peak_bit_rate);
345
   RADEON_ENC_CS(enc->enc_pic.rc_layer_init.frame_rate_num);
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   RADEON_ENC_CS(enc->enc_pic.rc_layer_init.frame_rate_den);
347
   RADEON_ENC_CS(enc->enc_pic.rc_layer_init.vbv_buffer_size);
348
   RADEON_ENC_CS(enc->enc_pic.rc_layer_init.avg_target_bits_per_picture);
349
   RADEON_ENC_CS(enc->enc_pic.rc_layer_init.peak_bits_per_picture_integer);
350
   RADEON_ENC_CS(enc->enc_pic.rc_layer_init.peak_bits_per_picture_fractional);
351
   RADEON_ENC_END();
352
}
353

354
static void radeon_uvd_enc_deblocking_filter_hevc(struct radeon_uvd_encoder *enc,
355
                                                  struct pipe_picture_desc *picture)
356
{
357
   struct pipe_h265_enc_picture_desc *pic = (struct pipe_h265_enc_picture_desc *)picture;
358
   enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled =
359
      pic->slice.slice_loop_filter_across_slices_enabled_flag;
360
   enc->enc_pic.hevc_deblock.deblocking_filter_disabled =
361
      pic->slice.slice_deblocking_filter_disabled_flag;
362
   enc->enc_pic.hevc_deblock.beta_offset_div2 = pic->slice.slice_beta_offset_div2;
363
   enc->enc_pic.hevc_deblock.tc_offset_div2 = pic->slice.slice_tc_offset_div2;
364
   enc->enc_pic.hevc_deblock.cb_qp_offset = pic->slice.slice_cb_qp_offset;
365
   enc->enc_pic.hevc_deblock.cr_qp_offset = pic->slice.slice_cr_qp_offset;
366

367
   RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_DEBLOCKING_FILTER);
368
   RADEON_ENC_CS(enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled);
369
   RADEON_ENC_CS(enc->enc_pic.hevc_deblock.deblocking_filter_disabled);
370
   RADEON_ENC_CS(enc->enc_pic.hevc_deblock.beta_offset_div2);
371
   RADEON_ENC_CS(enc->enc_pic.hevc_deblock.tc_offset_div2);
372
   RADEON_ENC_CS(enc->enc_pic.hevc_deblock.cb_qp_offset);
373
   RADEON_ENC_CS(enc->enc_pic.hevc_deblock.cr_qp_offset);
374
   RADEON_ENC_END();
375
}
376

377
static void radeon_uvd_enc_quality_params(struct radeon_uvd_encoder *enc)
378
{
379
   enc->enc_pic.quality_params.vbaq_mode = 0;
380
   enc->enc_pic.quality_params.scene_change_sensitivity = 0;
381
   enc->enc_pic.quality_params.scene_change_min_idr_interval = 0;
382

383
   RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_QUALITY_PARAMS);
384
   RADEON_ENC_CS(enc->enc_pic.quality_params.vbaq_mode);
385
   RADEON_ENC_CS(enc->enc_pic.quality_params.scene_change_sensitivity);
386
   RADEON_ENC_CS(enc->enc_pic.quality_params.scene_change_min_idr_interval);
387
   RADEON_ENC_END();
388
}
389

390
static void radeon_uvd_enc_nalu_sps_hevc(struct radeon_uvd_encoder *enc)
391
{
392
   RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_INSERT_NALU_BUFFER);
393
   RADEON_ENC_CS(RENC_UVD_NALU_TYPE_SPS);
394
   uint32_t *size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++];
395
   int i;
396

397
   radeon_uvd_enc_reset(enc);
398
   radeon_uvd_enc_set_emulation_prevention(enc, false);
399
   radeon_uvd_enc_code_fixed_bits(enc, 0x00000001, 32);
400
   radeon_uvd_enc_code_fixed_bits(enc, 0x4201, 16);
401
   radeon_uvd_enc_byte_align(enc);
402
   radeon_uvd_enc_set_emulation_prevention(enc, true);
403
   radeon_uvd_enc_code_fixed_bits(enc, 0x0, 4);
404
   radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1, 3);
405
   radeon_uvd_enc_code_fixed_bits(enc, 0x1, 1);
406
   radeon_uvd_enc_code_fixed_bits(enc, 0x0, 2);
407
   radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.general_tier_flag, 1);
408
   radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.general_profile_idc, 5);
409
   radeon_uvd_enc_code_fixed_bits(enc, 0x60000000, 32);
410
   radeon_uvd_enc_code_fixed_bits(enc, 0xb0000000, 32);
411
   radeon_uvd_enc_code_fixed_bits(enc, 0x0, 16);
412
   radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.general_level_idc, 8);
413

414
   for (i = 0; i < (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i++)
415
      radeon_uvd_enc_code_fixed_bits(enc, 0x0, 2);
416

417
   if ((enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1) > 0) {
418
      for (i = (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i < 8; i++)
419
         radeon_uvd_enc_code_fixed_bits(enc, 0x0, 2);
420
   }
421

422
   radeon_uvd_enc_code_ue(enc, 0x0);
423
   radeon_uvd_enc_code_ue(enc, enc->enc_pic.chroma_format_idc);
424
   radeon_uvd_enc_code_ue(enc, enc->enc_pic.session_init.aligned_picture_width);
425
   radeon_uvd_enc_code_ue(enc, enc->enc_pic.session_init.aligned_picture_height);
426

427
   int conformance_window_flag = (enc->enc_pic.crop_top > 0) || (enc->enc_pic.crop_bottom > 0) ||
428
                                       (enc->enc_pic.crop_left > 0) || (enc->enc_pic.crop_right > 0)
429
                                    ? 0x1
430
                                    : 0x0;
431
   radeon_uvd_enc_code_fixed_bits(enc, conformance_window_flag, 1);
432

433
   if (conformance_window_flag == 1) {
434
      radeon_uvd_enc_code_ue(enc, enc->enc_pic.crop_left);
435
      radeon_uvd_enc_code_ue(enc, enc->enc_pic.crop_right);
436
      radeon_uvd_enc_code_ue(enc, enc->enc_pic.crop_top);
437
      radeon_uvd_enc_code_ue(enc, enc->enc_pic.crop_bottom);
438
   }
439

440
   radeon_uvd_enc_code_ue(enc, enc->enc_pic.bit_depth_luma_minus8);
441
   radeon_uvd_enc_code_ue(enc, enc->enc_pic.bit_depth_chroma_minus8);
442
   radeon_uvd_enc_code_ue(enc, enc->enc_pic.log2_max_poc - 4);
443
   radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
444
   radeon_uvd_enc_code_ue(enc, 1);
445
   radeon_uvd_enc_code_ue(enc, 0x0);
446
   radeon_uvd_enc_code_ue(enc, 0x0);
447
   radeon_uvd_enc_code_ue(enc, enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3);
448
   /* Only support CTBSize 64 */
449
   radeon_uvd_enc_code_ue(
450
      enc, 6 - (enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3 + 3));
451
   radeon_uvd_enc_code_ue(enc, enc->enc_pic.log2_min_transform_block_size_minus2);
452
   radeon_uvd_enc_code_ue(enc, enc->enc_pic.log2_diff_max_min_transform_block_size);
453
   radeon_uvd_enc_code_ue(enc, enc->enc_pic.max_transform_hierarchy_depth_inter);
454
   radeon_uvd_enc_code_ue(enc, enc->enc_pic.max_transform_hierarchy_depth_intra);
455

456
   radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
457
   radeon_uvd_enc_code_fixed_bits(enc, !enc->enc_pic.hevc_spec_misc.amp_disabled, 1);
458
   radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.sample_adaptive_offset_enabled_flag, 1);
459
   radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.pcm_enabled_flag, 1);
460

461
   radeon_uvd_enc_code_ue(enc, 1);
462
   radeon_uvd_enc_code_ue(enc, 1);
463
   radeon_uvd_enc_code_ue(enc, 0);
464
   radeon_uvd_enc_code_ue(enc, 0);
465
   radeon_uvd_enc_code_fixed_bits(enc, 0x1, 1);
466

467
   radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
468

469
   radeon_uvd_enc_code_fixed_bits(enc, 0, 1);
470
   radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled,
471
                                  1);
472

473
   radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
474

475
   radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
476

477
   radeon_uvd_enc_code_fixed_bits(enc, 0x1, 1);
478

479
   radeon_uvd_enc_byte_align(enc);
480
   radeon_uvd_enc_flush_headers(enc);
481
   *size_in_bytes = (enc->bits_output + 7) / 8;
482
   RADEON_ENC_END();
483
}
484

485
static void radeon_uvd_enc_nalu_pps_hevc(struct radeon_uvd_encoder *enc)
486
{
487
   RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_INSERT_NALU_BUFFER);
488
   RADEON_ENC_CS(RENC_UVD_NALU_TYPE_PPS);
489
   uint32_t *size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++];
490
   radeon_uvd_enc_reset(enc);
491
   radeon_uvd_enc_set_emulation_prevention(enc, false);
492
   radeon_uvd_enc_code_fixed_bits(enc, 0x00000001, 32);
493
   radeon_uvd_enc_code_fixed_bits(enc, 0x4401, 16);
494
   radeon_uvd_enc_byte_align(enc);
495
   radeon_uvd_enc_set_emulation_prevention(enc, true);
496
   radeon_uvd_enc_code_ue(enc, 0x0);
497
   radeon_uvd_enc_code_ue(enc, 0x0);
498
   radeon_uvd_enc_code_fixed_bits(enc, 0x1, 1);
499
   radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1); /* output_flag_resent_flag */
500
   radeon_uvd_enc_code_fixed_bits(enc, 0x0, 3); /* num_extra_slice_header_bits */
501
   radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
502
   radeon_uvd_enc_code_fixed_bits(enc, 0x1, 1);
503
   radeon_uvd_enc_code_ue(enc, 0x0);
504
   radeon_uvd_enc_code_ue(enc, 0x0);
505
   radeon_uvd_enc_code_se(enc, 0x0);
506
   radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag, 1);
507
   radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
508
   if (enc->enc_pic.rc_session_init.rate_control_method == RENC_UVD_RATE_CONTROL_METHOD_NONE)
509
      radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
510
   else {
511
      radeon_uvd_enc_code_fixed_bits(enc, 0x1, 1);
512
      radeon_uvd_enc_code_ue(enc, 0x0);
513
   }
514
   radeon_uvd_enc_code_se(enc, enc->enc_pic.hevc_deblock.cb_qp_offset);
515
   radeon_uvd_enc_code_se(enc, enc->enc_pic.hevc_deblock.cr_qp_offset);
516
   radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
517
   radeon_uvd_enc_code_fixed_bits(enc, 0x0, 2);
518
   radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
519
   radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
520
   radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
521
   radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled,
522
                                  1);
523
   radeon_uvd_enc_code_fixed_bits(enc, 0x1, 1);
524
   radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
525
   radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.deblocking_filter_disabled, 1);
526

527
   if (!enc->enc_pic.hevc_deblock.deblocking_filter_disabled) {
528
      radeon_uvd_enc_code_se(enc, enc->enc_pic.hevc_deblock.beta_offset_div2);
529
      radeon_uvd_enc_code_se(enc, enc->enc_pic.hevc_deblock.tc_offset_div2);
530
   }
531

532
   radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
533
   radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
534
   radeon_uvd_enc_code_ue(enc, enc->enc_pic.log2_parallel_merge_level_minus2);
535
   radeon_uvd_enc_code_fixed_bits(enc, 0x0, 2);
536

537
   radeon_uvd_enc_code_fixed_bits(enc, 0x1, 1);
538

539
   radeon_uvd_enc_byte_align(enc);
540
   radeon_uvd_enc_flush_headers(enc);
541
   *size_in_bytes = (enc->bits_output + 7) / 8;
542
   RADEON_ENC_END();
543
}
544

545
static void radeon_uvd_enc_nalu_vps_hevc(struct radeon_uvd_encoder *enc)
546
{
547
   RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_INSERT_NALU_BUFFER);
548
   RADEON_ENC_CS(RENC_UVD_NALU_TYPE_VPS);
549
   uint32_t *size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++];
550
   int i;
551

552
   radeon_uvd_enc_reset(enc);
553
   radeon_uvd_enc_set_emulation_prevention(enc, false);
554
   radeon_uvd_enc_code_fixed_bits(enc, 0x00000001, 32);
555
   radeon_uvd_enc_code_fixed_bits(enc, 0x4001, 16);
556
   radeon_uvd_enc_byte_align(enc);
557
   radeon_uvd_enc_set_emulation_prevention(enc, true);
558

559
   radeon_uvd_enc_code_fixed_bits(enc, 0x0, 4);
560
   radeon_uvd_enc_code_fixed_bits(enc, 0x3, 2);
561
   radeon_uvd_enc_code_fixed_bits(enc, 0x0, 6);
562
   radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1, 3);
563
   radeon_uvd_enc_code_fixed_bits(enc, 0x1, 1);
564
   radeon_uvd_enc_code_fixed_bits(enc, 0xffff, 16);
565
   radeon_uvd_enc_code_fixed_bits(enc, 0x0, 2);
566
   radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.general_tier_flag, 1);
567
   radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.general_profile_idc, 5);
568
   radeon_uvd_enc_code_fixed_bits(enc, 0x60000000, 32);
569
   radeon_uvd_enc_code_fixed_bits(enc, 0xb0000000, 32);
570
   radeon_uvd_enc_code_fixed_bits(enc, 0x0, 16);
571
   radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.general_level_idc, 8);
572

573
   for (i = 0; i < (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i++)
574
      radeon_uvd_enc_code_fixed_bits(enc, 0x0, 2);
575

576
   if ((enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1) > 0) {
577
      for (i = (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i < 8; i++)
578
         radeon_uvd_enc_code_fixed_bits(enc, 0x0, 2);
579
   }
580

581
   radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
582
   radeon_uvd_enc_code_ue(enc, 0x1);
583
   radeon_uvd_enc_code_ue(enc, 0x0);
584
   radeon_uvd_enc_code_ue(enc, 0x0);
585

586
   radeon_uvd_enc_code_fixed_bits(enc, 0x0, 6);
587
   radeon_uvd_enc_code_ue(enc, 0x0);
588
   radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
589
   radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
590

591
   radeon_uvd_enc_code_fixed_bits(enc, 0x1, 1);
592

593
   radeon_uvd_enc_byte_align(enc);
594
   radeon_uvd_enc_flush_headers(enc);
595
   *size_in_bytes = (enc->bits_output + 7) / 8;
596
   RADEON_ENC_END();
597
}
598

599
static void radeon_uvd_enc_nalu_aud_hevc(struct radeon_uvd_encoder *enc)
600
{
601
   RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_INSERT_NALU_BUFFER);
602
   RADEON_ENC_CS(RENC_UVD_NALU_TYPE_AUD);
603
   uint32_t *size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++];
604
   radeon_uvd_enc_reset(enc);
605
   radeon_uvd_enc_set_emulation_prevention(enc, false);
606
   radeon_uvd_enc_code_fixed_bits(enc, 0x00000001, 32);
607
   radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
608
   radeon_uvd_enc_code_fixed_bits(enc, 35, 6);
609
   radeon_uvd_enc_code_fixed_bits(enc, 0x0, 6);
610
   radeon_uvd_enc_code_fixed_bits(enc, 0x1, 3);
611
   radeon_uvd_enc_byte_align(enc);
612
   radeon_uvd_enc_set_emulation_prevention(enc, true);
613
   switch (enc->enc_pic.picture_type) {
614
   case PIPE_H2645_ENC_PICTURE_TYPE_I:
615
   case PIPE_H2645_ENC_PICTURE_TYPE_IDR:
616
      radeon_uvd_enc_code_fixed_bits(enc, 0x00, 3);
617
      break;
618
   case PIPE_H2645_ENC_PICTURE_TYPE_P:
619
      radeon_uvd_enc_code_fixed_bits(enc, 0x01, 3);
620
      break;
621
   case PIPE_H2645_ENC_PICTURE_TYPE_B:
622
      radeon_uvd_enc_code_fixed_bits(enc, 0x02, 3);
623
      break;
624
   default:
625
      assert(0 && "Unsupported picture type!");
626
   }
627

628
   radeon_uvd_enc_code_fixed_bits(enc, 0x1, 1);
629

630
   radeon_uvd_enc_byte_align(enc);
631
   radeon_uvd_enc_flush_headers(enc);
632
   *size_in_bytes = (enc->bits_output + 7) / 8;
633
   RADEON_ENC_END();
634
}
635

636
static void radeon_uvd_enc_slice_header_hevc(struct radeon_uvd_encoder *enc)
637
{
638
   uint32_t instruction[RENC_UVD_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
639
   uint32_t num_bits[RENC_UVD_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
640
   unsigned int inst_index = 0;
641
   unsigned int bit_index = 0;
642
   unsigned int bits_copied = 0;
643
   RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_SLICE_HEADER);
644
   radeon_uvd_enc_reset(enc);
645
   radeon_uvd_enc_set_emulation_prevention(enc, false);
646

647
   radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
648
   radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.nal_unit_type, 6);
649
   radeon_uvd_enc_code_fixed_bits(enc, 0x0, 6);
650
   radeon_uvd_enc_code_fixed_bits(enc, 0x1, 3);
651

652
   radeon_uvd_enc_flush_headers(enc);
653
   bit_index++;
654
   instruction[inst_index] = RENC_UVD_HEADER_INSTRUCTION_COPY;
655
   num_bits[inst_index] = enc->bits_output - bits_copied;
656
   bits_copied = enc->bits_output;
657
   inst_index++;
658

659
   instruction[inst_index] = RENC_UVD_HEADER_INSTRUCTION_FIRST_SLICE;
660
   inst_index++;
661

662
   if ((enc->enc_pic.nal_unit_type >= 16) && (enc->enc_pic.nal_unit_type <= 23))
663
      radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
664

665
   radeon_uvd_enc_code_ue(enc, 0x0);
666

667
   radeon_uvd_enc_flush_headers(enc);
668
   bit_index++;
669
   instruction[inst_index] = RENC_UVD_HEADER_INSTRUCTION_COPY;
670
   num_bits[inst_index] = enc->bits_output - bits_copied;
671
   bits_copied = enc->bits_output;
672
   inst_index++;
673

674
   instruction[inst_index] = RENC_UVD_HEADER_INSTRUCTION_SLICE_SEGMENT;
675
   inst_index++;
676

677
   instruction[inst_index] = RENC_UVD_HEADER_INSTRUCTION_DEPENDENT_SLICE_END;
678
   inst_index++;
679

680
   switch (enc->enc_pic.picture_type) {
681
   case PIPE_H2645_ENC_PICTURE_TYPE_I:
682
   case PIPE_H2645_ENC_PICTURE_TYPE_IDR:
683
      radeon_uvd_enc_code_ue(enc, 0x2);
684
      break;
685
   case PIPE_H2645_ENC_PICTURE_TYPE_P:
686
   case PIPE_H2645_ENC_PICTURE_TYPE_SKIP:
687
      radeon_uvd_enc_code_ue(enc, 0x1);
688
      break;
689
   case PIPE_H2645_ENC_PICTURE_TYPE_B:
690
      radeon_uvd_enc_code_ue(enc, 0x0);
691
      break;
692
   default:
693
      radeon_uvd_enc_code_ue(enc, 0x1);
694
   }
695

696
   if ((enc->enc_pic.nal_unit_type != 19) && (enc->enc_pic.nal_unit_type != 20)) {
697
      radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.pic_order_cnt, enc->enc_pic.log2_max_poc);
698
      if (enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_P)
699
         radeon_uvd_enc_code_fixed_bits(enc, 0x1, 1);
700
      else {
701
         radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
702
         radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
703
         radeon_uvd_enc_code_ue(enc, 0x0);
704
         radeon_uvd_enc_code_ue(enc, 0x0);
705
      }
706
   }
707

708
   if (enc->enc_pic.sample_adaptive_offset_enabled_flag)
709
      radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1); /* slice_sao_luma_flag */
710

711
   if ((enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_P) ||
712
       (enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_B)) {
713
      radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
714
      radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.cabac_init_flag, 1);
715
      radeon_uvd_enc_code_ue(enc, 5 - enc->enc_pic.max_num_merge_cand);
716
   }
717

718
   radeon_uvd_enc_flush_headers(enc);
719
   bit_index++;
720
   instruction[inst_index] = RENC_UVD_HEADER_INSTRUCTION_COPY;
721
   num_bits[inst_index] = enc->bits_output - bits_copied;
722
   bits_copied = enc->bits_output;
723
   inst_index++;
724

725
   instruction[inst_index] = RENC_UVD_HEADER_INSTRUCTION_SLICE_QP_DELTA;
726
   inst_index++;
727

728
   if ((enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled) &&
729
       (!enc->enc_pic.hevc_deblock.deblocking_filter_disabled)) {
730
      radeon_uvd_enc_code_fixed_bits(
731
         enc, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled, 1);
732

733
      radeon_uvd_enc_flush_headers(enc);
734
      bit_index++;
735
      instruction[inst_index] = RENC_UVD_HEADER_INSTRUCTION_COPY;
736
      num_bits[inst_index] = enc->bits_output - bits_copied;
737
      bits_copied = enc->bits_output;
738
      inst_index++;
739
   }
740

741
   instruction[inst_index] = RENC_UVD_HEADER_INSTRUCTION_END;
742

743
   for (int i = bit_index; i < RENC_UVD_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS; i++)
744
      RADEON_ENC_CS(0x00000000);
745

746
   for (int j = 0; j < RENC_UVD_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS; j++) {
747
      RADEON_ENC_CS(instruction[j]);
748
      RADEON_ENC_CS(num_bits[j]);
749
   }
750

751
   RADEON_ENC_END();
752
}
753

754
static void radeon_uvd_enc_ctx(struct radeon_uvd_encoder *enc)
755
{
756
   struct si_screen *sscreen = (struct si_screen *)enc->screen;
757

758
   enc->enc_pic.ctx_buf.swizzle_mode = 0;
759
   if (sscreen->info.chip_class < GFX9) {
760
      enc->enc_pic.ctx_buf.rec_luma_pitch = (enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe);
761
      enc->enc_pic.ctx_buf.rec_chroma_pitch =
762
         (enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe);
763
   } else {
764
      enc->enc_pic.ctx_buf.rec_luma_pitch = enc->luma->u.gfx9.surf_pitch * enc->luma->bpe;
765
      enc->enc_pic.ctx_buf.rec_chroma_pitch = enc->chroma->u.gfx9.surf_pitch * enc->chroma->bpe;
766
   }
767
   enc->enc_pic.ctx_buf.num_reconstructed_pictures = 2;
768

769
   RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_ENCODE_CONTEXT_BUFFER);
770
   RADEON_ENC_READWRITE(enc->cpb.res->buf, enc->cpb.res->domains, 0);
771
   RADEON_ENC_CS(0x00000000); // reserved
772
   RADEON_ENC_CS(enc->enc_pic.ctx_buf.swizzle_mode);
773
   RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_luma_pitch);
774
   RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_chroma_pitch);
775
   RADEON_ENC_CS(enc->enc_pic.ctx_buf.num_reconstructed_pictures);
776
   /* reconstructed_picture_1_luma_offset */
777
   RADEON_ENC_CS(0x00000000);
778
   /* reconstructed_picture_1_chroma_offset */
779
   RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_chroma_pitch * align(enc->base.height, 16));
780
   /* reconstructed_picture_2_luma_offset */
781
   RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_luma_pitch * align(enc->base.height, 16) * 3 / 2);
782
   /* reconstructed_picture_2_chroma_offset */
783
   RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_chroma_pitch * align(enc->base.height, 16) * 5 / 2);
784

785
   for (int i = 0; i < 136; i++)
786
      RADEON_ENC_CS(0x00000000);
787

788
   RADEON_ENC_END();
789
}
790

791
static void radeon_uvd_enc_bitstream(struct radeon_uvd_encoder *enc)
792
{
793
   enc->enc_pic.bit_buf.mode = RENC_UVD_SWIZZLE_MODE_LINEAR;
794
   enc->enc_pic.bit_buf.video_bitstream_buffer_size = enc->bs_size;
795
   enc->enc_pic.bit_buf.video_bitstream_data_offset = 0;
796

797
   RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_VIDEO_BITSTREAM_BUFFER);
798
   RADEON_ENC_CS(enc->enc_pic.bit_buf.mode);
799
   RADEON_ENC_WRITE(enc->bs_handle, RADEON_DOMAIN_GTT, 0);
800
   RADEON_ENC_CS(enc->enc_pic.bit_buf.video_bitstream_buffer_size);
801
   RADEON_ENC_CS(enc->enc_pic.bit_buf.video_bitstream_data_offset);
802
   RADEON_ENC_END();
803
}
804

805
static void radeon_uvd_enc_feedback(struct radeon_uvd_encoder *enc)
806
{
807
   enc->enc_pic.fb_buf.mode = RENC_UVD_FEEDBACK_BUFFER_MODE_LINEAR;
808
   enc->enc_pic.fb_buf.feedback_buffer_size = 16;
809
   enc->enc_pic.fb_buf.feedback_data_size = 40;
810

811
   RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_FEEDBACK_BUFFER);
812
   RADEON_ENC_CS(enc->enc_pic.fb_buf.mode);
813
   RADEON_ENC_WRITE(enc->fb->res->buf, enc->fb->res->domains, 0x0);
814
   RADEON_ENC_CS(enc->enc_pic.fb_buf.feedback_buffer_size);
815
   RADEON_ENC_CS(enc->enc_pic.fb_buf.feedback_data_size);
816
   RADEON_ENC_END();
817
}
818

819
static void radeon_uvd_enc_intra_refresh(struct radeon_uvd_encoder *enc)
820
{
821
   enc->enc_pic.intra_ref.intra_refresh_mode = RENC_UVD_INTRA_REFRESH_MODE_NONE;
822
   enc->enc_pic.intra_ref.offset = 0;
823
   enc->enc_pic.intra_ref.region_size = 0;
824

825
   RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_INTRA_REFRESH);
826
   RADEON_ENC_CS(enc->enc_pic.intra_ref.intra_refresh_mode);
827
   RADEON_ENC_CS(enc->enc_pic.intra_ref.offset);
828
   RADEON_ENC_CS(enc->enc_pic.intra_ref.region_size);
829
   RADEON_ENC_END();
830
}
831

832
static void radeon_uvd_enc_rc_per_pic(struct radeon_uvd_encoder *enc,
833
                                      struct pipe_picture_desc *picture)
834
{
835
   struct pipe_h265_enc_picture_desc *pic = (struct pipe_h265_enc_picture_desc *)picture;
836
   enc->enc_pic.rc_per_pic.qp = pic->rc.quant_i_frames;
837
   enc->enc_pic.rc_per_pic.min_qp_app = 0;
838
   enc->enc_pic.rc_per_pic.max_qp_app = 51;
839
   enc->enc_pic.rc_per_pic.max_au_size = 0;
840
   enc->enc_pic.rc_per_pic.enabled_filler_data = pic->rc.fill_data_enable;
841
   enc->enc_pic.rc_per_pic.skip_frame_enable = false;
842
   enc->enc_pic.rc_per_pic.enforce_hrd = pic->rc.enforce_hrd;
843

844
   RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_RATE_CONTROL_PER_PICTURE);
845
   RADEON_ENC_CS(enc->enc_pic.rc_per_pic.qp);
846
   RADEON_ENC_CS(enc->enc_pic.rc_per_pic.min_qp_app);
847
   RADEON_ENC_CS(enc->enc_pic.rc_per_pic.max_qp_app);
848
   RADEON_ENC_CS(enc->enc_pic.rc_per_pic.max_au_size);
849
   RADEON_ENC_CS(enc->enc_pic.rc_per_pic.enabled_filler_data);
850
   RADEON_ENC_CS(enc->enc_pic.rc_per_pic.skip_frame_enable);
851
   RADEON_ENC_CS(enc->enc_pic.rc_per_pic.enforce_hrd);
852
   RADEON_ENC_END();
853
}
854

855
static void radeon_uvd_enc_encode_params_hevc(struct radeon_uvd_encoder *enc)
856
{
857
   struct si_screen *sscreen = (struct si_screen *)enc->screen;
858
   switch (enc->enc_pic.picture_type) {
859
   case PIPE_H2645_ENC_PICTURE_TYPE_I:
860
   case PIPE_H2645_ENC_PICTURE_TYPE_IDR:
861
      enc->enc_pic.enc_params.pic_type = RENC_UVD_PICTURE_TYPE_I;
862
      break;
863
   case PIPE_H2645_ENC_PICTURE_TYPE_P:
864
      enc->enc_pic.enc_params.pic_type = RENC_UVD_PICTURE_TYPE_P;
865
      break;
866
   case PIPE_H2645_ENC_PICTURE_TYPE_SKIP:
867
      enc->enc_pic.enc_params.pic_type = RENC_UVD_PICTURE_TYPE_P_SKIP;
868
      break;
869
   case PIPE_H2645_ENC_PICTURE_TYPE_B:
870
      enc->enc_pic.enc_params.pic_type = RENC_UVD_PICTURE_TYPE_B;
871
      break;
872
   default:
873
      enc->enc_pic.enc_params.pic_type = RENC_UVD_PICTURE_TYPE_I;
874
   }
875

876
   enc->enc_pic.enc_params.allowed_max_bitstream_size = enc->bs_size;
877
   if (sscreen->info.chip_class < GFX9) {
878
      enc->enc_pic.enc_params.input_pic_luma_pitch =
879
         (enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe);
880
      enc->enc_pic.enc_params.input_pic_chroma_pitch =
881
         (enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe);
882
   } else {
883
      enc->enc_pic.enc_params.input_pic_luma_pitch = enc->luma->u.gfx9.surf_pitch * enc->luma->bpe;
884
      enc->enc_pic.enc_params.input_pic_chroma_pitch =
885
         enc->chroma->u.gfx9.surf_pitch * enc->chroma->bpe;
886
   }
887
   enc->enc_pic.enc_params.input_pic_swizzle_mode = RENC_UVD_SWIZZLE_MODE_LINEAR;
888

889
   if (enc->enc_pic.enc_params.pic_type == RENC_UVD_PICTURE_TYPE_I)
890
      enc->enc_pic.enc_params.reference_picture_index = 0xFFFFFFFF;
891
   else
892
      enc->enc_pic.enc_params.reference_picture_index = (enc->enc_pic.frame_num - 1) % 2;
893

894
   enc->enc_pic.enc_params.reconstructed_picture_index = enc->enc_pic.frame_num % 2;
895

896
   RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_ENCODE_PARAMS);
897
   RADEON_ENC_CS(enc->enc_pic.enc_params.pic_type);
898
   RADEON_ENC_CS(enc->enc_pic.enc_params.allowed_max_bitstream_size);
899

900
   if (sscreen->info.chip_class < GFX9) {
901
      RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, (uint64_t)enc->luma->u.legacy.level[0].offset_256B * 256);
902
      RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, (uint64_t)enc->chroma->u.legacy.level[0].offset_256B * 256);
903
   } else {
904
      RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->luma->u.gfx9.surf_offset);
905
      RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->chroma->u.gfx9.surf_offset);
906
   }
907
   RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_luma_pitch);
908
   RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_chroma_pitch);
909
   RADEON_ENC_CS(0x00000000); // reserved
910
   RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_swizzle_mode);
911
   RADEON_ENC_CS(enc->enc_pic.enc_params.reference_picture_index);
912
   RADEON_ENC_CS(enc->enc_pic.enc_params.reconstructed_picture_index);
913
   RADEON_ENC_END();
914
}
915

916
static void radeon_uvd_enc_op_init(struct radeon_uvd_encoder *enc)
917
{
918
   RADEON_ENC_BEGIN(RENC_UVD_IB_OP_INITIALIZE);
919
   RADEON_ENC_END();
920
}
921

922
static void radeon_uvd_enc_op_close(struct radeon_uvd_encoder *enc)
923
{
924
   RADEON_ENC_BEGIN(RENC_UVD_IB_OP_CLOSE_SESSION);
925
   RADEON_ENC_END();
926
}
927

928
static void radeon_uvd_enc_op_enc(struct radeon_uvd_encoder *enc)
929
{
930
   RADEON_ENC_BEGIN(RENC_UVD_IB_OP_ENCODE);
931
   RADEON_ENC_END();
932
}
933

934
static void radeon_uvd_enc_op_init_rc(struct radeon_uvd_encoder *enc)
935
{
936
   RADEON_ENC_BEGIN(RENC_UVD_IB_OP_INIT_RC);
937
   RADEON_ENC_END();
938
}
939

940
static void radeon_uvd_enc_op_init_rc_vbv(struct radeon_uvd_encoder *enc)
941
{
942
   RADEON_ENC_BEGIN(RENC_UVD_IB_OP_INIT_RC_VBV_BUFFER_LEVEL);
943
   RADEON_ENC_END();
944
}
945

946
static void radeon_uvd_enc_op_speed(struct radeon_uvd_encoder *enc)
947
{
948
   RADEON_ENC_BEGIN(RENC_UVD_IB_OP_SET_SPEED_ENCODING_MODE);
949
   RADEON_ENC_END();
950
}
951

952
static void begin(struct radeon_uvd_encoder *enc, struct pipe_picture_desc *pic)
953
{
954
   radeon_uvd_enc_session_info(enc);
955
   enc->total_task_size = 0;
956
   radeon_uvd_enc_task_info(enc, enc->need_feedback);
957
   radeon_uvd_enc_op_init(enc);
958

959
   radeon_uvd_enc_session_init_hevc(enc);
960
   radeon_uvd_enc_slice_control_hevc(enc);
961
   radeon_uvd_enc_spec_misc_hevc(enc, pic);
962
   radeon_uvd_enc_deblocking_filter_hevc(enc, pic);
963

964
   radeon_uvd_enc_layer_control(enc);
965
   radeon_uvd_enc_rc_session_init(enc, pic);
966
   radeon_uvd_enc_quality_params(enc);
967
   radeon_uvd_enc_layer_select(enc);
968
   radeon_uvd_enc_rc_layer_init(enc, pic);
969
   radeon_uvd_enc_layer_select(enc);
970
   radeon_uvd_enc_rc_per_pic(enc, pic);
971
   radeon_uvd_enc_op_init_rc(enc);
972
   radeon_uvd_enc_op_init_rc_vbv(enc);
973
   *enc->p_task_size = (enc->total_task_size);
974
}
975

976
static void encode(struct radeon_uvd_encoder *enc)
977
{
978
   radeon_uvd_enc_session_info(enc);
979
   enc->total_task_size = 0;
980
   radeon_uvd_enc_task_info(enc, enc->need_feedback);
981

982
   radeon_uvd_enc_nalu_aud_hevc(enc);
983

984
   if (enc->enc_pic.is_iframe) {
985
      radeon_uvd_enc_nalu_vps_hevc(enc);
986
      radeon_uvd_enc_nalu_pps_hevc(enc);
987
      radeon_uvd_enc_nalu_sps_hevc(enc);
988
   }
989
   radeon_uvd_enc_slice_header_hevc(enc);
990
   radeon_uvd_enc_encode_params_hevc(enc);
991

992
   radeon_uvd_enc_ctx(enc);
993
   radeon_uvd_enc_bitstream(enc);
994
   radeon_uvd_enc_feedback(enc);
995
   radeon_uvd_enc_intra_refresh(enc);
996

997
   radeon_uvd_enc_op_speed(enc);
998
   radeon_uvd_enc_op_enc(enc);
999
   *enc->p_task_size = (enc->total_task_size);
1000
}
1001

1002
static void destroy(struct radeon_uvd_encoder *enc)
1003
{
1004
   radeon_uvd_enc_session_info(enc);
1005
   enc->total_task_size = 0;
1006
   radeon_uvd_enc_task_info(enc, enc->need_feedback);
1007
   radeon_uvd_enc_op_close(enc);
1008
   *enc->p_task_size = (enc->total_task_size);
1009
}
1010

1011
void radeon_uvd_enc_1_1_init(struct radeon_uvd_encoder *enc)
1012
{
1013
   enc->begin = begin;
1014
   enc->encode = encode;
1015
   enc->destroy = destroy;
1016
}
1017

1018
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