CoCalc -- radeon_vcn_enc_1

GitHub Repository: PojavLauncherTeam/mesa
Path: blob/21.2-virgl/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
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/**************************************************************************
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 *
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 * Copyright 2017 Advanced Micro Devices, Inc.
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 * All Rights Reserved.
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a
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 * copy of this software and associated documentation files (the
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 * "Software"), to deal in the Software without restriction, including
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 * without limitation the rights to use, copy, modify, merge, publish,
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 * distribute, sub license, and/or sell copies of the Software, and to
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 * permit persons to whom the Software is furnished to do so, subject to
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 * the following conditions:
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 *
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 * The above copyright notice and this permission notice (including the
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 * next paragraph) shall be included in all copies or substantial portions
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 * of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
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 * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
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 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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 *
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 **************************************************************************/
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#include "pipe/p_video_codec.h"
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#include "radeon_vcn_enc.h"
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#include "radeon_video.h"
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#include "si_pipe.h"
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#include "util/u_video.h"
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#include <stdio.h>
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#define RENCODE_FW_INTERFACE_MAJOR_VERSION 1
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#define RENCODE_FW_INTERFACE_MINOR_VERSION 2
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#define RENCODE_IB_PARAM_SESSION_INFO              0x00000001
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#define RENCODE_IB_PARAM_TASK_INFO                 0x00000002
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#define RENCODE_IB_PARAM_SESSION_INIT              0x00000003
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#define RENCODE_IB_PARAM_LAYER_CONTROL             0x00000004
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#define RENCODE_IB_PARAM_LAYER_SELECT              0x00000005
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#define RENCODE_IB_PARAM_RATE_CONTROL_SESSION_INIT 0x00000006
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#define RENCODE_IB_PARAM_RATE_CONTROL_LAYER_INIT   0x00000007
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#define RENCODE_IB_PARAM_RATE_CONTROL_PER_PICTURE  0x00000008
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#define RENCODE_IB_PARAM_QUALITY_PARAMS            0x00000009
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#define RENCODE_IB_PARAM_SLICE_HEADER              0x0000000a
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#define RENCODE_IB_PARAM_ENCODE_PARAMS             0x0000000b
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#define RENCODE_IB_PARAM_INTRA_REFRESH             0x0000000c
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#define RENCODE_IB_PARAM_ENCODE_CONTEXT_BUFFER     0x0000000d
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#define RENCODE_IB_PARAM_VIDEO_BITSTREAM_BUFFER    0x0000000e
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#define RENCODE_IB_PARAM_FEEDBACK_BUFFER           0x00000010
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#define RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU        0x00000020
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#define RENCODE_HEVC_IB_PARAM_SLICE_CONTROL        0x00100001
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#define RENCODE_HEVC_IB_PARAM_SPEC_MISC            0x00100002
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#define RENCODE_HEVC_IB_PARAM_DEBLOCKING_FILTER    0x00100003
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#define RENCODE_H264_IB_PARAM_SLICE_CONTROL        0x00200001
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#define RENCODE_H264_IB_PARAM_SPEC_MISC            0x00200002
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#define RENCODE_H264_IB_PARAM_ENCODE_PARAMS        0x00200003
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#define RENCODE_H264_IB_PARAM_DEBLOCKING_FILTER    0x00200004
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static void radeon_enc_session_info(struct radeon_encoder *enc)
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{
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   RADEON_ENC_BEGIN(enc->cmd.session_info);
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   RADEON_ENC_CS(enc->enc_pic.session_info.interface_version);
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   RADEON_ENC_READWRITE(enc->si->res->buf, enc->si->res->domains, 0x0);
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   RADEON_ENC_CS(RENCODE_ENGINE_TYPE_ENCODE);
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   RADEON_ENC_END();
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}
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static void radeon_enc_task_info(struct radeon_encoder *enc, bool need_feedback)
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{
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   enc->enc_pic.task_info.task_id++;
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   if (need_feedback)
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      enc->enc_pic.task_info.allowed_max_num_feedbacks = 1;
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   else
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      enc->enc_pic.task_info.allowed_max_num_feedbacks = 0;
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   RADEON_ENC_BEGIN(enc->cmd.task_info);
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   enc->p_task_size = &enc->cs.current.buf[enc->cs.current.cdw++];
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   RADEON_ENC_CS(enc->enc_pic.task_info.task_id);
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   RADEON_ENC_CS(enc->enc_pic.task_info.allowed_max_num_feedbacks);
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   RADEON_ENC_END();
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}
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static void radeon_enc_session_init(struct radeon_encoder *enc)
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{
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   enc->enc_pic.session_init.encode_standard = RENCODE_ENCODE_STANDARD_H264;
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   enc->enc_pic.session_init.aligned_picture_width = align(enc->base.width, 16);
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   enc->enc_pic.session_init.aligned_picture_height = align(enc->base.height, 16);
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   enc->enc_pic.session_init.padding_width =
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      enc->enc_pic.session_init.aligned_picture_width - enc->base.width;
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   enc->enc_pic.session_init.padding_height =
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      enc->enc_pic.session_init.aligned_picture_height - enc->base.height;
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   enc->enc_pic.session_init.pre_encode_mode = RENCODE_PREENCODE_MODE_NONE;
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   enc->enc_pic.session_init.pre_encode_chroma_enabled = false;
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   RADEON_ENC_BEGIN(enc->cmd.session_init);
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   RADEON_ENC_CS(enc->enc_pic.session_init.encode_standard);
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   RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_width);
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   RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_height);
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   RADEON_ENC_CS(enc->enc_pic.session_init.padding_width);
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   RADEON_ENC_CS(enc->enc_pic.session_init.padding_height);
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   RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_mode);
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   RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_chroma_enabled);
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   RADEON_ENC_END();
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}
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static void radeon_enc_session_init_hevc(struct radeon_encoder *enc)
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{
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   enc->enc_pic.session_init.encode_standard = RENCODE_ENCODE_STANDARD_HEVC;
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   enc->enc_pic.session_init.aligned_picture_width = align(enc->base.width, 64);
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   enc->enc_pic.session_init.aligned_picture_height = align(enc->base.height, 16);
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   enc->enc_pic.session_init.padding_width =
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      enc->enc_pic.session_init.aligned_picture_width - enc->base.width;
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   enc->enc_pic.session_init.padding_height =
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      enc->enc_pic.session_init.aligned_picture_height - enc->base.height;
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   enc->enc_pic.session_init.pre_encode_mode = RENCODE_PREENCODE_MODE_NONE;
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   enc->enc_pic.session_init.pre_encode_chroma_enabled = false;
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   RADEON_ENC_BEGIN(enc->cmd.session_init);
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   RADEON_ENC_CS(enc->enc_pic.session_init.encode_standard);
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   RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_width);
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   RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_height);
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   RADEON_ENC_CS(enc->enc_pic.session_init.padding_width);
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   RADEON_ENC_CS(enc->enc_pic.session_init.padding_height);
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   RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_mode);
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   RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_chroma_enabled);
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   RADEON_ENC_END();
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}
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static void radeon_enc_layer_control(struct radeon_encoder *enc)
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{
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   enc->enc_pic.layer_ctrl.max_num_temporal_layers = 1;
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   enc->enc_pic.layer_ctrl.num_temporal_layers = 1;
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   RADEON_ENC_BEGIN(enc->cmd.layer_control);
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   RADEON_ENC_CS(enc->enc_pic.layer_ctrl.max_num_temporal_layers);
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   RADEON_ENC_CS(enc->enc_pic.layer_ctrl.num_temporal_layers);
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   RADEON_ENC_END();
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}
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static void radeon_enc_layer_select(struct radeon_encoder *enc)
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{
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   enc->enc_pic.layer_sel.temporal_layer_index = 0;
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   RADEON_ENC_BEGIN(enc->cmd.layer_select);
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   RADEON_ENC_CS(enc->enc_pic.layer_sel.temporal_layer_index);
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   RADEON_ENC_END();
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}
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static void radeon_enc_slice_control(struct radeon_encoder *enc)
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{
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   enc->enc_pic.slice_ctrl.slice_control_mode = RENCODE_H264_SLICE_CONTROL_MODE_FIXED_MBS;
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   enc->enc_pic.slice_ctrl.num_mbs_per_slice =
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      align(enc->base.width, 16) / 16 * align(enc->base.height, 16) / 16;
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   RADEON_ENC_BEGIN(enc->cmd.slice_control_h264);
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   RADEON_ENC_CS(enc->enc_pic.slice_ctrl.slice_control_mode);
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   RADEON_ENC_CS(enc->enc_pic.slice_ctrl.num_mbs_per_slice);
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   RADEON_ENC_END();
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}
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static void radeon_enc_slice_control_hevc(struct radeon_encoder *enc)
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{
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   enc->enc_pic.hevc_slice_ctrl.slice_control_mode = RENCODE_HEVC_SLICE_CONTROL_MODE_FIXED_CTBS;
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   enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice =
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      align(enc->base.width, 64) / 64 * align(enc->base.height, 64) / 64;
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   enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice_segment =
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      enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice;
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   RADEON_ENC_BEGIN(enc->cmd.slice_control_hevc);
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   RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.slice_control_mode);
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   RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice);
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   RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice_segment);
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   RADEON_ENC_END();
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}
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static void radeon_enc_spec_misc(struct radeon_encoder *enc)
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{
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   enc->enc_pic.spec_misc.constrained_intra_pred_flag = 0;
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   enc->enc_pic.spec_misc.cabac_enable = 0;
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   enc->enc_pic.spec_misc.cabac_init_idc = 0;
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   enc->enc_pic.spec_misc.half_pel_enabled = 1;
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   enc->enc_pic.spec_misc.quarter_pel_enabled = 1;
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   enc->enc_pic.spec_misc.profile_idc = u_get_h264_profile_idc(enc->base.profile);
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   enc->enc_pic.spec_misc.level_idc = enc->base.level;
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   RADEON_ENC_BEGIN(enc->cmd.spec_misc_h264);
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   RADEON_ENC_CS(enc->enc_pic.spec_misc.constrained_intra_pred_flag);
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   RADEON_ENC_CS(enc->enc_pic.spec_misc.cabac_enable);
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   RADEON_ENC_CS(enc->enc_pic.spec_misc.cabac_init_idc);
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   RADEON_ENC_CS(enc->enc_pic.spec_misc.half_pel_enabled);
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   RADEON_ENC_CS(enc->enc_pic.spec_misc.quarter_pel_enabled);
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   RADEON_ENC_CS(enc->enc_pic.spec_misc.profile_idc);
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   RADEON_ENC_CS(enc->enc_pic.spec_misc.level_idc);
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   RADEON_ENC_END();
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}
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static void radeon_enc_spec_misc_hevc(struct radeon_encoder *enc)
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{
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   RADEON_ENC_BEGIN(enc->cmd.spec_misc_hevc);
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   RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3);
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   RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.amp_disabled);
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   RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled);
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   RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag);
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   RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.cabac_init_flag);
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   RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.half_pel_enabled);
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   RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.quarter_pel_enabled);
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   RADEON_ENC_END();
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}
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static void radeon_enc_rc_session_init(struct radeon_encoder *enc)
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{
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   RADEON_ENC_BEGIN(enc->cmd.rc_session_init);
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   RADEON_ENC_CS(enc->enc_pic.rc_session_init.rate_control_method);
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   RADEON_ENC_CS(enc->enc_pic.rc_session_init.vbv_buffer_level);
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   RADEON_ENC_END();
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}
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static void radeon_enc_rc_layer_init(struct radeon_encoder *enc)
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{
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   RADEON_ENC_BEGIN(enc->cmd.rc_layer_init);
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   RADEON_ENC_CS(enc->enc_pic.rc_layer_init.target_bit_rate);
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   RADEON_ENC_CS(enc->enc_pic.rc_layer_init.peak_bit_rate);
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   RADEON_ENC_CS(enc->enc_pic.rc_layer_init.frame_rate_num);
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   RADEON_ENC_CS(enc->enc_pic.rc_layer_init.frame_rate_den);
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   RADEON_ENC_CS(enc->enc_pic.rc_layer_init.vbv_buffer_size);
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   RADEON_ENC_CS(enc->enc_pic.rc_layer_init.avg_target_bits_per_picture);
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   RADEON_ENC_CS(enc->enc_pic.rc_layer_init.peak_bits_per_picture_integer);
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   RADEON_ENC_CS(enc->enc_pic.rc_layer_init.peak_bits_per_picture_fractional);
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   RADEON_ENC_END();
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}
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static void radeon_enc_deblocking_filter_h264(struct radeon_encoder *enc)
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{
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   enc->enc_pic.h264_deblock.disable_deblocking_filter_idc = 0;
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   enc->enc_pic.h264_deblock.alpha_c0_offset_div2 = 0;
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   enc->enc_pic.h264_deblock.beta_offset_div2 = 0;
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   enc->enc_pic.h264_deblock.cb_qp_offset = 0;
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   enc->enc_pic.h264_deblock.cr_qp_offset = 0;
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   RADEON_ENC_BEGIN(enc->cmd.deblocking_filter_h264);
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   RADEON_ENC_CS(enc->enc_pic.h264_deblock.disable_deblocking_filter_idc);
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   RADEON_ENC_CS(enc->enc_pic.h264_deblock.alpha_c0_offset_div2);
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   RADEON_ENC_CS(enc->enc_pic.h264_deblock.beta_offset_div2);
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   RADEON_ENC_CS(enc->enc_pic.h264_deblock.cb_qp_offset);
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   RADEON_ENC_CS(enc->enc_pic.h264_deblock.cr_qp_offset);
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   RADEON_ENC_END();
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}
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static void radeon_enc_deblocking_filter_hevc(struct radeon_encoder *enc)
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{
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   RADEON_ENC_BEGIN(enc->cmd.deblocking_filter_hevc);
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   RADEON_ENC_CS(enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled);
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   RADEON_ENC_CS(enc->enc_pic.hevc_deblock.deblocking_filter_disabled);
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   RADEON_ENC_CS(enc->enc_pic.hevc_deblock.beta_offset_div2);
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   RADEON_ENC_CS(enc->enc_pic.hevc_deblock.tc_offset_div2);
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   RADEON_ENC_CS(enc->enc_pic.hevc_deblock.cb_qp_offset);
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   RADEON_ENC_CS(enc->enc_pic.hevc_deblock.cr_qp_offset);
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   RADEON_ENC_END();
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}
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static void radeon_enc_quality_params(struct radeon_encoder *enc)
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{
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   enc->enc_pic.quality_params.vbaq_mode = 0;
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   enc->enc_pic.quality_params.scene_change_sensitivity = 0;
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   enc->enc_pic.quality_params.scene_change_min_idr_interval = 0;
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   RADEON_ENC_BEGIN(enc->cmd.quality_params);
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   RADEON_ENC_CS(enc->enc_pic.quality_params.vbaq_mode);
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   RADEON_ENC_CS(enc->enc_pic.quality_params.scene_change_sensitivity);
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   RADEON_ENC_CS(enc->enc_pic.quality_params.scene_change_min_idr_interval);
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   RADEON_ENC_END();
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}
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static void radeon_enc_nalu_sps(struct radeon_encoder *enc)
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{
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   RADEON_ENC_BEGIN(enc->cmd.nalu);
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   RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_SPS);
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   uint32_t *size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++];
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   radeon_enc_reset(enc);
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   radeon_enc_set_emulation_prevention(enc, false);
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   radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
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   radeon_enc_code_fixed_bits(enc, 0x67, 8);
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   radeon_enc_byte_align(enc);
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   radeon_enc_set_emulation_prevention(enc, true);
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   radeon_enc_code_fixed_bits(enc, enc->enc_pic.spec_misc.profile_idc, 8);
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   radeon_enc_code_fixed_bits(enc, 0x44, 8); // hardcode to constrained baseline
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   radeon_enc_code_fixed_bits(enc, enc->enc_pic.spec_misc.level_idc, 8);
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   radeon_enc_code_ue(enc, 0x0);
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   if (enc->enc_pic.spec_misc.profile_idc == 100 || enc->enc_pic.spec_misc.profile_idc == 110 ||
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       enc->enc_pic.spec_misc.profile_idc == 122 || enc->enc_pic.spec_misc.profile_idc == 244 ||
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       enc->enc_pic.spec_misc.profile_idc == 44  || enc->enc_pic.spec_misc.profile_idc == 83 ||
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       enc->enc_pic.spec_misc.profile_idc == 86  || enc->enc_pic.spec_misc.profile_idc == 118 ||
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       enc->enc_pic.spec_misc.profile_idc == 128 || enc->enc_pic.spec_misc.profile_idc == 138) {
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      radeon_enc_code_ue(enc, 0x1);
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      radeon_enc_code_ue(enc, 0x0);
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      radeon_enc_code_ue(enc, 0x0);
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      radeon_enc_code_fixed_bits(enc, 0x0, 2);
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   }
307

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   radeon_enc_code_ue(enc, 1);
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   radeon_enc_code_ue(enc, enc->enc_pic.pic_order_cnt_type);
310

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   if (enc->enc_pic.pic_order_cnt_type == 0)
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      radeon_enc_code_ue(enc, 1);
313

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   radeon_enc_code_ue(enc, (enc->base.max_references + 1));
315
   radeon_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers > 1 ? 0x1 : 0x0,
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                              1);
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   radeon_enc_code_ue(enc, (enc->enc_pic.session_init.aligned_picture_width / 16 - 1));
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   radeon_enc_code_ue(enc, (enc->enc_pic.session_init.aligned_picture_height / 16 - 1));
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   bool progressive_only = true;
320
   radeon_enc_code_fixed_bits(enc, progressive_only ? 0x1 : 0x0, 1);
321

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   if (!progressive_only)
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      radeon_enc_code_fixed_bits(enc, 0x0, 1);
324

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   radeon_enc_code_fixed_bits(enc, 0x1, 1);
326

327
   if ((enc->enc_pic.crop_left != 0) || (enc->enc_pic.crop_right  != 0) ||
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       (enc->enc_pic.crop_top  != 0) || (enc->enc_pic.crop_bottom != 0)) {
329
      radeon_enc_code_fixed_bits(enc, 0x1, 1);
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      radeon_enc_code_ue(enc, enc->enc_pic.crop_left);
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      radeon_enc_code_ue(enc, enc->enc_pic.crop_right);
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      radeon_enc_code_ue(enc, enc->enc_pic.crop_top);
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      radeon_enc_code_ue(enc, enc->enc_pic.crop_bottom);
334
   } else
335
      radeon_enc_code_fixed_bits(enc, 0x0, 1);
336

337
   radeon_enc_code_fixed_bits(enc, 0x1, 1);
338
   radeon_enc_code_fixed_bits(enc, 0x0, 1);
339
   radeon_enc_code_fixed_bits(enc, 0x0, 1);
340
   radeon_enc_code_fixed_bits(enc, 0x0, 1);
341
   radeon_enc_code_fixed_bits(enc, 0x0, 1);
342
   radeon_enc_code_fixed_bits(enc, 0x0, 1);
343
   radeon_enc_code_fixed_bits(enc, 0x0, 1);
344
   radeon_enc_code_fixed_bits(enc, 0x0, 1);
345
   radeon_enc_code_fixed_bits(enc, 0x0, 1);
346
   radeon_enc_code_fixed_bits(enc, 0x1, 1);
347
   radeon_enc_code_fixed_bits(enc, 0x1, 1);
348
   radeon_enc_code_ue(enc, 0x0);
349
   radeon_enc_code_ue(enc, 0x0);
350
   radeon_enc_code_ue(enc, 16);
351
   radeon_enc_code_ue(enc, 16);
352
   radeon_enc_code_ue(enc, 0x0);
353
   radeon_enc_code_ue(enc, (enc->base.max_references + 1));
354

355
   radeon_enc_code_fixed_bits(enc, 0x1, 1);
356

357
   radeon_enc_byte_align(enc);
358
   radeon_enc_flush_headers(enc);
359
   *size_in_bytes = (enc->bits_output + 7) / 8;
360
   RADEON_ENC_END();
361
}
362

363
static void radeon_enc_nalu_sps_hevc(struct radeon_encoder *enc)
364
{
365
   RADEON_ENC_BEGIN(enc->cmd.nalu);
366
   RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_SPS);
367
   uint32_t *size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++];
368
   int i;
369

370
   radeon_enc_reset(enc);
371
   radeon_enc_set_emulation_prevention(enc, false);
372
   radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
373
   radeon_enc_code_fixed_bits(enc, 0x4201, 16);
374
   radeon_enc_byte_align(enc);
375
   radeon_enc_set_emulation_prevention(enc, true);
376
   radeon_enc_code_fixed_bits(enc, 0x0, 4);
377
   radeon_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1, 3);
378
   radeon_enc_code_fixed_bits(enc, 0x1, 1);
379
   radeon_enc_code_fixed_bits(enc, 0x0, 2);
380
   radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_tier_flag, 1);
381
   radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_profile_idc, 5);
382
   radeon_enc_code_fixed_bits(enc, 0x60000000, 32);
383
   radeon_enc_code_fixed_bits(enc, 0xb0000000, 32);
384
   radeon_enc_code_fixed_bits(enc, 0x0, 16);
385
   radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_level_idc, 8);
386

387
   for (i = 0; i < (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i++)
388
      radeon_enc_code_fixed_bits(enc, 0x0, 2);
389

390
   if ((enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1) > 0) {
391
      for (i = (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i < 8; i++)
392
         radeon_enc_code_fixed_bits(enc, 0x0, 2);
393
   }
394

395
   radeon_enc_code_ue(enc, 0x0);
396
   radeon_enc_code_ue(enc, enc->enc_pic.chroma_format_idc);
397
   radeon_enc_code_ue(enc, enc->enc_pic.session_init.aligned_picture_width);
398
   radeon_enc_code_ue(enc, enc->enc_pic.session_init.aligned_picture_height);
399

400
   if ((enc->enc_pic.crop_left != 0) || (enc->enc_pic.crop_right  != 0) ||
401
       (enc->enc_pic.crop_top  != 0) || (enc->enc_pic.crop_bottom != 0)) {
402
      radeon_enc_code_fixed_bits(enc, 0x1, 1);
403
      radeon_enc_code_ue(enc, enc->enc_pic.crop_left);
404
      radeon_enc_code_ue(enc, enc->enc_pic.crop_right);
405
      radeon_enc_code_ue(enc, enc->enc_pic.crop_top);
406
      radeon_enc_code_ue(enc, enc->enc_pic.crop_bottom);
407
   } else if (enc->enc_pic.session_init.padding_width  != 0 ||
408
              enc->enc_pic.session_init.padding_height != 0) {
409
      radeon_enc_code_fixed_bits(enc, 0x1, 1);
410
      radeon_enc_code_ue(enc, enc->enc_pic.session_init.padding_width / 2);
411
      radeon_enc_code_ue(enc, enc->enc_pic.session_init.padding_width / 2);
412
      radeon_enc_code_ue(enc, enc->enc_pic.session_init.padding_height / 2);
413
      radeon_enc_code_ue(enc, enc->enc_pic.session_init.padding_height / 2);
414
   } else
415
      radeon_enc_code_fixed_bits(enc, 0x0, 1);
416

417
   radeon_enc_code_ue(enc, enc->enc_pic.bit_depth_luma_minus8);
418
   radeon_enc_code_ue(enc, enc->enc_pic.bit_depth_chroma_minus8);
419
   radeon_enc_code_ue(enc, enc->enc_pic.log2_max_poc - 4);
420
   radeon_enc_code_fixed_bits(enc, 0x0, 1);
421
   radeon_enc_code_ue(enc, 1);
422
   radeon_enc_code_ue(enc, 0x0);
423
   radeon_enc_code_ue(enc, 0x0);
424
   radeon_enc_code_ue(enc, enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3);
425
   // Only support CTBSize 64
426
   radeon_enc_code_ue(enc,
427
                      6 - (enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3 + 3));
428
   radeon_enc_code_ue(enc, enc->enc_pic.log2_min_transform_block_size_minus2);
429
   radeon_enc_code_ue(enc, enc->enc_pic.log2_diff_max_min_transform_block_size);
430
   radeon_enc_code_ue(enc, enc->enc_pic.max_transform_hierarchy_depth_inter);
431
   radeon_enc_code_ue(enc, enc->enc_pic.max_transform_hierarchy_depth_intra);
432

433
   radeon_enc_code_fixed_bits(enc, 0x0, 1);
434
   radeon_enc_code_fixed_bits(enc, !enc->enc_pic.hevc_spec_misc.amp_disabled, 1);
435
   radeon_enc_code_fixed_bits(enc, enc->enc_pic.sample_adaptive_offset_enabled_flag, 1);
436
   radeon_enc_code_fixed_bits(enc, enc->enc_pic.pcm_enabled_flag, 1);
437

438
   radeon_enc_code_ue(enc, 1);
439
   radeon_enc_code_ue(enc, 1);
440
   radeon_enc_code_ue(enc, 0);
441
   radeon_enc_code_ue(enc, 0);
442
   radeon_enc_code_fixed_bits(enc, 0x1, 1);
443

444
   radeon_enc_code_fixed_bits(enc, 0x0, 1);
445

446
   radeon_enc_code_fixed_bits(enc, 0, 1);
447
   radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled, 1);
448

449
   radeon_enc_code_fixed_bits(enc, 0x0, 1);
450

451
   radeon_enc_code_fixed_bits(enc, 0x0, 1);
452

453
   radeon_enc_code_fixed_bits(enc, 0x1, 1);
454

455
   radeon_enc_byte_align(enc);
456
   radeon_enc_flush_headers(enc);
457
   *size_in_bytes = (enc->bits_output + 7) / 8;
458
   RADEON_ENC_END();
459
}
460

461
static void radeon_enc_nalu_pps(struct radeon_encoder *enc)
462
{
463
   RADEON_ENC_BEGIN(enc->cmd.nalu);
464
   RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_PPS);
465
   uint32_t *size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++];
466
   radeon_enc_reset(enc);
467
   radeon_enc_set_emulation_prevention(enc, false);
468
   radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
469
   radeon_enc_code_fixed_bits(enc, 0x68, 8);
470
   radeon_enc_byte_align(enc);
471
   radeon_enc_set_emulation_prevention(enc, true);
472
   radeon_enc_code_ue(enc, 0x0);
473
   radeon_enc_code_ue(enc, 0x0);
474
   radeon_enc_code_fixed_bits(enc, (enc->enc_pic.spec_misc.cabac_enable ? 0x1 : 0x0), 1);
475
   radeon_enc_code_fixed_bits(enc, 0x0, 1);
476
   radeon_enc_code_ue(enc, 0x0);
477
   radeon_enc_code_ue(enc, 0x0);
478
   radeon_enc_code_ue(enc, 0x0);
479
   radeon_enc_code_fixed_bits(enc, 0x0, 1);
480
   radeon_enc_code_fixed_bits(enc, 0x0, 2);
481
   radeon_enc_code_se(enc, 0x0);
482
   radeon_enc_code_se(enc, 0x0);
483
   radeon_enc_code_se(enc, 0x0);
484
   radeon_enc_code_fixed_bits(enc, 0x1, 1);
485
   radeon_enc_code_fixed_bits(enc, 0x0, 1);
486
   radeon_enc_code_fixed_bits(enc, 0x0, 1);
487

488
   radeon_enc_code_fixed_bits(enc, 0x1, 1);
489

490
   radeon_enc_byte_align(enc);
491
   radeon_enc_flush_headers(enc);
492
   *size_in_bytes = (enc->bits_output + 7) / 8;
493
   RADEON_ENC_END();
494
}
495

496
static void radeon_enc_nalu_pps_hevc(struct radeon_encoder *enc)
497
{
498
   RADEON_ENC_BEGIN(enc->cmd.nalu);
499
   RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_PPS);
500
   uint32_t *size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++];
501
   radeon_enc_reset(enc);
502
   radeon_enc_set_emulation_prevention(enc, false);
503
   radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
504
   radeon_enc_code_fixed_bits(enc, 0x4401, 16);
505
   radeon_enc_byte_align(enc);
506
   radeon_enc_set_emulation_prevention(enc, true);
507
   radeon_enc_code_ue(enc, 0x0);
508
   radeon_enc_code_ue(enc, 0x0);
509
   radeon_enc_code_fixed_bits(enc, 0x1, 1);
510
   radeon_enc_code_fixed_bits(enc, 0x0, 4);
511
   radeon_enc_code_fixed_bits(enc, 0x0, 1);
512
   radeon_enc_code_fixed_bits(enc, 0x1, 1);
513
   radeon_enc_code_ue(enc, 0x0);
514
   radeon_enc_code_ue(enc, 0x0);
515
   radeon_enc_code_se(enc, 0x0);
516
   radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag, 1);
517
   radeon_enc_code_fixed_bits(enc, 0x0, 1);
518
   if (enc->enc_pic.rc_session_init.rate_control_method == RENCODE_RATE_CONTROL_METHOD_NONE)
519
      radeon_enc_code_fixed_bits(enc, 0x0, 1);
520
   else {
521
      radeon_enc_code_fixed_bits(enc, 0x1, 1);
522
      radeon_enc_code_ue(enc, 0x0);
523
   }
524
   radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cb_qp_offset);
525
   radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cr_qp_offset);
526
   radeon_enc_code_fixed_bits(enc, 0x0, 1);
527
   radeon_enc_code_fixed_bits(enc, 0x0, 2);
528
   radeon_enc_code_fixed_bits(enc, 0x0, 1);
529
   radeon_enc_code_fixed_bits(enc, 0x0, 1);
530
   radeon_enc_code_fixed_bits(enc, 0x0, 1);
531
   radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled, 1);
532
   radeon_enc_code_fixed_bits(enc, 0x1, 1);
533
   radeon_enc_code_fixed_bits(enc, 0x0, 1);
534
   radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.deblocking_filter_disabled, 1);
535

536
   if (!enc->enc_pic.hevc_deblock.deblocking_filter_disabled) {
537
      radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.beta_offset_div2);
538
      radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.tc_offset_div2);
539
   }
540

541
   radeon_enc_code_fixed_bits(enc, 0x0, 1);
542
   radeon_enc_code_fixed_bits(enc, 0x0, 1);
543
   radeon_enc_code_ue(enc, enc->enc_pic.log2_parallel_merge_level_minus2);
544
   radeon_enc_code_fixed_bits(enc, 0x0, 2);
545

546
   radeon_enc_code_fixed_bits(enc, 0x1, 1);
547

548
   radeon_enc_byte_align(enc);
549
   radeon_enc_flush_headers(enc);
550
   *size_in_bytes = (enc->bits_output + 7) / 8;
551
   RADEON_ENC_END();
552
}
553

554
static void radeon_enc_nalu_vps(struct radeon_encoder *enc)
555
{
556
   RADEON_ENC_BEGIN(enc->cmd.nalu);
557
   RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_VPS);
558
   uint32_t *size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++];
559
   int i;
560

561
   radeon_enc_reset(enc);
562
   radeon_enc_set_emulation_prevention(enc, false);
563
   radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
564
   radeon_enc_code_fixed_bits(enc, 0x4001, 16);
565
   radeon_enc_byte_align(enc);
566
   radeon_enc_set_emulation_prevention(enc, true);
567

568
   radeon_enc_code_fixed_bits(enc, 0x0, 4);
569
   radeon_enc_code_fixed_bits(enc, 0x3, 2);
570
   radeon_enc_code_fixed_bits(enc, 0x0, 6);
571
   radeon_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1, 3);
572
   radeon_enc_code_fixed_bits(enc, 0x1, 1);
573
   radeon_enc_code_fixed_bits(enc, 0xffff, 16);
574
   radeon_enc_code_fixed_bits(enc, 0x0, 2);
575
   radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_tier_flag, 1);
576
   radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_profile_idc, 5);
577
   radeon_enc_code_fixed_bits(enc, 0x60000000, 32);
578
   radeon_enc_code_fixed_bits(enc, 0xb0000000, 32);
579
   radeon_enc_code_fixed_bits(enc, 0x0, 16);
580
   radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_level_idc, 8);
581

582
   for (i = 0; i < (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i++)
583
      radeon_enc_code_fixed_bits(enc, 0x0, 2);
584

585
   if ((enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1) > 0) {
586
      for (i = (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i < 8; i++)
587
         radeon_enc_code_fixed_bits(enc, 0x0, 2);
588
   }
589

590
   radeon_enc_code_fixed_bits(enc, 0x0, 1);
591
   radeon_enc_code_ue(enc, 0x1);
592
   radeon_enc_code_ue(enc, 0x0);
593
   radeon_enc_code_ue(enc, 0x0);
594

595
   radeon_enc_code_fixed_bits(enc, 0x0, 6);
596
   radeon_enc_code_ue(enc, 0x0);
597
   radeon_enc_code_fixed_bits(enc, 0x0, 1);
598
   radeon_enc_code_fixed_bits(enc, 0x0, 1);
599

600
   radeon_enc_code_fixed_bits(enc, 0x1, 1);
601

602
   radeon_enc_byte_align(enc);
603
   radeon_enc_flush_headers(enc);
604
   *size_in_bytes = (enc->bits_output + 7) / 8;
605
   RADEON_ENC_END();
606
}
607

608
static void radeon_enc_nalu_aud_hevc(struct radeon_encoder *enc)
609
{
610
   RADEON_ENC_BEGIN(enc->cmd.nalu);
611
   RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_AUD);
612
   uint32_t *size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++];
613
   radeon_enc_reset(enc);
614
   radeon_enc_set_emulation_prevention(enc, false);
615
   radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
616
   radeon_enc_code_fixed_bits(enc, 0x0, 1);
617
   radeon_enc_code_fixed_bits(enc, 35, 6);
618
   radeon_enc_code_fixed_bits(enc, 0x0, 6);
619
   radeon_enc_code_fixed_bits(enc, 0x1, 3);
620
   radeon_enc_byte_align(enc);
621
   radeon_enc_set_emulation_prevention(enc, true);
622
   switch (enc->enc_pic.picture_type) {
623
   case PIPE_H2645_ENC_PICTURE_TYPE_I:
624
   case PIPE_H2645_ENC_PICTURE_TYPE_IDR:
625
      radeon_enc_code_fixed_bits(enc, 0x00, 3);
626
      break;
627
   case PIPE_H2645_ENC_PICTURE_TYPE_P:
628
      radeon_enc_code_fixed_bits(enc, 0x01, 3);
629
      break;
630
   case PIPE_H2645_ENC_PICTURE_TYPE_B:
631
      radeon_enc_code_fixed_bits(enc, 0x02, 3);
632
      break;
633
   default:
634
      radeon_enc_code_fixed_bits(enc, 0x02, 3);
635
   }
636

637
   radeon_enc_code_fixed_bits(enc, 0x1, 1);
638

639
   radeon_enc_byte_align(enc);
640
   radeon_enc_flush_headers(enc);
641
   *size_in_bytes = (enc->bits_output + 7) / 8;
642
   RADEON_ENC_END();
643
}
644

645
static void radeon_enc_slice_header(struct radeon_encoder *enc)
646
{
647
   uint32_t instruction[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
648
   uint32_t num_bits[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
649
   unsigned int inst_index = 0;
650
   unsigned int cdw_start = 0;
651
   unsigned int cdw_filled = 0;
652
   unsigned int bits_copied = 0;
653
   RADEON_ENC_BEGIN(enc->cmd.slice_header);
654
   radeon_enc_reset(enc);
655
   radeon_enc_set_emulation_prevention(enc, false);
656

657
   cdw_start = enc->cs.current.cdw;
658
   if (enc->enc_pic.is_idr)
659
      radeon_enc_code_fixed_bits(enc, 0x65, 8);
660
   else if (enc->enc_pic.not_referenced)
661
      radeon_enc_code_fixed_bits(enc, 0x01, 8);
662
   else
663
      radeon_enc_code_fixed_bits(enc, 0x41, 8);
664

665
   radeon_enc_flush_headers(enc);
666
   instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
667
   num_bits[inst_index] = enc->bits_output - bits_copied;
668
   bits_copied = enc->bits_output;
669
   inst_index++;
670

671
   instruction[inst_index] = RENCODE_H264_HEADER_INSTRUCTION_FIRST_MB;
672
   inst_index++;
673

674
   switch (enc->enc_pic.picture_type) {
675
   case PIPE_H2645_ENC_PICTURE_TYPE_I:
676
   case PIPE_H2645_ENC_PICTURE_TYPE_IDR:
677
      radeon_enc_code_fixed_bits(enc, 0x08, 7);
678
      break;
679
   case PIPE_H2645_ENC_PICTURE_TYPE_P:
680
   case PIPE_H2645_ENC_PICTURE_TYPE_SKIP:
681
      radeon_enc_code_fixed_bits(enc, 0x06, 5);
682
      break;
683
   case PIPE_H2645_ENC_PICTURE_TYPE_B:
684
      radeon_enc_code_fixed_bits(enc, 0x07, 5);
685
      break;
686
   default:
687
      radeon_enc_code_fixed_bits(enc, 0x08, 7);
688
   }
689

690
   radeon_enc_code_ue(enc, 0x0);
691
   radeon_enc_code_fixed_bits(enc, enc->enc_pic.frame_num % 32, 5);
692

693
   if (enc->enc_pic.h264_enc_params.input_picture_structure !=
694
       RENCODE_H264_PICTURE_STRUCTURE_FRAME) {
695
      radeon_enc_code_fixed_bits(enc, 0x1, 1);
696
      radeon_enc_code_fixed_bits(enc,
697
                                 enc->enc_pic.h264_enc_params.input_picture_structure ==
698
                                       RENCODE_H264_PICTURE_STRUCTURE_BOTTOM_FIELD
699
                                    ? 1
700
                                    : 0,
701
                                 1);
702
   }
703

704
   if (enc->enc_pic.is_idr)
705
      radeon_enc_code_ue(enc, enc->enc_pic.is_even_frame);
706

707
   enc->enc_pic.is_even_frame = !enc->enc_pic.is_even_frame;
708

709
   if (enc->enc_pic.pic_order_cnt_type == 0)
710
      radeon_enc_code_fixed_bits(enc, enc->enc_pic.pic_order_cnt % 32, 5);
711

712
   if (enc->enc_pic.picture_type != PIPE_H2645_ENC_PICTURE_TYPE_IDR) {
713
      radeon_enc_code_fixed_bits(enc, 0x0, 1);
714

715
      if (enc->enc_pic.frame_num - enc->enc_pic.ref_idx_l0 > 1) {
716
         radeon_enc_code_fixed_bits(enc, 0x1, 1);
717
         radeon_enc_code_ue(enc, 0x0);
718
         radeon_enc_code_ue(enc, (enc->enc_pic.frame_num - enc->enc_pic.ref_idx_l0 - 1));
719
         radeon_enc_code_ue(enc, 0x3);
720
      } else
721
         radeon_enc_code_fixed_bits(enc, 0x0, 1);
722
   }
723

724
   if (enc->enc_pic.is_idr) {
725
      radeon_enc_code_fixed_bits(enc, 0x0, 1);
726
      radeon_enc_code_fixed_bits(enc, 0x0, 1);
727
   } else
728
      radeon_enc_code_fixed_bits(enc, 0x0, 1);
729

730
   if ((enc->enc_pic.picture_type != PIPE_H2645_ENC_PICTURE_TYPE_IDR) &&
731
       (enc->enc_pic.spec_misc.cabac_enable))
732
      radeon_enc_code_ue(enc, enc->enc_pic.spec_misc.cabac_init_idc);
733

734
   radeon_enc_flush_headers(enc);
735
   instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
736
   num_bits[inst_index] = enc->bits_output - bits_copied;
737
   bits_copied = enc->bits_output;
738
   inst_index++;
739

740
   instruction[inst_index] = RENCODE_H264_HEADER_INSTRUCTION_SLICE_QP_DELTA;
741
   inst_index++;
742

743
   radeon_enc_code_ue(enc, enc->enc_pic.h264_deblock.disable_deblocking_filter_idc ? 1 : 0);
744

745
   if (!enc->enc_pic.h264_deblock.disable_deblocking_filter_idc) {
746
      radeon_enc_code_se(enc, enc->enc_pic.h264_deblock.alpha_c0_offset_div2);
747
      radeon_enc_code_se(enc, enc->enc_pic.h264_deblock.beta_offset_div2);
748
   }
749

750
   radeon_enc_flush_headers(enc);
751
   instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
752
   num_bits[inst_index] = enc->bits_output - bits_copied;
753
   bits_copied = enc->bits_output;
754
   inst_index++;
755

756
   instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_END;
757

758
   cdw_filled = enc->cs.current.cdw - cdw_start;
759
   for (int i = 0; i < RENCODE_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS - cdw_filled; i++)
760
      RADEON_ENC_CS(0x00000000);
761

762
   for (int j = 0; j < RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS; j++) {
763
      RADEON_ENC_CS(instruction[j]);
764
      RADEON_ENC_CS(num_bits[j]);
765
   }
766

767
   RADEON_ENC_END();
768
}
769

770
static void radeon_enc_slice_header_hevc(struct radeon_encoder *enc)
771
{
772
   uint32_t instruction[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
773
   uint32_t num_bits[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
774
   unsigned int inst_index = 0;
775
   unsigned int cdw_start = 0;
776
   unsigned int cdw_filled = 0;
777
   unsigned int bits_copied = 0;
778
   RADEON_ENC_BEGIN(enc->cmd.slice_header);
779
   radeon_enc_reset(enc);
780
   radeon_enc_set_emulation_prevention(enc, false);
781

782
   cdw_start = enc->cs.current.cdw;
783
   radeon_enc_code_fixed_bits(enc, 0x0, 1);
784
   radeon_enc_code_fixed_bits(enc, enc->enc_pic.nal_unit_type, 6);
785
   radeon_enc_code_fixed_bits(enc, 0x0, 6);
786
   radeon_enc_code_fixed_bits(enc, 0x1, 3);
787

788
   radeon_enc_flush_headers(enc);
789
   instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
790
   num_bits[inst_index] = enc->bits_output - bits_copied;
791
   bits_copied = enc->bits_output;
792
   inst_index++;
793

794
   instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_FIRST_SLICE;
795
   inst_index++;
796

797
   if ((enc->enc_pic.nal_unit_type >= 16) && (enc->enc_pic.nal_unit_type <= 23))
798
      radeon_enc_code_fixed_bits(enc, 0x0, 1);
799

800
   radeon_enc_code_ue(enc, 0x0);
801

802
   radeon_enc_flush_headers(enc);
803
   instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
804
   num_bits[inst_index] = enc->bits_output - bits_copied;
805
   bits_copied = enc->bits_output;
806
   inst_index++;
807

808
   instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_SLICE_SEGMENT;
809
   inst_index++;
810

811
   instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_DEPENDENT_SLICE_END;
812
   inst_index++;
813

814
   switch (enc->enc_pic.picture_type) {
815
   case PIPE_H2645_ENC_PICTURE_TYPE_I:
816
   case PIPE_H2645_ENC_PICTURE_TYPE_IDR:
817
      radeon_enc_code_ue(enc, 0x2);
818
      break;
819
   case PIPE_H2645_ENC_PICTURE_TYPE_P:
820
   case PIPE_H2645_ENC_PICTURE_TYPE_SKIP:
821
      radeon_enc_code_ue(enc, 0x1);
822
      break;
823
   case PIPE_H2645_ENC_PICTURE_TYPE_B:
824
      radeon_enc_code_ue(enc, 0x0);
825
      break;
826
   default:
827
      radeon_enc_code_ue(enc, 0x1);
828
   }
829

830
   if ((enc->enc_pic.nal_unit_type != 19) && (enc->enc_pic.nal_unit_type != 20)) {
831
      radeon_enc_code_fixed_bits(enc, enc->enc_pic.pic_order_cnt, enc->enc_pic.log2_max_poc);
832
      if (enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_P)
833
         radeon_enc_code_fixed_bits(enc, 0x1, 1);
834
      else {
835
         radeon_enc_code_fixed_bits(enc, 0x0, 1);
836
         radeon_enc_code_fixed_bits(enc, 0x0, 1);
837
         radeon_enc_code_ue(enc, 0x0);
838
         radeon_enc_code_ue(enc, 0x0);
839
      }
840
   }
841

842
   if ((enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_P) ||
843
       (enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_B)) {
844
      radeon_enc_code_fixed_bits(enc, 0x0, 1);
845
      radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.cabac_init_flag, 1);
846
      radeon_enc_code_ue(enc, 5 - enc->enc_pic.max_num_merge_cand);
847
   }
848

849
   radeon_enc_flush_headers(enc);
850
   instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
851
   num_bits[inst_index] = enc->bits_output - bits_copied;
852
   bits_copied = enc->bits_output;
853
   inst_index++;
854

855
   instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_SLICE_QP_DELTA;
856
   inst_index++;
857

858
   if ((enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled) &&
859
       (!enc->enc_pic.hevc_deblock.deblocking_filter_disabled)) {
860
      radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled,
861
                                 1);
862

863
      radeon_enc_flush_headers(enc);
864
      instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
865
      num_bits[inst_index] = enc->bits_output - bits_copied;
866
      bits_copied = enc->bits_output;
867
      inst_index++;
868
   }
869

870
   instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_END;
871

872
   cdw_filled = enc->cs.current.cdw - cdw_start;
873
   for (int i = 0; i < RENCODE_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS - cdw_filled; i++)
874
      RADEON_ENC_CS(0x00000000);
875

876
   for (int j = 0; j < RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS; j++) {
877
      RADEON_ENC_CS(instruction[j]);
878
      RADEON_ENC_CS(num_bits[j]);
879
   }
880

881
   RADEON_ENC_END();
882
}
883

884
static void radeon_enc_ctx(struct radeon_encoder *enc)
885
{
886
   enc->enc_pic.ctx_buf.swizzle_mode = 0;
887
   enc->enc_pic.ctx_buf.rec_luma_pitch = align(enc->base.width, enc->alignment);
888
   enc->enc_pic.ctx_buf.rec_chroma_pitch = align(enc->base.width, enc->alignment);
889
   enc->enc_pic.ctx_buf.num_reconstructed_pictures = 2;
890

891
   RADEON_ENC_BEGIN(enc->cmd.ctx);
892
   RADEON_ENC_READWRITE(enc->cpb.res->buf, enc->cpb.res->domains, 0);
893
   RADEON_ENC_CS(enc->enc_pic.ctx_buf.swizzle_mode);
894
   RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_luma_pitch);
895
   RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_chroma_pitch);
896
   RADEON_ENC_CS(enc->enc_pic.ctx_buf.num_reconstructed_pictures);
897
   /* reconstructed_picture_1_luma_offset */
898
   RADEON_ENC_CS(0x00000000);
899
   /* reconstructed_picture_1_chroma_offset */
900
   RADEON_ENC_CS(align(enc->base.width, enc->alignment) * align(enc->base.height, 16));
901
   /* reconstructed_picture_2_luma_offset */
902
   RADEON_ENC_CS(align(enc->base.width, enc->alignment) * align(enc->base.height, 16) * 3 / 2);
903
   /* reconstructed_picture_2_chroma_offset */
904
   RADEON_ENC_CS(align(enc->base.width, enc->alignment) * align(enc->base.height, 16) * 5 / 2);
905

906
   for (int i = 0; i < 136; i++)
907
      RADEON_ENC_CS(0x00000000);
908

909
   RADEON_ENC_END();
910
}
911

912
static void radeon_enc_bitstream(struct radeon_encoder *enc)
913
{
914
   enc->enc_pic.bit_buf.mode = RENCODE_REC_SWIZZLE_MODE_LINEAR;
915
   enc->enc_pic.bit_buf.video_bitstream_buffer_size = enc->bs_size;
916
   enc->enc_pic.bit_buf.video_bitstream_data_offset = 0;
917

918
   RADEON_ENC_BEGIN(enc->cmd.bitstream);
919
   RADEON_ENC_CS(enc->enc_pic.bit_buf.mode);
920
   RADEON_ENC_WRITE(enc->bs_handle, RADEON_DOMAIN_GTT, 0);
921
   RADEON_ENC_CS(enc->enc_pic.bit_buf.video_bitstream_buffer_size);
922
   RADEON_ENC_CS(enc->enc_pic.bit_buf.video_bitstream_data_offset);
923
   RADEON_ENC_END();
924
}
925

926
static void radeon_enc_feedback(struct radeon_encoder *enc)
927
{
928
   enc->enc_pic.fb_buf.mode = RENCODE_FEEDBACK_BUFFER_MODE_LINEAR;
929
   enc->enc_pic.fb_buf.feedback_buffer_size = 16;
930
   enc->enc_pic.fb_buf.feedback_data_size = 40;
931

932
   RADEON_ENC_BEGIN(enc->cmd.feedback);
933
   RADEON_ENC_CS(enc->enc_pic.fb_buf.mode);
934
   RADEON_ENC_WRITE(enc->fb->res->buf, enc->fb->res->domains, 0x0);
935
   RADEON_ENC_CS(enc->enc_pic.fb_buf.feedback_buffer_size);
936
   RADEON_ENC_CS(enc->enc_pic.fb_buf.feedback_data_size);
937
   RADEON_ENC_END();
938
}
939

940
static void radeon_enc_intra_refresh(struct radeon_encoder *enc)
941
{
942
   enc->enc_pic.intra_ref.intra_refresh_mode = RENCODE_INTRA_REFRESH_MODE_NONE;
943
   enc->enc_pic.intra_ref.offset = 0;
944
   enc->enc_pic.intra_ref.region_size = 0;
945

946
   RADEON_ENC_BEGIN(enc->cmd.intra_refresh);
947
   RADEON_ENC_CS(enc->enc_pic.intra_ref.intra_refresh_mode);
948
   RADEON_ENC_CS(enc->enc_pic.intra_ref.offset);
949
   RADEON_ENC_CS(enc->enc_pic.intra_ref.region_size);
950
   RADEON_ENC_END();
951
}
952

953
static void radeon_enc_rc_per_pic(struct radeon_encoder *enc)
954
{
955
   RADEON_ENC_BEGIN(enc->cmd.rc_per_pic);
956
   RADEON_ENC_CS(enc->enc_pic.rc_per_pic.qp);
957
   RADEON_ENC_CS(enc->enc_pic.rc_per_pic.min_qp_app);
958
   RADEON_ENC_CS(enc->enc_pic.rc_per_pic.max_qp_app);
959
   RADEON_ENC_CS(enc->enc_pic.rc_per_pic.max_au_size);
960
   RADEON_ENC_CS(enc->enc_pic.rc_per_pic.enabled_filler_data);
961
   RADEON_ENC_CS(enc->enc_pic.rc_per_pic.skip_frame_enable);
962
   RADEON_ENC_CS(enc->enc_pic.rc_per_pic.enforce_hrd);
963
   RADEON_ENC_END();
964
}
965

966
static void radeon_enc_encode_params(struct radeon_encoder *enc)
967
{
968
   switch (enc->enc_pic.picture_type) {
969
   case PIPE_H2645_ENC_PICTURE_TYPE_I:
970
   case PIPE_H2645_ENC_PICTURE_TYPE_IDR:
971
      enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I;
972
      break;
973
   case PIPE_H2645_ENC_PICTURE_TYPE_P:
974
      enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_P;
975
      break;
976
   case PIPE_H2645_ENC_PICTURE_TYPE_SKIP:
977
      enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_P_SKIP;
978
      break;
979
   case PIPE_H2645_ENC_PICTURE_TYPE_B:
980
      enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_B;
981
      break;
982
   default:
983
      enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I;
984
   }
985

986
   if (enc->luma->meta_offset) {
987
      RVID_ERR("DCC surfaces not supported.\n");
988
      return;
989
   }
990

991
   enc->enc_pic.enc_params.allowed_max_bitstream_size = enc->bs_size;
992
   enc->enc_pic.enc_params.input_pic_luma_pitch = enc->luma->u.gfx9.surf_pitch;
993
   enc->enc_pic.enc_params.input_pic_chroma_pitch = enc->chroma->u.gfx9.surf_pitch;
994
   enc->enc_pic.enc_params.input_pic_swizzle_mode = enc->luma->u.gfx9.swizzle_mode;
995

996
   if (enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_IDR)
997
      enc->enc_pic.enc_params.reference_picture_index = 0xFFFFFFFF;
998
   else
999
      enc->enc_pic.enc_params.reference_picture_index = (enc->enc_pic.frame_num - 1) % 2;
1000

1001
   enc->enc_pic.enc_params.reconstructed_picture_index = enc->enc_pic.frame_num % 2;
1002

1003
   RADEON_ENC_BEGIN(enc->cmd.enc_params);
1004
   RADEON_ENC_CS(enc->enc_pic.enc_params.pic_type);
1005
   RADEON_ENC_CS(enc->enc_pic.enc_params.allowed_max_bitstream_size);
1006
   RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->luma->u.gfx9.surf_offset);
1007
   RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->chroma->u.gfx9.surf_offset);
1008
   RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_luma_pitch);
1009
   RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_chroma_pitch);
1010
   RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_swizzle_mode);
1011
   RADEON_ENC_CS(enc->enc_pic.enc_params.reference_picture_index);
1012
   RADEON_ENC_CS(enc->enc_pic.enc_params.reconstructed_picture_index);
1013
   RADEON_ENC_END();
1014
}
1015

1016
static void radeon_enc_encode_params_hevc(struct radeon_encoder *enc)
1017
{
1018
   switch (enc->enc_pic.picture_type) {
1019
   case PIPE_H2645_ENC_PICTURE_TYPE_I:
1020
   case PIPE_H2645_ENC_PICTURE_TYPE_IDR:
1021
      enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I;
1022
      break;
1023
   case PIPE_H2645_ENC_PICTURE_TYPE_P:
1024
      enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_P;
1025
      break;
1026
   case PIPE_H2645_ENC_PICTURE_TYPE_SKIP:
1027
      enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_P_SKIP;
1028
      break;
1029
   case PIPE_H2645_ENC_PICTURE_TYPE_B:
1030
      enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_B;
1031
      break;
1032
   default:
1033
      enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I;
1034
   }
1035

1036
   if (enc->luma->meta_offset) {
1037
      RVID_ERR("DCC surfaces not supported.\n");
1038
      return;
1039
   }
1040

1041
   enc->enc_pic.enc_params.allowed_max_bitstream_size = enc->bs_size;
1042
   enc->enc_pic.enc_params.input_pic_luma_pitch = enc->luma->u.gfx9.surf_pitch;
1043
   enc->enc_pic.enc_params.input_pic_chroma_pitch = enc->chroma->u.gfx9.surf_pitch;
1044
   enc->enc_pic.enc_params.input_pic_swizzle_mode = enc->luma->u.gfx9.swizzle_mode;
1045

1046
   if (enc->enc_pic.enc_params.pic_type == RENCODE_PICTURE_TYPE_I)
1047
      enc->enc_pic.enc_params.reference_picture_index = 0xFFFFFFFF;
1048
   else
1049
      enc->enc_pic.enc_params.reference_picture_index = (enc->enc_pic.frame_num - 1) % 2;
1050

1051
   enc->enc_pic.enc_params.reconstructed_picture_index = enc->enc_pic.frame_num % 2;
1052

1053
   RADEON_ENC_BEGIN(enc->cmd.enc_params);
1054
   RADEON_ENC_CS(enc->enc_pic.enc_params.pic_type);
1055
   RADEON_ENC_CS(enc->enc_pic.enc_params.allowed_max_bitstream_size);
1056
   RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->luma->u.gfx9.surf_offset);
1057
   RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->chroma->u.gfx9.surf_offset);
1058
   RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_luma_pitch);
1059
   RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_chroma_pitch);
1060
   RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_swizzle_mode);
1061
   RADEON_ENC_CS(enc->enc_pic.enc_params.reference_picture_index);
1062
   RADEON_ENC_CS(enc->enc_pic.enc_params.reconstructed_picture_index);
1063
   RADEON_ENC_END();
1064
}
1065

1066
static void radeon_enc_encode_params_h264(struct radeon_encoder *enc)
1067
{
1068
   enc->enc_pic.h264_enc_params.input_picture_structure = RENCODE_H264_PICTURE_STRUCTURE_FRAME;
1069
   enc->enc_pic.h264_enc_params.interlaced_mode = RENCODE_H264_INTERLACING_MODE_PROGRESSIVE;
1070
   enc->enc_pic.h264_enc_params.reference_picture_structure = RENCODE_H264_PICTURE_STRUCTURE_FRAME;
1071
   enc->enc_pic.h264_enc_params.reference_picture1_index = 0xFFFFFFFF;
1072

1073
   RADEON_ENC_BEGIN(enc->cmd.enc_params_h264);
1074
   RADEON_ENC_CS(enc->enc_pic.h264_enc_params.input_picture_structure);
1075
   RADEON_ENC_CS(enc->enc_pic.h264_enc_params.interlaced_mode);
1076
   RADEON_ENC_CS(enc->enc_pic.h264_enc_params.reference_picture_structure);
1077
   RADEON_ENC_CS(enc->enc_pic.h264_enc_params.reference_picture1_index);
1078
   RADEON_ENC_END();
1079
}
1080

1081
static void radeon_enc_op_init(struct radeon_encoder *enc)
1082
{
1083
   RADEON_ENC_BEGIN(RENCODE_IB_OP_INITIALIZE);
1084
   RADEON_ENC_END();
1085
}
1086

1087
static void radeon_enc_op_close(struct radeon_encoder *enc)
1088
{
1089
   RADEON_ENC_BEGIN(RENCODE_IB_OP_CLOSE_SESSION);
1090
   RADEON_ENC_END();
1091
}
1092

1093
static void radeon_enc_op_enc(struct radeon_encoder *enc)
1094
{
1095
   RADEON_ENC_BEGIN(RENCODE_IB_OP_ENCODE);
1096
   RADEON_ENC_END();
1097
}
1098

1099
static void radeon_enc_op_init_rc(struct radeon_encoder *enc)
1100
{
1101
   RADEON_ENC_BEGIN(RENCODE_IB_OP_INIT_RC);
1102
   RADEON_ENC_END();
1103
}
1104

1105
static void radeon_enc_op_init_rc_vbv(struct radeon_encoder *enc)
1106
{
1107
   RADEON_ENC_BEGIN(RENCODE_IB_OP_INIT_RC_VBV_BUFFER_LEVEL);
1108
   RADEON_ENC_END();
1109
}
1110

1111
static void radeon_enc_op_speed(struct radeon_encoder *enc)
1112
{
1113
   RADEON_ENC_BEGIN(RENCODE_IB_OP_SET_SPEED_ENCODING_MODE);
1114
   RADEON_ENC_END();
1115
}
1116

1117
static void begin(struct radeon_encoder *enc)
1118
{
1119
   enc->session_info(enc);
1120
   enc->total_task_size = 0;
1121
   enc->task_info(enc, enc->need_feedback);
1122
   enc->op_init(enc);
1123

1124
   enc->session_init(enc);
1125
   enc->slice_control(enc);
1126
   enc->spec_misc(enc);
1127
   enc->deblocking_filter(enc);
1128

1129
   enc->layer_control(enc);
1130
   enc->rc_session_init(enc);
1131
   enc->quality_params(enc);
1132
   enc->layer_select(enc);
1133
   enc->rc_layer_init(enc);
1134
   enc->layer_select(enc);
1135
   enc->rc_per_pic(enc);
1136
   enc->op_init_rc(enc);
1137
   enc->op_init_rc_vbv(enc);
1138
   *enc->p_task_size = (enc->total_task_size);
1139
}
1140

1141
static void radeon_enc_headers_h264(struct radeon_encoder *enc)
1142
{
1143
   if (enc->enc_pic.is_idr) {
1144
      enc->nalu_sps(enc);
1145
      enc->nalu_pps(enc);
1146
   }
1147
   enc->slice_header(enc);
1148
   enc->encode_params(enc);
1149
   enc->encode_params_codec_spec(enc);
1150
}
1151

1152
static void radeon_enc_headers_hevc(struct radeon_encoder *enc)
1153
{
1154
   enc->nalu_aud(enc);
1155
   if (enc->enc_pic.is_idr) {
1156
      enc->nalu_vps(enc);
1157
      enc->nalu_pps(enc);
1158
      enc->nalu_sps(enc);
1159
   }
1160
   enc->slice_header(enc);
1161
   enc->encode_params(enc);
1162
}
1163

1164
static void encode(struct radeon_encoder *enc)
1165
{
1166
   enc->session_info(enc);
1167
   enc->total_task_size = 0;
1168
   enc->task_info(enc, enc->need_feedback);
1169

1170
   enc->encode_headers(enc);
1171
   enc->ctx(enc);
1172
   enc->bitstream(enc);
1173
   enc->feedback(enc);
1174
   enc->intra_refresh(enc);
1175

1176
   enc->op_preset(enc);
1177
   enc->op_enc(enc);
1178
   *enc->p_task_size = (enc->total_task_size);
1179
}
1180

1181
static void destroy(struct radeon_encoder *enc)
1182
{
1183
   enc->session_info(enc);
1184
   enc->total_task_size = 0;
1185
   enc->task_info(enc, enc->need_feedback);
1186
   enc->op_close(enc);
1187
   *enc->p_task_size = (enc->total_task_size);
1188
}
1189

1190
void radeon_enc_1_2_init(struct radeon_encoder *enc)
1191
{
1192
   enc->begin = begin;
1193
   enc->encode = encode;
1194
   enc->destroy = destroy;
1195
   enc->session_info = radeon_enc_session_info;
1196
   enc->task_info = radeon_enc_task_info;
1197
   enc->layer_control = radeon_enc_layer_control;
1198
   enc->layer_select = radeon_enc_layer_select;
1199
   enc->rc_session_init = radeon_enc_rc_session_init;
1200
   enc->rc_layer_init = radeon_enc_rc_layer_init;
1201
   enc->quality_params = radeon_enc_quality_params;
1202
   enc->ctx = radeon_enc_ctx;
1203
   enc->bitstream = radeon_enc_bitstream;
1204
   enc->feedback = radeon_enc_feedback;
1205
   enc->intra_refresh = radeon_enc_intra_refresh;
1206
   enc->rc_per_pic = radeon_enc_rc_per_pic;
1207
   enc->encode_params = radeon_enc_encode_params;
1208
   enc->op_init = radeon_enc_op_init;
1209
   enc->op_close = radeon_enc_op_close;
1210
   enc->op_enc = radeon_enc_op_enc;
1211
   enc->op_init_rc = radeon_enc_op_init_rc;
1212
   enc->op_init_rc_vbv = radeon_enc_op_init_rc_vbv;
1213
   enc->op_preset = radeon_enc_op_speed;
1214

1215
   if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_MPEG4_AVC) {
1216
      enc->session_init = radeon_enc_session_init;
1217
      enc->slice_control = radeon_enc_slice_control;
1218
      enc->spec_misc = radeon_enc_spec_misc;
1219
      enc->deblocking_filter = radeon_enc_deblocking_filter_h264;
1220
      enc->nalu_sps = radeon_enc_nalu_sps;
1221
      enc->nalu_pps = radeon_enc_nalu_pps;
1222
      enc->slice_header = radeon_enc_slice_header;
1223
      enc->encode_params = radeon_enc_encode_params;
1224
      enc->encode_params_codec_spec = radeon_enc_encode_params_h264;
1225
      enc->encode_headers = radeon_enc_headers_h264;
1226
   } else if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_HEVC) {
1227
      enc->session_init = radeon_enc_session_init_hevc;
1228
      enc->slice_control = radeon_enc_slice_control_hevc;
1229
      enc->spec_misc = radeon_enc_spec_misc_hevc;
1230
      enc->deblocking_filter = radeon_enc_deblocking_filter_hevc;
1231
      enc->nalu_sps = radeon_enc_nalu_sps_hevc;
1232
      enc->nalu_pps = radeon_enc_nalu_pps_hevc;
1233
      enc->nalu_vps = radeon_enc_nalu_vps;
1234
      enc->nalu_aud = radeon_enc_nalu_aud_hevc;
1235
      enc->slice_header = radeon_enc_slice_header_hevc;
1236
      enc->encode_params = radeon_enc_encode_params_hevc;
1237
      enc->encode_headers = radeon_enc_headers_hevc;
1238
   }
1239

1240
   enc->cmd.session_info = RENCODE_IB_PARAM_SESSION_INFO;
1241
   enc->cmd.task_info = RENCODE_IB_PARAM_TASK_INFO;
1242
   enc->cmd.session_init = RENCODE_IB_PARAM_SESSION_INIT;
1243
   enc->cmd.layer_control = RENCODE_IB_PARAM_LAYER_CONTROL;
1244
   enc->cmd.layer_select = RENCODE_IB_PARAM_LAYER_SELECT;
1245
   enc->cmd.rc_session_init = RENCODE_IB_PARAM_RATE_CONTROL_SESSION_INIT;
1246
   enc->cmd.rc_layer_init = RENCODE_IB_PARAM_RATE_CONTROL_LAYER_INIT;
1247
   enc->cmd.rc_per_pic = RENCODE_IB_PARAM_RATE_CONTROL_PER_PICTURE;
1248
   enc->cmd.quality_params = RENCODE_IB_PARAM_QUALITY_PARAMS;
1249
   enc->cmd.nalu = RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU;
1250
   enc->cmd.slice_header = RENCODE_IB_PARAM_SLICE_HEADER;
1251
   enc->cmd.enc_params = RENCODE_IB_PARAM_ENCODE_PARAMS;
1252
   enc->cmd.intra_refresh = RENCODE_IB_PARAM_INTRA_REFRESH;
1253
   enc->cmd.ctx = RENCODE_IB_PARAM_ENCODE_CONTEXT_BUFFER;
1254
   enc->cmd.bitstream = RENCODE_IB_PARAM_VIDEO_BITSTREAM_BUFFER;
1255
   enc->cmd.feedback = RENCODE_IB_PARAM_FEEDBACK_BUFFER;
1256
   enc->cmd.slice_control_hevc = RENCODE_HEVC_IB_PARAM_SLICE_CONTROL;
1257
   enc->cmd.spec_misc_hevc = RENCODE_HEVC_IB_PARAM_SPEC_MISC;
1258
   enc->cmd.deblocking_filter_hevc = RENCODE_HEVC_IB_PARAM_DEBLOCKING_FILTER;
1259
   enc->cmd.slice_control_h264 = RENCODE_H264_IB_PARAM_SLICE_CONTROL;
1260
   enc->cmd.spec_misc_h264 = RENCODE_H264_IB_PARAM_SPEC_MISC;
1261
   enc->cmd.enc_params_h264 = RENCODE_H264_IB_PARAM_ENCODE_PARAMS;
1262
   enc->cmd.deblocking_filter_h264 = RENCODE_H264_IB_PARAM_DEBLOCKING_FILTER;
1263

1264
   enc->enc_pic.session_info.interface_version =
1265
      ((RENCODE_FW_INTERFACE_MAJOR_VERSION << RENCODE_IF_MAJOR_VERSION_SHIFT) |
1266
       (RENCODE_FW_INTERFACE_MINOR_VERSION << RENCODE_IF_MINOR_VERSION_SHIFT));
1267
}
1268

1269
Product

Resources

Company
