CoCalc -- radeon_vcn_enc_2

GitHub Repository: PojavLauncherTeam/mesa
Path: blob/21.2-virgl/src/gallium/drivers/radeon/radeon_vcn_enc_2_0.c
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/**************************************************************************
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 *
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 * Copyright 2017 Advanced Micro Devices, Inc.
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 * All Rights Reserved.
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a
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 * copy of this software and associated documentation files (the
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 * "Software"), to deal in the Software without restriction, including
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 * without limitation the rights to use, copy, modify, merge, publish,
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 * distribute, sub license, and/or sell copies of the Software, and to
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 * permit persons to whom the Software is furnished to do so, subject to
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 * the following conditions:
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 *
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 * The above copyright notice and this permission notice (including the
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 * next paragraph) shall be included in all copies or substantial portions
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 * of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
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 * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
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 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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 *
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 **************************************************************************/
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#include "pipe/p_video_codec.h"
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#include "radeon_vcn_enc.h"
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#include "radeon_video.h"
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#include "si_pipe.h"
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#include "util/u_video.h"
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#include <stdio.h>
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#define RENCODE_FW_INTERFACE_MAJOR_VERSION         1
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#define RENCODE_FW_INTERFACE_MINOR_VERSION         1
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#define RENCODE_IB_PARAM_SESSION_INFO              0x00000001
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#define RENCODE_IB_PARAM_TASK_INFO                 0x00000002
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#define RENCODE_IB_PARAM_SESSION_INIT              0x00000003
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#define RENCODE_IB_PARAM_LAYER_CONTROL             0x00000004
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#define RENCODE_IB_PARAM_LAYER_SELECT              0x00000005
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#define RENCODE_IB_PARAM_RATE_CONTROL_SESSION_INIT 0x00000006
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#define RENCODE_IB_PARAM_RATE_CONTROL_LAYER_INIT   0x00000007
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#define RENCODE_IB_PARAM_RATE_CONTROL_PER_PICTURE  0x00000008
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#define RENCODE_IB_PARAM_QUALITY_PARAMS            0x00000009
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#define RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU        0x0000000a
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#define RENCODE_IB_PARAM_SLICE_HEADER              0x0000000b
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#define RENCODE_IB_PARAM_INPUT_FORMAT              0x0000000c
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#define RENCODE_IB_PARAM_OUTPUT_FORMAT             0x0000000d
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#define RENCODE_IB_PARAM_ENCODE_PARAMS             0x0000000f
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#define RENCODE_IB_PARAM_INTRA_REFRESH             0x00000010
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#define RENCODE_IB_PARAM_ENCODE_CONTEXT_BUFFER     0x00000011
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#define RENCODE_IB_PARAM_VIDEO_BITSTREAM_BUFFER    0x00000012
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#define RENCODE_IB_PARAM_FEEDBACK_BUFFER           0x00000015
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#define RENCODE_HEVC_IB_PARAM_SLICE_CONTROL        0x00100001
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#define RENCODE_HEVC_IB_PARAM_SPEC_MISC            0x00100002
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#define RENCODE_HEVC_IB_PARAM_LOOP_FILTER          0x00100003
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#define RENCODE_H264_IB_PARAM_SLICE_CONTROL        0x00200001
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#define RENCODE_H264_IB_PARAM_SPEC_MISC            0x00200002
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#define RENCODE_H264_IB_PARAM_ENCODE_PARAMS        0x00200003
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#define RENCODE_H264_IB_PARAM_DEBLOCKING_FILTER    0x00200004
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#define RENCODE_COLOR_VOLUME_G22_BT709             0
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#define RENCODE_COLOR_VOLUME_G10_BT2020            3
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#define RENCODE_COLOR_BIT_DEPTH_8_BIT              0
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#define RENCODE_COLOR_BIT_DEPTH_10_BIT             1
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#define RENCODE_COLOR_PACKING_FORMAT_NV12          0
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#define RENCODE_COLOR_PACKING_FORMAT_P010          1
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static void radeon_enc_op_balance(struct radeon_encoder *enc)
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{
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   RADEON_ENC_BEGIN(RENCODE_IB_OP_SET_BALANCE_ENCODING_MODE);
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   RADEON_ENC_END();
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}
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static void radeon_enc_slice_header_hevc(struct radeon_encoder *enc)
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{
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   uint32_t instruction[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
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   uint32_t num_bits[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
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   unsigned int inst_index = 0;
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   unsigned int cdw_start = 0;
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   unsigned int cdw_filled = 0;
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   unsigned int bits_copied = 0;
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   RADEON_ENC_BEGIN(enc->cmd.slice_header);
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   radeon_enc_reset(enc);
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   radeon_enc_set_emulation_prevention(enc, false);
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   cdw_start = enc->cs.current.cdw;
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   radeon_enc_code_fixed_bits(enc, 0x0, 1);
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   radeon_enc_code_fixed_bits(enc, enc->enc_pic.nal_unit_type, 6);
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   radeon_enc_code_fixed_bits(enc, 0x0, 6);
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   radeon_enc_code_fixed_bits(enc, 0x1, 3);
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   radeon_enc_flush_headers(enc);
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   instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
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   num_bits[inst_index] = enc->bits_output - bits_copied;
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   bits_copied = enc->bits_output;
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   inst_index++;
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   instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_FIRST_SLICE;
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   inst_index++;
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   if ((enc->enc_pic.nal_unit_type >= 16) && (enc->enc_pic.nal_unit_type <= 23))
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      radeon_enc_code_fixed_bits(enc, 0x0, 1);
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   radeon_enc_code_ue(enc, 0x0);
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   radeon_enc_flush_headers(enc);
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   instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
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   num_bits[inst_index] = enc->bits_output - bits_copied;
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   bits_copied = enc->bits_output;
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   inst_index++;
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   instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_SLICE_SEGMENT;
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   inst_index++;
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   instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_DEPENDENT_SLICE_END;
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   inst_index++;
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   switch (enc->enc_pic.picture_type) {
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   case PIPE_H2645_ENC_PICTURE_TYPE_I:
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   case PIPE_H2645_ENC_PICTURE_TYPE_IDR:
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      radeon_enc_code_ue(enc, 0x2);
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      break;
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   case PIPE_H2645_ENC_PICTURE_TYPE_P:
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   case PIPE_H2645_ENC_PICTURE_TYPE_SKIP:
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      radeon_enc_code_ue(enc, 0x1);
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      break;
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   case PIPE_H2645_ENC_PICTURE_TYPE_B:
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      radeon_enc_code_ue(enc, 0x0);
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      break;
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   default:
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      radeon_enc_code_ue(enc, 0x1);
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   }
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   if ((enc->enc_pic.nal_unit_type != 19) && (enc->enc_pic.nal_unit_type != 20)) {
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      radeon_enc_code_fixed_bits(enc, enc->enc_pic.pic_order_cnt, enc->enc_pic.log2_max_poc);
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      if (enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_P)
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         radeon_enc_code_fixed_bits(enc, 0x1, 1);
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      else {
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         radeon_enc_code_fixed_bits(enc, 0x0, 1);
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         radeon_enc_code_fixed_bits(enc, 0x0, 1);
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         radeon_enc_code_ue(enc, 0x0);
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         radeon_enc_code_ue(enc, 0x0);
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      }
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   }
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   if (enc->enc_pic.sample_adaptive_offset_enabled_flag) {
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      radeon_enc_flush_headers(enc);
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      instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
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      num_bits[inst_index] = enc->bits_output - bits_copied;
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      bits_copied = enc->bits_output;
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      inst_index++;
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      instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_SAO_ENABLE;
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      inst_index++;
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   }
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   if ((enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_P) ||
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       (enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_B)) {
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      radeon_enc_code_fixed_bits(enc, 0x0, 1);
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      radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.cabac_init_flag, 1);
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      radeon_enc_code_ue(enc, 5 - enc->enc_pic.max_num_merge_cand);
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   }
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   radeon_enc_flush_headers(enc);
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   instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
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   num_bits[inst_index] = enc->bits_output - bits_copied;
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   bits_copied = enc->bits_output;
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   inst_index++;
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   instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_SLICE_QP_DELTA;
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   inst_index++;
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   if ((enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled) &&
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       (!enc->enc_pic.hevc_deblock.deblocking_filter_disabled ||
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        enc->enc_pic.sample_adaptive_offset_enabled_flag)) {
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       if (enc->enc_pic.sample_adaptive_offset_enabled_flag) {
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           radeon_enc_flush_headers(enc);
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           instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
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           num_bits[inst_index] = enc->bits_output - bits_copied;
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           bits_copied = enc->bits_output;
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           inst_index++;
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           instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_LOOP_FILTER_ACROSS_SLICES_ENABLE;
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           inst_index++;
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       }
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       else
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           radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled, 1);
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   }
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   radeon_enc_flush_headers(enc);
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   instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
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   num_bits[inst_index] = enc->bits_output - bits_copied;
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   bits_copied = enc->bits_output;
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   inst_index++;
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   instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_END;
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   cdw_filled = enc->cs.current.cdw - cdw_start;
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   for (int i = 0; i < RENCODE_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS - cdw_filled; i++)
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      RADEON_ENC_CS(0x00000000);
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   for (int j = 0; j < RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS; j++) {
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      RADEON_ENC_CS(instruction[j]);
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      RADEON_ENC_CS(num_bits[j]);
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   }
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   RADEON_ENC_END();
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}
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static void radeon_enc_quality_params(struct radeon_encoder *enc)
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{
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   enc->enc_pic.quality_params.vbaq_mode = 0;
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   enc->enc_pic.quality_params.scene_change_sensitivity = 0;
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   enc->enc_pic.quality_params.scene_change_min_idr_interval = 0;
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   enc->enc_pic.quality_params.two_pass_search_center_map_mode = 0;
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   RADEON_ENC_BEGIN(enc->cmd.quality_params);
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   RADEON_ENC_CS(enc->enc_pic.quality_params.vbaq_mode);
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   RADEON_ENC_CS(enc->enc_pic.quality_params.scene_change_sensitivity);
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   RADEON_ENC_CS(enc->enc_pic.quality_params.scene_change_min_idr_interval);
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   RADEON_ENC_CS(enc->enc_pic.quality_params.two_pass_search_center_map_mode);
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   RADEON_ENC_END();
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}
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static void radeon_enc_loop_filter_hevc(struct radeon_encoder *enc)
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{
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   RADEON_ENC_BEGIN(enc->cmd.deblocking_filter_hevc);
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   RADEON_ENC_CS(enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled);
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   RADEON_ENC_CS(enc->enc_pic.hevc_deblock.deblocking_filter_disabled);
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   RADEON_ENC_CS(enc->enc_pic.hevc_deblock.beta_offset_div2);
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   RADEON_ENC_CS(enc->enc_pic.hevc_deblock.tc_offset_div2);
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   RADEON_ENC_CS(enc->enc_pic.hevc_deblock.cb_qp_offset);
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   RADEON_ENC_CS(enc->enc_pic.hevc_deblock.cr_qp_offset);
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   RADEON_ENC_CS(!enc->enc_pic.sample_adaptive_offset_enabled_flag);
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   RADEON_ENC_END();
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}
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static void radeon_enc_nalu_sps_hevc(struct radeon_encoder *enc)
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{
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   RADEON_ENC_BEGIN(enc->cmd.nalu);
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   RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_SPS);
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   uint32_t *size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++];
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   int i;
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   radeon_enc_reset(enc);
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   radeon_enc_set_emulation_prevention(enc, false);
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   radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
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   radeon_enc_code_fixed_bits(enc, 0x4201, 16);
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   radeon_enc_byte_align(enc);
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   radeon_enc_set_emulation_prevention(enc, true);
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   radeon_enc_code_fixed_bits(enc, 0x0, 4);
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   radeon_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1, 3);
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   radeon_enc_code_fixed_bits(enc, 0x1, 1);
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   radeon_enc_code_fixed_bits(enc, 0x0, 2);
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   radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_tier_flag, 1);
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   radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_profile_idc, 5);
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   if (enc->enc_pic.general_profile_idc == 2)
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      radeon_enc_code_fixed_bits(enc, 0x20000000, 32);
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   else
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      radeon_enc_code_fixed_bits(enc, 0x60000000, 32);
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   radeon_enc_code_fixed_bits(enc, 0xb0000000, 32);
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   radeon_enc_code_fixed_bits(enc, 0x0, 16);
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   radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_level_idc, 8);
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   for (i = 0; i < (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i++)
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      radeon_enc_code_fixed_bits(enc, 0x0, 2);
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277
   if ((enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1) > 0) {
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      for (i = (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i < 8; i++)
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         radeon_enc_code_fixed_bits(enc, 0x0, 2);
280
   }
281

282
   radeon_enc_code_ue(enc, 0x0);
283
   radeon_enc_code_ue(enc, enc->enc_pic.chroma_format_idc);
284
   radeon_enc_code_ue(enc, enc->enc_pic.session_init.aligned_picture_width);
285
   radeon_enc_code_ue(enc, enc->enc_pic.session_init.aligned_picture_height);
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287
   if ((enc->enc_pic.crop_left != 0) || (enc->enc_pic.crop_right  != 0) ||
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       (enc->enc_pic.crop_top  != 0) || (enc->enc_pic.crop_bottom != 0)) {
289
      radeon_enc_code_fixed_bits(enc, 0x1, 1);
290
      radeon_enc_code_ue(enc, enc->enc_pic.crop_left);
291
      radeon_enc_code_ue(enc, enc->enc_pic.crop_right);
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      radeon_enc_code_ue(enc, enc->enc_pic.crop_top);
293
      radeon_enc_code_ue(enc, enc->enc_pic.crop_bottom);
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   } else if (enc->enc_pic.session_init.padding_width  != 0 ||
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              enc->enc_pic.session_init.padding_height != 0) {
296
      radeon_enc_code_fixed_bits(enc, 0x1, 1);
297
      radeon_enc_code_ue(enc, enc->enc_pic.session_init.padding_width / 2);
298
      radeon_enc_code_ue(enc, enc->enc_pic.session_init.padding_width / 2);
299
      radeon_enc_code_ue(enc, enc->enc_pic.session_init.padding_height / 2);
300
      radeon_enc_code_ue(enc, enc->enc_pic.session_init.padding_height / 2);
301
   } else
302
   radeon_enc_code_fixed_bits(enc, 0x0, 1);
303

304
   radeon_enc_code_ue(enc, enc->enc_pic.bit_depth_luma_minus8);
305
   radeon_enc_code_ue(enc, enc->enc_pic.bit_depth_chroma_minus8);
306
   radeon_enc_code_ue(enc, enc->enc_pic.log2_max_poc - 4);
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   radeon_enc_code_fixed_bits(enc, 0x0, 1);
308
   radeon_enc_code_ue(enc, 1);
309
   radeon_enc_code_ue(enc, 0x0);
310
   radeon_enc_code_ue(enc, 0x0);
311
   radeon_enc_code_ue(enc, enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3);
312
   // Only support CTBSize 64
313
   radeon_enc_code_ue(enc,
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                      6 - (enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3 + 3));
315
   radeon_enc_code_ue(enc, enc->enc_pic.log2_min_transform_block_size_minus2);
316
   radeon_enc_code_ue(enc, enc->enc_pic.log2_diff_max_min_transform_block_size);
317
   radeon_enc_code_ue(enc, enc->enc_pic.max_transform_hierarchy_depth_inter);
318
   radeon_enc_code_ue(enc, enc->enc_pic.max_transform_hierarchy_depth_intra);
319

320
   radeon_enc_code_fixed_bits(enc, 0x0, 1);
321
   radeon_enc_code_fixed_bits(enc, !enc->enc_pic.hevc_spec_misc.amp_disabled, 1);
322
   radeon_enc_code_fixed_bits(enc, enc->enc_pic.sample_adaptive_offset_enabled_flag, 1);
323
   radeon_enc_code_fixed_bits(enc, enc->enc_pic.pcm_enabled_flag, 1);
324

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   radeon_enc_code_ue(enc, 1);
326
   radeon_enc_code_ue(enc, 1);
327
   radeon_enc_code_ue(enc, 0);
328
   radeon_enc_code_ue(enc, 0);
329
   radeon_enc_code_fixed_bits(enc, 0x1, 1);
330

331
   radeon_enc_code_fixed_bits(enc, 0x0, 1);
332

333
   radeon_enc_code_fixed_bits(enc, 0, 1);
334
   radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled, 1);
335

336
   radeon_enc_code_fixed_bits(enc, 0x0, 1);
337

338
   radeon_enc_code_fixed_bits(enc, 0x0, 1);
339

340
   radeon_enc_code_fixed_bits(enc, 0x1, 1);
341

342
   radeon_enc_byte_align(enc);
343
   radeon_enc_flush_headers(enc);
344
   *size_in_bytes = (enc->bits_output + 7) / 8;
345
   RADEON_ENC_END();
346
}
347

348
static void radeon_enc_nalu_pps_hevc(struct radeon_encoder *enc)
349
{
350
   RADEON_ENC_BEGIN(enc->cmd.nalu);
351
   RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_PPS);
352
   uint32_t *size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++];
353
   radeon_enc_reset(enc);
354
   radeon_enc_set_emulation_prevention(enc, false);
355
   radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
356
   radeon_enc_code_fixed_bits(enc, 0x4401, 16);
357
   radeon_enc_byte_align(enc);
358
   radeon_enc_set_emulation_prevention(enc, true);
359
   radeon_enc_code_ue(enc, 0x0);
360
   radeon_enc_code_ue(enc, 0x0);
361
   radeon_enc_code_fixed_bits(enc, 0x1, 1);
362
   radeon_enc_code_fixed_bits(enc, 0x0, 4);
363
   radeon_enc_code_fixed_bits(enc, 0x0, 1);
364
   radeon_enc_code_fixed_bits(enc, 0x1, 1);
365
   radeon_enc_code_ue(enc, 0x0);
366
   radeon_enc_code_ue(enc, 0x0);
367
   radeon_enc_code_se(enc, 0x0);
368
   radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag, 1);
369
   radeon_enc_code_fixed_bits(enc, 0x0, 1);
370
   if (enc->enc_pic.rc_session_init.rate_control_method == RENCODE_RATE_CONTROL_METHOD_NONE)
371
      radeon_enc_code_fixed_bits(enc, 0x0, 1);
372
   else {
373
      radeon_enc_code_fixed_bits(enc, 0x1, 1);
374
      radeon_enc_code_ue(enc, 0x0);
375
   }
376
   radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cb_qp_offset);
377
   radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cr_qp_offset);
378
   radeon_enc_code_fixed_bits(enc, 0x0, 1);
379
   radeon_enc_code_fixed_bits(enc, 0x0, 2);
380
   radeon_enc_code_fixed_bits(enc, 0x0, 1);
381
   radeon_enc_code_fixed_bits(enc, 0x0, 1);
382
   radeon_enc_code_fixed_bits(enc, 0x0, 1);
383
   radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled, 1);
384
   radeon_enc_code_fixed_bits(enc, 0x1, 1);
385
   radeon_enc_code_fixed_bits(enc, 0x0, 1);
386
   radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.deblocking_filter_disabled, 1);
387

388
   if (!enc->enc_pic.hevc_deblock.deblocking_filter_disabled) {
389
      radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.beta_offset_div2);
390
      radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.tc_offset_div2);
391
   }
392

393
   radeon_enc_code_fixed_bits(enc, 0x0, 1);
394
   radeon_enc_code_fixed_bits(enc, 0x0, 1);
395
   radeon_enc_code_ue(enc, enc->enc_pic.log2_parallel_merge_level_minus2);
396
   radeon_enc_code_fixed_bits(enc, 0x0, 2);
397

398
   radeon_enc_code_fixed_bits(enc, 0x1, 1);
399

400
   radeon_enc_byte_align(enc);
401
   radeon_enc_flush_headers(enc);
402
   *size_in_bytes = (enc->bits_output + 7) / 8;
403
   RADEON_ENC_END();
404
}
405

406
static void radeon_enc_input_format(struct radeon_encoder *enc)
407
{
408
   RADEON_ENC_BEGIN(enc->cmd.input_format);
409
   if (enc->base.profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10) {
410
      RADEON_ENC_CS(RENCODE_COLOR_VOLUME_G10_BT2020);
411
      RADEON_ENC_CS(0);
412
      RADEON_ENC_CS(0);
413
      RADEON_ENC_CS(0);
414
      RADEON_ENC_CS(0);
415
      RADEON_ENC_CS(RENCODE_COLOR_BIT_DEPTH_10_BIT);
416
      RADEON_ENC_CS(RENCODE_COLOR_PACKING_FORMAT_P010);
417
   } else {
418
      RADEON_ENC_CS(RENCODE_COLOR_VOLUME_G22_BT709);
419
      RADEON_ENC_CS(0);
420
      RADEON_ENC_CS(0);
421
      RADEON_ENC_CS(0);
422
      RADEON_ENC_CS(0);
423
      RADEON_ENC_CS(RENCODE_COLOR_BIT_DEPTH_8_BIT);
424
      RADEON_ENC_CS(RENCODE_COLOR_PACKING_FORMAT_NV12);
425
   }
426
   RADEON_ENC_END();
427
}
428

429
static void radeon_enc_output_format(struct radeon_encoder *enc)
430
{
431
   RADEON_ENC_BEGIN(enc->cmd.output_format);
432
   if (enc->base.profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10) {
433
      RADEON_ENC_CS(RENCODE_COLOR_VOLUME_G10_BT2020);
434
      RADEON_ENC_CS(0);
435
      RADEON_ENC_CS(0);
436
      RADEON_ENC_CS(RENCODE_COLOR_BIT_DEPTH_10_BIT);
437
   } else {
438
      RADEON_ENC_CS(RENCODE_COLOR_VOLUME_G22_BT709);
439
      RADEON_ENC_CS(0);
440
      RADEON_ENC_CS(0);
441
      RADEON_ENC_CS(RENCODE_COLOR_BIT_DEPTH_8_BIT);
442
   }
443
   RADEON_ENC_END();
444
}
445

446
static void radeon_enc_ctx(struct radeon_encoder *enc)
447
{
448
   enc->enc_pic.ctx_buf.swizzle_mode = 0;
449

450
   uint32_t aligned_width = enc->enc_pic.session_init.aligned_picture_width;
451
   uint32_t aligned_height = enc->enc_pic.session_init.aligned_picture_height;
452

453
   enc->enc_pic.ctx_buf.rec_luma_pitch = align(aligned_width, enc->alignment);
454
   enc->enc_pic.ctx_buf.rec_chroma_pitch = align(aligned_width, enc->alignment);
455

456
   int luma_size = enc->enc_pic.ctx_buf.rec_luma_pitch * align(aligned_height, enc->alignment);
457
   if (enc->enc_pic.bit_depth_luma_minus8 == 2)
458
      luma_size *= 2;
459
   int chroma_size = align(luma_size / 2, enc->alignment);
460
   int offset = 0;
461

462
   enc->enc_pic.ctx_buf.num_reconstructed_pictures = 2;
463
   for (int i = 0; i < enc->enc_pic.ctx_buf.num_reconstructed_pictures; i++) {
464
      enc->enc_pic.ctx_buf.reconstructed_pictures[i].luma_offset = offset;
465
      offset += luma_size;
466
      enc->enc_pic.ctx_buf.reconstructed_pictures[i].chroma_offset = offset;
467
      offset += chroma_size;
468
   }
469

470
   RADEON_ENC_BEGIN(enc->cmd.ctx);
471
   RADEON_ENC_READWRITE(enc->cpb.res->buf, enc->cpb.res->domains, 0);
472
   RADEON_ENC_CS(enc->enc_pic.ctx_buf.swizzle_mode);
473
   RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_luma_pitch);
474
   RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_chroma_pitch);
475
   RADEON_ENC_CS(enc->enc_pic.ctx_buf.num_reconstructed_pictures);
476

477
   for (int i = 0; i < enc->enc_pic.ctx_buf.num_reconstructed_pictures; i++) {
478
      RADEON_ENC_CS(enc->enc_pic.ctx_buf.reconstructed_pictures[i].luma_offset);
479
      RADEON_ENC_CS(enc->enc_pic.ctx_buf.reconstructed_pictures[i].chroma_offset);
480
   }
481

482
   for (int i = 0; i < 136; i++)
483
      RADEON_ENC_CS(0x00000000);
484

485
   RADEON_ENC_END();
486
}
487

488
static void encode(struct radeon_encoder *enc)
489
{
490
   enc->session_info(enc);
491
   enc->total_task_size = 0;
492
   enc->task_info(enc, enc->need_feedback);
493

494
   enc->encode_headers(enc);
495
   enc->ctx(enc);
496
   enc->bitstream(enc);
497
   enc->feedback(enc);
498
   enc->intra_refresh(enc);
499
   enc->input_format(enc);
500
   enc->output_format(enc);
501

502
   enc->op_preset(enc);
503
   enc->op_enc(enc);
504
   *enc->p_task_size = (enc->total_task_size);
505
}
506

507
void radeon_enc_2_0_init(struct radeon_encoder *enc)
508
{
509
   radeon_enc_1_2_init(enc);
510
   enc->encode = encode;
511
   enc->ctx = radeon_enc_ctx;
512
   enc->quality_params = radeon_enc_quality_params;
513
   enc->input_format = radeon_enc_input_format;
514
   enc->output_format = radeon_enc_output_format;
515

516
   if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_HEVC) {
517
      enc->deblocking_filter = radeon_enc_loop_filter_hevc;
518
      enc->nalu_sps = radeon_enc_nalu_sps_hevc;
519
      enc->nalu_pps = radeon_enc_nalu_pps_hevc;
520
      enc->slice_header = radeon_enc_slice_header_hevc;
521
      enc->op_preset = radeon_enc_op_balance;
522
   }
523

524
   enc->cmd.session_info = RENCODE_IB_PARAM_SESSION_INFO;
525
   enc->cmd.task_info = RENCODE_IB_PARAM_TASK_INFO;
526
   enc->cmd.session_init = RENCODE_IB_PARAM_SESSION_INIT;
527
   enc->cmd.layer_control = RENCODE_IB_PARAM_LAYER_CONTROL;
528
   enc->cmd.layer_select = RENCODE_IB_PARAM_LAYER_SELECT;
529
   enc->cmd.rc_session_init = RENCODE_IB_PARAM_RATE_CONTROL_SESSION_INIT;
530
   enc->cmd.rc_layer_init = RENCODE_IB_PARAM_RATE_CONTROL_LAYER_INIT;
531
   enc->cmd.rc_per_pic = RENCODE_IB_PARAM_RATE_CONTROL_PER_PICTURE;
532
   enc->cmd.quality_params = RENCODE_IB_PARAM_QUALITY_PARAMS;
533
   enc->cmd.nalu = RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU;
534
   enc->cmd.slice_header = RENCODE_IB_PARAM_SLICE_HEADER;
535
   enc->cmd.input_format = RENCODE_IB_PARAM_INPUT_FORMAT;
536
   enc->cmd.output_format = RENCODE_IB_PARAM_OUTPUT_FORMAT;
537
   enc->cmd.enc_params = RENCODE_IB_PARAM_ENCODE_PARAMS;
538
   enc->cmd.intra_refresh = RENCODE_IB_PARAM_INTRA_REFRESH;
539
   enc->cmd.ctx = RENCODE_IB_PARAM_ENCODE_CONTEXT_BUFFER;
540
   enc->cmd.bitstream = RENCODE_IB_PARAM_VIDEO_BITSTREAM_BUFFER;
541
   enc->cmd.feedback = RENCODE_IB_PARAM_FEEDBACK_BUFFER;
542
   enc->cmd.slice_control_hevc = RENCODE_HEVC_IB_PARAM_SLICE_CONTROL;
543
   enc->cmd.spec_misc_hevc = RENCODE_HEVC_IB_PARAM_SPEC_MISC;
544
   enc->cmd.deblocking_filter_hevc = RENCODE_HEVC_IB_PARAM_LOOP_FILTER;
545
   enc->cmd.slice_control_h264 = RENCODE_H264_IB_PARAM_SLICE_CONTROL;
546
   enc->cmd.spec_misc_h264 = RENCODE_H264_IB_PARAM_SPEC_MISC;
547
   enc->cmd.enc_params_h264 = RENCODE_H264_IB_PARAM_ENCODE_PARAMS;
548
   enc->cmd.deblocking_filter_h264 = RENCODE_H264_IB_PARAM_DEBLOCKING_FILTER;
549

550
   enc->enc_pic.session_info.interface_version =
551
      ((RENCODE_FW_INTERFACE_MAJOR_VERSION << RENCODE_IF_MAJOR_VERSION_SHIFT) |
552
       (RENCODE_FW_INTERFACE_MINOR_VERSION << RENCODE_IF_MINOR_VERSION_SHIFT));
553
}
554

555
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