CoCalc -- radeon_vcn_enc_3

GitHub Repository: PojavLauncherTeam/mesa
Path: blob/21.2-virgl/src/gallium/drivers/radeon/radeon_vcn_enc_3_0.c
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/**************************************************************************
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 *
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 * Copyright 2020 Advanced Micro Devices, Inc.
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 * All Rights Reserved.
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a
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 * copy of this software and associated documentation files (the
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 * "Software"), to deal in the Software without restriction, including
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 * without limitation the rights to use, copy, modify, merge, publish,
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 * distribute, sub license, and/or sell copies of the Software, and to
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 * permit persons to whom the Software is furnished to do so, subject to
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 * the following conditions:
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 *
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 * The above copyright notice and this permission notice (including the
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 * next paragraph) shall be included in all copies or substantial portions
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 * of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
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 * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
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 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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 *
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 **************************************************************************/
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#include <stdio.h>
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#include "pipe/p_video_codec.h"
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#include "util/u_video.h"
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#include "si_pipe.h"
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#include "radeon_video.h"
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#include "radeon_vcn_enc.h"
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#define RENCODE_FW_INTERFACE_MAJOR_VERSION   1
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#define RENCODE_FW_INTERFACE_MINOR_VERSION   0
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static void radeon_enc_spec_misc(struct radeon_encoder *enc)
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{
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   enc->enc_pic.spec_misc.constrained_intra_pred_flag = 0;
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   enc->enc_pic.spec_misc.cabac_enable = 0;
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   enc->enc_pic.spec_misc.cabac_init_idc = 0;
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   enc->enc_pic.spec_misc.half_pel_enabled = 1;
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   enc->enc_pic.spec_misc.quarter_pel_enabled = 1;
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   enc->enc_pic.spec_misc.profile_idc = u_get_h264_profile_idc(enc->base.profile);
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   enc->enc_pic.spec_misc.level_idc = enc->base.level;
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   enc->enc_pic.spec_misc.b_picture_enabled = 0;
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   enc->enc_pic.spec_misc.weighted_bipred_idc = 0;
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   RADEON_ENC_BEGIN(enc->cmd.spec_misc_h264);
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   RADEON_ENC_CS(enc->enc_pic.spec_misc.constrained_intra_pred_flag);
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   RADEON_ENC_CS(enc->enc_pic.spec_misc.cabac_enable);
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   RADEON_ENC_CS(enc->enc_pic.spec_misc.cabac_init_idc);
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   RADEON_ENC_CS(enc->enc_pic.spec_misc.half_pel_enabled);
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   RADEON_ENC_CS(enc->enc_pic.spec_misc.quarter_pel_enabled);
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   RADEON_ENC_CS(enc->enc_pic.spec_misc.profile_idc);
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   RADEON_ENC_CS(enc->enc_pic.spec_misc.level_idc);
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   RADEON_ENC_CS(enc->enc_pic.spec_misc.b_picture_enabled);
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   RADEON_ENC_CS(enc->enc_pic.spec_misc.weighted_bipred_idc);
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   RADEON_ENC_END();
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}
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static void radeon_enc_quality_params(struct radeon_encoder *enc)
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{
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   enc->enc_pic.quality_params.vbaq_mode = 0;
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   enc->enc_pic.quality_params.scene_change_sensitivity = 0;
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   enc->enc_pic.quality_params.scene_change_min_idr_interval = 0;
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   enc->enc_pic.quality_params.two_pass_search_center_map_mode = 0;
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   RADEON_ENC_BEGIN(enc->cmd.quality_params);
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   RADEON_ENC_CS(enc->enc_pic.quality_params.vbaq_mode);
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   RADEON_ENC_CS(enc->enc_pic.quality_params.scene_change_sensitivity);
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   RADEON_ENC_CS(enc->enc_pic.quality_params.scene_change_min_idr_interval);
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   RADEON_ENC_CS(enc->enc_pic.quality_params.two_pass_search_center_map_mode);
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   RADEON_ENC_CS(0);
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   RADEON_ENC_END();
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}
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static void radeon_enc_encode_params_h264(struct radeon_encoder *enc)
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{
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   enc->enc_pic.h264_enc_params.input_picture_structure = RENCODE_H264_PICTURE_STRUCTURE_FRAME;
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   enc->enc_pic.h264_enc_params.input_pic_order_cnt = 0;
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   enc->enc_pic.h264_enc_params.interlaced_mode = RENCODE_H264_INTERLACING_MODE_PROGRESSIVE;
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   enc->enc_pic.h264_enc_params.l0_reference_picture1_index = 0xFFFFFFFF;
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   enc->enc_pic.h264_enc_params.l1_reference_picture0_index= 0xFFFFFFFF;
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   RADEON_ENC_BEGIN(enc->cmd.enc_params_h264);
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   RADEON_ENC_CS(enc->enc_pic.h264_enc_params.input_picture_structure);
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   RADEON_ENC_CS(enc->enc_pic.h264_enc_params.input_pic_order_cnt);
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   RADEON_ENC_CS(enc->enc_pic.h264_enc_params.interlaced_mode);
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   RADEON_ENC_CS(enc->enc_pic.h264_enc_params.picture_info_l0_reference_picture0.pic_type);
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   RADEON_ENC_CS(enc->enc_pic.h264_enc_params.picture_info_l0_reference_picture0.is_long_term);
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   RADEON_ENC_CS(enc->enc_pic.h264_enc_params.picture_info_l0_reference_picture0.picture_structure);
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   RADEON_ENC_CS(enc->enc_pic.h264_enc_params.picture_info_l0_reference_picture0.pic_order_cnt);
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   RADEON_ENC_CS(enc->enc_pic.h264_enc_params.l0_reference_picture1_index);
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   RADEON_ENC_CS(enc->enc_pic.h264_enc_params.picture_info_l0_reference_picture1.pic_type);
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   RADEON_ENC_CS(enc->enc_pic.h264_enc_params.picture_info_l0_reference_picture1.is_long_term);
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   RADEON_ENC_CS(enc->enc_pic.h264_enc_params.picture_info_l0_reference_picture1.picture_structure);
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   RADEON_ENC_CS(enc->enc_pic.h264_enc_params.picture_info_l0_reference_picture1.pic_order_cnt);
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   RADEON_ENC_CS(enc->enc_pic.h264_enc_params.l1_reference_picture0_index);
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   RADEON_ENC_CS(enc->enc_pic.h264_enc_params.picture_info_l1_reference_picture0.pic_type);
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   RADEON_ENC_CS(enc->enc_pic.h264_enc_params.picture_info_l1_reference_picture0.is_long_term);
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   RADEON_ENC_CS(enc->enc_pic.h264_enc_params.picture_info_l1_reference_picture0.picture_structure);
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   RADEON_ENC_CS(enc->enc_pic.h264_enc_params.picture_info_l1_reference_picture0.pic_order_cnt);
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   RADEON_ENC_END();
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}
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static void radeon_enc_nalu_pps_hevc(struct radeon_encoder *enc)
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{
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   uint32_t *size_in_bytes;
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   RADEON_ENC_BEGIN(enc->cmd.nalu);
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   RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_PPS);
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   size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++];
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   radeon_enc_reset(enc);
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   radeon_enc_set_emulation_prevention(enc, false);
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   radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
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   radeon_enc_code_fixed_bits(enc, 0x4401, 16);
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   radeon_enc_byte_align(enc);
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   radeon_enc_set_emulation_prevention(enc, true);
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   radeon_enc_code_ue(enc, 0x0);
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   radeon_enc_code_ue(enc, 0x0);
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   radeon_enc_code_fixed_bits(enc, 0x1, 1);
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   radeon_enc_code_fixed_bits(enc, 0x0, 4);
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   radeon_enc_code_fixed_bits(enc, 0x0, 1);
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   radeon_enc_code_fixed_bits(enc, 0x1, 1);
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   radeon_enc_code_ue(enc, 0x0);
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   radeon_enc_code_ue(enc, 0x0);
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   radeon_enc_code_se(enc, 0x0);
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   radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag, 1);
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   radeon_enc_code_fixed_bits(enc, 0x1, 1);
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   if (enc->enc_pic.rc_session_init.rate_control_method ==
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      RENCODE_RATE_CONTROL_METHOD_NONE)
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      radeon_enc_code_fixed_bits(enc, 0x0, 1);
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   else {
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      radeon_enc_code_fixed_bits(enc, 0x1, 1);
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      radeon_enc_code_ue(enc, 0x0);
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   }
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   radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cb_qp_offset);
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   radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cr_qp_offset);
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   radeon_enc_code_fixed_bits(enc, 0x0, 1);
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   radeon_enc_code_fixed_bits(enc, 0x0, 2);
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   radeon_enc_code_fixed_bits(enc, 0x0, 1);
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   radeon_enc_code_fixed_bits(enc, 0x0, 1);
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   radeon_enc_code_fixed_bits(enc, 0x0, 1);
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   radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled, 1);
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   radeon_enc_code_fixed_bits(enc, 0x1, 1);
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   radeon_enc_code_fixed_bits(enc, 0x0, 1);
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   radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.deblocking_filter_disabled, 1);
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   if (!enc->enc_pic.hevc_deblock.deblocking_filter_disabled) {
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      radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.beta_offset_div2);
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      radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.tc_offset_div2);
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   }
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   radeon_enc_code_fixed_bits(enc, 0x0, 1);
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   radeon_enc_code_fixed_bits(enc, 0x0, 1);
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   radeon_enc_code_ue(enc, enc->enc_pic.log2_parallel_merge_level_minus2);
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   radeon_enc_code_fixed_bits(enc, 0x0, 2);
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   radeon_enc_code_fixed_bits(enc, 0x1, 1);
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   radeon_enc_byte_align(enc);
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   radeon_enc_flush_headers(enc);
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   *size_in_bytes = (enc->bits_output + 7) / 8;
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   RADEON_ENC_END();
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}
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void radeon_enc_3_0_init(struct radeon_encoder *enc)
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{
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   radeon_enc_2_0_init(enc);
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   if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_MPEG4_AVC) {
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      enc->spec_misc = radeon_enc_spec_misc;
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      enc->encode_params_codec_spec = radeon_enc_encode_params_h264;
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      enc->quality_params = radeon_enc_quality_params;
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   }
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   if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_HEVC)
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      enc->nalu_pps = radeon_enc_nalu_pps_hevc;
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   enc->enc_pic.session_info.interface_version =
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      ((RENCODE_FW_INTERFACE_MAJOR_VERSION << RENCODE_IF_MAJOR_VERSION_SHIFT) |
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      (RENCODE_FW_INTERFACE_MINOR_VERSION << RENCODE_IF_MINOR_VERSION_SHIFT));
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}
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