CoCalc -- si_build

GitHub Repository: PojavLauncherTeam/mesa
Path: blob/21.2-virgl/src/gallium/drivers/radeonsi/si_build_pm4.h
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/*
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 * Copyright 2013 Advanced Micro Devices, Inc.
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 * All Rights Reserved.
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a
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 * copy of this software and associated documentation files (the "Software"),
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 * to deal in the Software without restriction, including without limitation
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 * on the rights to use, copy, modify, merge, publish, distribute, sub
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 * license, and/or sell copies of the Software, and to permit persons to whom
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 * the Software is furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice (including the next
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 * paragraph) shall be included in all copies or substantial portions of the
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 * Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
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 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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 * USE OR OTHER DEALINGS IN THE SOFTWARE.
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 */
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/**
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 * This file contains helpers for writing commands to commands streams.
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 */
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#ifndef SI_BUILD_PM4_H
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#define SI_BUILD_PM4_H
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#include "si_pipe.h"
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#include "sid.h"
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#if 0
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#include "ac_shadowed_regs.h"
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#define SI_CHECK_SHADOWED_REGS(reg_offset, count) ac_check_shadowed_regs(GFX10, CHIP_NAVI14, reg_offset, count)
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#else
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#define SI_CHECK_SHADOWED_REGS(reg_offset, count)
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#endif
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#define radeon_begin(cs) struct radeon_cmdbuf *__cs = (cs); \
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                         unsigned __cs_num = __cs->current.cdw; \
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                         UNUSED unsigned __cs_num_initial = __cs_num; \
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                         uint32_t *__cs_buf = __cs->current.buf
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#define radeon_begin_again(cs) do { \
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   assert(__cs == NULL); \
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   __cs = (cs); \
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   __cs_num = __cs->current.cdw; \
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   __cs_num_initial = __cs_num; \
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   __cs_buf = __cs->current.buf; \
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} while (0)
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#define radeon_end() do { \
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   __cs->current.cdw = __cs_num; \
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   assert(__cs->current.cdw <= __cs->current.max_dw); \
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   __cs = NULL; \
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} while (0)
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#define radeon_emit(cs, value)  __cs_buf[__cs_num++] = (value)
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#define radeon_packets_added()  (__cs_num != __cs_num_initial)
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#define radeon_end_update_context_roll(sctx) do { \
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   radeon_end(); \
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   if (radeon_packets_added()) \
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      (sctx)->context_roll = true; \
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} while (0)
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#define radeon_emit_array(cs, values, num) do { \
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   unsigned __n = (num); \
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   memcpy(__cs_buf + __cs_num, (values), __n * 4); \
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   __cs_num += __n; \
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} while (0)
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#define radeon_set_config_reg_seq(cs, reg, num) do { \
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   SI_CHECK_SHADOWED_REGS(reg, num); \
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   assert((reg) < SI_CONTEXT_REG_OFFSET); \
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   radeon_emit(cs, PKT3(PKT3_SET_CONFIG_REG, num, 0)); \
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   radeon_emit(cs, ((reg) - SI_CONFIG_REG_OFFSET) >> 2); \
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} while (0)
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#define radeon_set_config_reg(cs, reg, value) do { \
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   radeon_set_config_reg_seq(cs, reg, 1); \
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   radeon_emit(cs, value); \
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} while (0)
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#define radeon_set_context_reg_seq(cs, reg, num) do { \
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   SI_CHECK_SHADOWED_REGS(reg, num); \
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   assert((reg) >= SI_CONTEXT_REG_OFFSET); \
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   radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, num, 0)); \
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   radeon_emit(cs, ((reg) - SI_CONTEXT_REG_OFFSET) >> 2); \
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} while (0)
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#define radeon_set_context_reg(cs, reg, value) do { \
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   radeon_set_context_reg_seq(cs, reg, 1); \
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   radeon_emit(cs, value); \
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} while (0)
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#define radeon_set_context_reg_seq_array(cs, reg, num, values) do { \
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   radeon_set_context_reg_seq(cs, reg, num); \
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   radeon_emit_array(cs, values, num); \
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} while (0)
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#define radeon_set_context_reg_idx(cs, reg, idx, value) do { \
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   SI_CHECK_SHADOWED_REGS(reg, 1); \
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   assert((reg) >= SI_CONTEXT_REG_OFFSET); \
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   radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, 1, 0)); \
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   radeon_emit(cs, ((reg) - SI_CONTEXT_REG_OFFSET) >> 2 | ((idx) << 28)); \
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   radeon_emit(cs, value); \
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} while (0)
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#define radeon_set_sh_reg_seq(cs, reg, num) do { \
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   SI_CHECK_SHADOWED_REGS(reg, num); \
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   assert((reg) >= SI_SH_REG_OFFSET && (reg) < SI_SH_REG_END); \
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   radeon_emit(cs, PKT3(PKT3_SET_SH_REG, num, 0)); \
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   radeon_emit(cs, ((reg) - SI_SH_REG_OFFSET) >> 2); \
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} while (0)
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#define radeon_set_sh_reg(cs, reg, value) do { \
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   radeon_set_sh_reg_seq(cs, reg, 1); \
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   radeon_emit(cs, value); \
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} while (0)
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#define radeon_set_uconfig_reg_seq(cs, reg, num, perfctr) do { \
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   SI_CHECK_SHADOWED_REGS(reg, num); \
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   assert((reg) >= CIK_UCONFIG_REG_OFFSET && (reg) < CIK_UCONFIG_REG_END); \
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   radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, num, perfctr)); \
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   radeon_emit(cs, ((reg) - CIK_UCONFIG_REG_OFFSET) >> 2); \
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} while (0)
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#define radeon_set_uconfig_reg(cs, reg, value) do { \
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   radeon_set_uconfig_reg_seq(cs, reg, 1, false); \
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   radeon_emit(cs, value); \
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} while (0)
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#define radeon_set_uconfig_reg_perfctr(cs, reg, value) do { \
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   radeon_set_uconfig_reg_seq(cs, reg, 1, true); \
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   radeon_emit(cs, value); \
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} while (0)
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#define radeon_set_uconfig_reg_idx(cs, screen, chip_class, reg, idx, value) do { \
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   SI_CHECK_SHADOWED_REGS(reg, 1); \
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   assert((reg) >= CIK_UCONFIG_REG_OFFSET && (reg) < CIK_UCONFIG_REG_END); \
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   assert((idx) != 0); \
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   unsigned __opcode = PKT3_SET_UCONFIG_REG_INDEX; \
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   if ((chip_class) < GFX9 || \
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       ((chip_class) == GFX9 && (screen)->info.me_fw_version < 26)) \
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      __opcode = PKT3_SET_UCONFIG_REG; \
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   radeon_emit(cs, PKT3(__opcode, 1, 0)); \
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   radeon_emit(cs, ((reg) - CIK_UCONFIG_REG_OFFSET) >> 2 | ((idx) << 28)); \
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   radeon_emit(cs, value); \
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} while (0)
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#define radeon_set_context_reg_rmw(cs, reg, value, mask) do { \
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   SI_CHECK_SHADOWED_REGS(reg, 1); \
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   assert((reg) >= SI_CONTEXT_REG_OFFSET); \
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   radeon_emit(cs, PKT3(PKT3_CONTEXT_REG_RMW, 2, 0)); \
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   radeon_emit(cs, ((reg) - SI_CONTEXT_REG_OFFSET) >> 2); \
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   radeon_emit(cs, mask); \
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   radeon_emit(cs, value); \
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} while (0)
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/* Emit PKT3_CONTEXT_REG_RMW if the register value is different. */
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#define radeon_opt_set_context_reg_rmw(sctx, offset, reg, val, mask) do { \
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   unsigned __value = (val); \
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   assert((__value & ~mask) == 0); \
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   __value &= mask; \
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   if (((sctx->tracked_regs.reg_saved >> (reg)) & 0x1) != 0x1 || \
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       sctx->tracked_regs.reg_value[reg] != __value) { \
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      radeon_set_context_reg_rmw(&sctx->gfx_cs, offset, __value, mask); \
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      sctx->tracked_regs.reg_saved |= 0x1ull << (reg); \
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      sctx->tracked_regs.reg_value[reg] = __value; \
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   } \
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} while (0)
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/* Emit PKT3_SET_CONTEXT_REG if the register value is different. */
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#define radeon_opt_set_context_reg(sctx, offset, reg, val) do { \
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   unsigned __value = val; \
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   if (((sctx->tracked_regs.reg_saved >> (reg)) & 0x1) != 0x1 || \
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       sctx->tracked_regs.reg_value[reg] != __value) { \
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      radeon_set_context_reg(&sctx->gfx_cs, offset, __value); \
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      sctx->tracked_regs.reg_saved |= 0x1ull << (reg); \
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      sctx->tracked_regs.reg_value[reg] = __value; \
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   } \
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} while (0)
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/**
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 * Set 2 consecutive registers if any registers value is different.
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 * @param offset        starting register offset
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 * @param val1          is written to first register
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 * @param val2          is written to second register
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 */
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#define radeon_opt_set_context_reg2(sctx, offset, reg, val1, val2) do { \
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   unsigned __value1 = (val1), __value2 = (val2); \
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   if (((sctx->tracked_regs.reg_saved >> (reg)) & 0x3) != 0x3 || \
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       sctx->tracked_regs.reg_value[reg] != __value1 || \
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       sctx->tracked_regs.reg_value[(reg) + 1] != __value2) { \
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      radeon_set_context_reg_seq(&sctx->gfx_cs, offset, 2); \
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      radeon_emit(cs, __value1); \
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      radeon_emit(cs, __value2); \
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      sctx->tracked_regs.reg_value[reg] = __value1; \
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      sctx->tracked_regs.reg_value[(reg) + 1] = __value2; \
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      sctx->tracked_regs.reg_saved |= 0x3ull << (reg); \
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   } \
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} while (0)
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/**
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 * Set 3 consecutive registers if any registers value is different.
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 */
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#define radeon_opt_set_context_reg3(sctx, offset, reg, val1, val2, val3) do { \
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   unsigned __value1 = (val1), __value2 = (val2), __value3 = (val3); \
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   if (((sctx->tracked_regs.reg_saved >> (reg)) & 0x7) != 0x7 || \
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       sctx->tracked_regs.reg_value[reg] != __value1 || \
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       sctx->tracked_regs.reg_value[(reg) + 1] != __value2 || \
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       sctx->tracked_regs.reg_value[(reg) + 2] != __value3) { \
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      radeon_set_context_reg_seq(&sctx->gfx_cs, offset, 3); \
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      radeon_emit(cs, __value1); \
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      radeon_emit(cs, __value2); \
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      radeon_emit(cs, __value3); \
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      sctx->tracked_regs.reg_value[reg] = __value1; \
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      sctx->tracked_regs.reg_value[(reg) + 1] = __value2; \
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      sctx->tracked_regs.reg_value[(reg) + 2] = __value3; \
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      sctx->tracked_regs.reg_saved |= 0x7ull << (reg); \
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   } \
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} while (0)
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/**
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 * Set 4 consecutive registers if any registers value is different.
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 */
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#define radeon_opt_set_context_reg4(sctx, offset, reg, val1, val2, val3, val4) do { \
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   unsigned __value1 = (val1), __value2 = (val2), __value3 = (val3), __value4 = (val4); \
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   if (((sctx->tracked_regs.reg_saved >> (reg)) & 0xf) != 0xf || \
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       sctx->tracked_regs.reg_value[reg] != __value1 || \
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       sctx->tracked_regs.reg_value[(reg) + 1] != __value2 || \
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       sctx->tracked_regs.reg_value[(reg) + 2] != __value3 || \
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       sctx->tracked_regs.reg_value[(reg) + 3] != __value4) { \
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      radeon_set_context_reg_seq(&sctx->gfx_cs, offset, 4); \
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      radeon_emit(cs, __value1); \
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      radeon_emit(cs, __value2); \
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      radeon_emit(cs, __value3); \
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      radeon_emit(cs, __value4); \
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      sctx->tracked_regs.reg_value[reg] = __value1; \
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      sctx->tracked_regs.reg_value[(reg) + 1] = __value2; \
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      sctx->tracked_regs.reg_value[(reg) + 2] = __value3; \
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      sctx->tracked_regs.reg_value[(reg) + 3] = __value4; \
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      sctx->tracked_regs.reg_saved |= 0xfull << (reg); \
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   } \
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} while (0)
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/**
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 * Set consecutive registers if any registers value is different.
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 */
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#define radeon_opt_set_context_regn(sctx, offset, value, saved_val, num) do { \
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   for (unsigned i = 0; i < (num); i++) { \
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      if ((saved_val)[i] != (value)[i]) { \
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         radeon_set_context_reg_seq(&(sctx)->gfx_cs, offset, num); \
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         for (unsigned j = 0; j < (num); j++) \
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            radeon_emit(cs, value[j]); \
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         memcpy(saved_val, value, sizeof(uint32_t) * (num)); \
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         break; \
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      } \
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   } \
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} while (0)
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#define radeon_set_privileged_config_reg(cs, reg, value) do { \
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   assert((reg) < CIK_UCONFIG_REG_OFFSET); \
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   radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0)); \
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   radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_IMM) | \
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               COPY_DATA_DST_SEL(COPY_DATA_PERF)); \
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   radeon_emit(cs, value); \
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   radeon_emit(cs, 0); /* unused */ \
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   radeon_emit(cs, (reg) >> 2); \
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   radeon_emit(cs, 0); /* unused */ \
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} while (0)
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#define radeon_emit_32bit_pointer(sscreen, cs, va) do { \
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   radeon_emit(cs, va); \
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   assert((va) == 0 || ((va) >> 32) == sscreen->info.address32_hi); \
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} while (0)
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#define radeon_emit_one_32bit_pointer(sctx, desc, sh_base) do { \
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   unsigned sh_offset = (sh_base) + (desc)->shader_userdata_offset; \
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   radeon_set_sh_reg_seq(&sctx->gfx_cs, sh_offset, 1); \
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   radeon_emit_32bit_pointer(sctx->screen, cs, (desc)->gpu_address); \
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} while (0)
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/* This should be evaluated at compile time if all parameters are constants. */
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static ALWAYS_INLINE unsigned
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si_get_user_data_base(enum chip_class chip_class, enum si_has_tess has_tess,
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                      enum si_has_gs has_gs, enum si_has_ngg ngg,
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                      enum pipe_shader_type shader)
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{
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   switch (shader) {
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   case PIPE_SHADER_VERTEX:
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      /* VS can be bound as VS, ES, or LS. */
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      if (has_tess) {
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         if (chip_class >= GFX10) {
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            return R_00B430_SPI_SHADER_USER_DATA_HS_0;
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         } else if (chip_class == GFX9) {
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            return R_00B430_SPI_SHADER_USER_DATA_LS_0;
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         } else {
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            return R_00B530_SPI_SHADER_USER_DATA_LS_0;
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         }
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      } else if (chip_class >= GFX10) {
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         if (ngg || has_gs) {
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            return R_00B230_SPI_SHADER_USER_DATA_GS_0;
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         } else {
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            return R_00B130_SPI_SHADER_USER_DATA_VS_0;
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         }
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      } else if (has_gs) {
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         return R_00B330_SPI_SHADER_USER_DATA_ES_0;
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      } else {
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         return R_00B130_SPI_SHADER_USER_DATA_VS_0;
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      }
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   case PIPE_SHADER_TESS_CTRL:
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      if (chip_class == GFX9) {
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         return R_00B430_SPI_SHADER_USER_DATA_LS_0;
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      } else {
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         return R_00B430_SPI_SHADER_USER_DATA_HS_0;
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      }
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   case PIPE_SHADER_TESS_EVAL:
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      /* TES can be bound as ES, VS, or not bound. */
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      if (has_tess) {
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         if (chip_class >= GFX10) {
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            if (ngg || has_gs) {
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               return R_00B230_SPI_SHADER_USER_DATA_GS_0;
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            } else {
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               return R_00B130_SPI_SHADER_USER_DATA_VS_0;
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            }
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         } else if (has_gs) {
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            return R_00B330_SPI_SHADER_USER_DATA_ES_0;
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         } else {
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            return R_00B130_SPI_SHADER_USER_DATA_VS_0;
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         }
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      } else {
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         return 0;
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      }
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   case PIPE_SHADER_GEOMETRY:
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      if (chip_class == GFX9) {
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         return R_00B330_SPI_SHADER_USER_DATA_ES_0;
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      } else {
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         return R_00B230_SPI_SHADER_USER_DATA_GS_0;
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      }
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   default:
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      assert(0);
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      return 0;
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   }
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}
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#endif
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