Path: blob/21.2-virgl/src/gallium/drivers/swr/rasterizer/common/simd16intrin.h
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/****************************************************************************1* Copyright (C) 2014-2015 Intel Corporation. All Rights Reserved.2*3* Permission is hereby granted, free of charge, to any person obtaining a4* copy of this software and associated documentation files (the "Software"),5* to deal in the Software without restriction, including without limitation6* the rights to use, copy, modify, merge, publish, distribute, sublicense,7* and/or sell copies of the Software, and to permit persons to whom the8* Software is furnished to do so, subject to the following conditions:9*10* The above copyright notice and this permission notice (including the next11* paragraph) shall be included in all copies or substantial portions of the12* Software.13*14* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER18* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING19* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS20* IN THE SOFTWARE.21****************************************************************************/2223#ifndef __SWR_SIMD16INTRIN_H__24#define __SWR_SIMD16INTRIN_H__2526#if KNOB_SIMD16_WIDTH == 1627typedef SIMD512 SIMD16;28#else29#error Unsupported vector width30#endif // KNOB_SIMD16_WIDTH == 163132#define _simd16_setzero_ps SIMD16::setzero_ps33#define _simd16_setzero_si SIMD16::setzero_si34#define _simd16_set1_ps SIMD16::set1_ps35#define _simd16_set1_epi8 SIMD16::set1_epi836#define _simd16_set1_epi32 SIMD16::set1_epi3237#define _simd16_set_ps SIMD16::set_ps38#define _simd16_set_epi32 SIMD16::set_epi3239#define _simd16_load_ps SIMD16::load_ps40#define _simd16_loadu_ps SIMD16::loadu_ps41#if 142#define _simd16_load1_ps SIMD16::broadcast_ss43#endif44#define _simd16_load_si SIMD16::load_si45#define _simd16_loadu_si SIMD16::loadu_si46#define _simd16_broadcast_ss(m) SIMD16::broadcast_ss((float const*)m)47#define _simd16_store_ps SIMD16::store_ps48#define _simd16_store_si SIMD16::store_si49#define _simd16_extract_ps(a, imm8) SIMD16::extract_ps<imm8>(a)50#define _simd16_extract_si(a, imm8) SIMD16::extract_si<imm8>(a)51#define _simd16_insert_ps(a, b, imm8) SIMD16::insert_ps<imm8>(a, b)52#define _simd16_insert_si(a, b, imm8) SIMD16::insert_si<imm8>(a, b)53#define _simd16_maskstore_ps SIMD16::maskstore_ps54#define _simd16_blend_ps(a, b, mask) SIMD16::blend_ps<mask>(a, b)55#define _simd16_blendv_ps SIMD16::blendv_ps56#define _simd16_blendv_epi32 SIMD16::blendv_epi3257#define _simd16_mul_ps SIMD16::mul_ps58#define _simd16_div_ps SIMD16::div_ps59#define _simd16_add_ps SIMD16::add_ps60#define _simd16_sub_ps SIMD16::sub_ps61#define _simd16_rsqrt_ps SIMD16::rsqrt_ps62#define _simd16_min_ps SIMD16::min_ps63#define _simd16_max_ps SIMD16::max_ps64#define _simd16_movemask_ps SIMD16::movemask_ps65#define _simd16_movemask_pd SIMD16::movemask_pd66#define _simd16_cvtps_epi32 SIMD16::cvtps_epi3267#define _simd16_cvttps_epi32 SIMD16::cvttps_epi3268#define _simd16_cvtepi32_ps SIMD16::cvtepi32_ps69#define _simd16_cmp_ps(a, b, comp) SIMD16::cmp_ps<SIMD16::CompareType(comp)>(a, b)70#define _simd16_cmplt_ps SIMD16::cmplt_ps71#define _simd16_cmpgt_ps SIMD16::cmpgt_ps72#define _simd16_cmpneq_ps SIMD16::cmpneq_ps73#define _simd16_cmpeq_ps SIMD16::cmpeq_ps74#define _simd16_cmpge_ps SIMD16::cmpge_ps75#define _simd16_cmple_ps SIMD16::cmple_ps76#define _simd16_castsi_ps SIMD16::castsi_ps77#define _simd16_castps_si SIMD16::castps_si78#define _simd16_castsi_pd SIMD16::castsi_pd79#define _simd16_castpd_si SIMD16::castpd_si80#define _simd16_castpd_ps SIMD16::castpd_ps81#define _simd16_castps_pd SIMD16::castps_pd82#define _simd16_and_ps SIMD16::and_ps83#define _simd16_andnot_ps SIMD16::andnot_ps84#define _simd16_or_ps SIMD16::or_ps85#define _simd16_xor_ps SIMD16::xor_ps86#define _simd16_round_ps(a, mode) SIMD16::round_ps<SIMD16::RoundMode(mode)>(a)87#define _simd16_mul_epi32 SIMD16::mul_epi3288#define _simd16_mullo_epi32 SIMD16::mullo_epi3289#define _simd16_sub_epi32 SIMD16::sub_epi3290#define _simd16_sub_epi64 SIMD16::sub_epi6491#define _simd16_min_epi32 SIMD16::min_epi3292#define _simd16_max_epi32 SIMD16::max_epi3293#define _simd16_min_epu32 SIMD16::min_epu3294#define _simd16_max_epu32 SIMD16::max_epu3295#define _simd16_add_epi32 SIMD16::add_epi3296#define _simd16_and_si SIMD16::and_si97#define _simd16_andnot_si SIMD16::andnot_si98#define _simd16_or_si SIMD16::or_si99#define _simd16_xor_si SIMD16::xor_si100#define _simd16_cmpeq_epi32 SIMD16::cmpeq_epi32101#define _simd16_cmpgt_epi32 SIMD16::cmpgt_epi32102#define _simd16_cmplt_epi32 SIMD16::cmplt_epi32103#define _simd16_testz_ps SIMD16::testz_ps104#define _simd16_unpacklo_ps SIMD16::unpacklo_ps105#define _simd16_unpackhi_ps SIMD16::unpackhi_ps106#define _simd16_unpacklo_pd SIMD16::unpacklo_pd107#define _simd16_unpackhi_pd SIMD16::unpackhi_pd108#define _simd16_unpacklo_epi8 SIMD16::unpacklo_epi8109#define _simd16_unpackhi_epi8 SIMD16::unpackhi_epi8110#define _simd16_unpacklo_epi16 SIMD16::unpacklo_epi16111#define _simd16_unpackhi_epi16 SIMD16::unpackhi_epi16112#define _simd16_unpacklo_epi32 SIMD16::unpacklo_epi32113#define _simd16_unpackhi_epi32 SIMD16::unpackhi_epi32114#define _simd16_unpacklo_epi64 SIMD16::unpacklo_epi64115#define _simd16_unpackhi_epi64 SIMD16::unpackhi_epi64116#define _simd16_slli_epi32(a, i) SIMD16::slli_epi32<i>(a)117#define _simd16_srli_epi32(a, i) SIMD16::srli_epi32<i>(a)118#define _simd16_srai_epi32(a, i) SIMD16::srai_epi32<i>(a)119#define _simd16_fmadd_ps SIMD16::fmadd_ps120#define _simd16_fmsub_ps SIMD16::fmsub_ps121#define _simd16_adds_epu8 SIMD16::adds_epu8122#define _simd16_subs_epu8 SIMD16::subs_epu8123#define _simd16_add_epi8 SIMD16::add_epi8124#define _simd16_shuffle_epi8 SIMD16::shuffle_epi8125126#define _simd16_i32gather_ps(m, index, scale) \127SIMD16::i32gather_ps<SIMD16::ScaleFactor(scale)>(m, index)128#define _simd16_mask_i32gather_ps(a, m, index, mask, scale) \129SIMD16::mask_i32gather_ps<SIMD16::ScaleFactor(scale)>(a, m, index, mask)130131#define _simd16_abs_epi32 SIMD16::abs_epi32132133#define _simd16_cmpeq_epi64 SIMD16::cmpeq_epi64134#define _simd16_cmpgt_epi64 SIMD16::cmpgt_epi64135#define _simd16_cmpeq_epi16 SIMD16::cmpeq_epi16136#define _simd16_cmpgt_epi16 SIMD16::cmpgt_epi16137#define _simd16_cmpeq_epi8 SIMD16::cmpeq_epi8138#define _simd16_cmpgt_epi8 SIMD16::cmpgt_epi8139140#define _simd16_permute_ps_i(a, i) SIMD16::permute_ps<i>(a)141#define _simd16_permute_ps SIMD16::permute_ps142#define _simd16_permute_epi32 SIMD16::permute_epi32143#define _simd16_sllv_epi32 SIMD16::sllv_epi32144#define _simd16_srlv_epi32 SIMD16::sllv_epi32145#define _simd16_permute2f128_ps(a, b, i) SIMD16::permute2f128_ps<i>(a, b)146#define _simd16_permute2f128_pd(a, b, i) SIMD16::permute2f128_pd<i>(a, b)147#define _simd16_permute2f128_si(a, b, i) SIMD16::permute2f128_si<i>(a, b)148#define _simd16_shuffle_ps(a, b, i) SIMD16::shuffle_ps<i>(a, b)149#define _simd16_shuffle_pd(a, b, i) SIMD16::shuffle_pd<i>(a, b)150#define _simd16_shuffle_epi32(a, b, imm8) SIMD16::shuffle_epi32<imm8>(a, b)151#define _simd16_shuffle_epi64(a, b, imm8) SIMD16::shuffle_epi64<imm8>(a, b)152#define _simd16_cvtepu8_epi16 SIMD16::cvtepu8_epi16153#define _simd16_cvtepu8_epi32 SIMD16::cvtepu8_epi32154#define _simd16_cvtepu16_epi32 SIMD16::cvtepu16_epi32155#define _simd16_cvtepu16_epi64 SIMD16::cvtepu16_epi64156#define _simd16_cvtepu32_epi64 SIMD16::cvtepu32_epi64157#define _simd16_packus_epi16 SIMD16::packus_epi16158#define _simd16_packs_epi16 SIMD16::packs_epi16159#define _simd16_packus_epi32 SIMD16::packus_epi32160#define _simd16_packs_epi32 SIMD16::packs_epi32161#define _simd16_cmplt_ps_mask SIMD16::cmp_ps_mask<SIMD16::CompareType::LT_OQ>162#define _simd16_cmpeq_ps_mask SIMD16::cmp_ps_mask<SIMD16::CompareType::EQ_OQ>163#define _simd16_int2mask(mask) simd16mask(mask)164#define _simd16_mask2int(mask) int(mask)165#define _simd16_vmask_ps SIMD16::vmask_ps166167#endif //__SWR_SIMD16INTRIN_H_168169170