Path: blob/21.2-virgl/src/gallium/drivers/vc4/kernel/vc4_packet.h
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/*1* Copyright © 2014 Broadcom2*3* Permission is hereby granted, free of charge, to any person obtaining a4* copy of this software and associated documentation files (the "Software"),5* to deal in the Software without restriction, including without limitation6* the rights to use, copy, modify, merge, publish, distribute, sublicense,7* and/or sell copies of the Software, and to permit persons to whom the8* Software is furnished to do so, subject to the following conditions:9*10* The above copyright notice and this permission notice (including the next11* paragraph) shall be included in all copies or substantial portions of the12* Software.13*14* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER18* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING19* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS20* IN THE SOFTWARE.21*/2223#ifndef VC4_PACKET_H24#define VC4_PACKET_H2526enum vc4_packet {27VC4_PACKET_HALT = 0,28VC4_PACKET_NOP = 1,2930VC4_PACKET_FLUSH = 4,31VC4_PACKET_FLUSH_ALL = 5,32VC4_PACKET_START_TILE_BINNING = 6,33VC4_PACKET_INCREMENT_SEMAPHORE = 7,34VC4_PACKET_WAIT_ON_SEMAPHORE = 8,3536VC4_PACKET_BRANCH = 16,37VC4_PACKET_BRANCH_TO_SUB_LIST = 17,3839VC4_PACKET_STORE_MS_TILE_BUFFER = 24,40VC4_PACKET_STORE_MS_TILE_BUFFER_AND_EOF = 25,41VC4_PACKET_STORE_FULL_RES_TILE_BUFFER = 26,42VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER = 27,43VC4_PACKET_STORE_TILE_BUFFER_GENERAL = 28,44VC4_PACKET_LOAD_TILE_BUFFER_GENERAL = 29,4546VC4_PACKET_GL_INDEXED_PRIMITIVE = 32,47VC4_PACKET_GL_ARRAY_PRIMITIVE = 33,4849VC4_PACKET_COMPRESSED_PRIMITIVE = 48,50VC4_PACKET_CLIPPED_COMPRESSED_PRIMITIVE = 49,5152VC4_PACKET_PRIMITIVE_LIST_FORMAT = 56,5354VC4_PACKET_GL_SHADER_STATE = 64,55VC4_PACKET_NV_SHADER_STATE = 65,56VC4_PACKET_VG_SHADER_STATE = 66,5758VC4_PACKET_CONFIGURATION_BITS = 96,59VC4_PACKET_FLAT_SHADE_FLAGS = 97,60VC4_PACKET_POINT_SIZE = 98,61VC4_PACKET_LINE_WIDTH = 99,62VC4_PACKET_RHT_X_BOUNDARY = 100,63VC4_PACKET_DEPTH_OFFSET = 101,64VC4_PACKET_CLIP_WINDOW = 102,65VC4_PACKET_VIEWPORT_OFFSET = 103,66VC4_PACKET_Z_CLIPPING = 104,67VC4_PACKET_CLIPPER_XY_SCALING = 105,68VC4_PACKET_CLIPPER_Z_SCALING = 106,6970VC4_PACKET_TILE_BINNING_MODE_CONFIG = 112,71VC4_PACKET_TILE_RENDERING_MODE_CONFIG = 113,72VC4_PACKET_CLEAR_COLORS = 114,73VC4_PACKET_TILE_COORDINATES = 115,7475/* Not an actual hardware packet -- this is what we use to put76* references to GEM bos in the command stream, since we need the u3277* int the actual address packet in order to store the offset from the78* start of the BO.79*/80VC4_PACKET_GEM_HANDLES = 254,81} __attribute__ ((__packed__));8283#define VC4_PACKET_HALT_SIZE 184#define VC4_PACKET_NOP_SIZE 185#define VC4_PACKET_FLUSH_SIZE 186#define VC4_PACKET_FLUSH_ALL_SIZE 187#define VC4_PACKET_START_TILE_BINNING_SIZE 188#define VC4_PACKET_INCREMENT_SEMAPHORE_SIZE 189#define VC4_PACKET_WAIT_ON_SEMAPHORE_SIZE 190#define VC4_PACKET_BRANCH_SIZE 591#define VC4_PACKET_BRANCH_TO_SUB_LIST_SIZE 592#define VC4_PACKET_STORE_MS_TILE_BUFFER_SIZE 193#define VC4_PACKET_STORE_MS_TILE_BUFFER_AND_EOF_SIZE 194#define VC4_PACKET_STORE_FULL_RES_TILE_BUFFER_SIZE 595#define VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER_SIZE 596#define VC4_PACKET_STORE_TILE_BUFFER_GENERAL_SIZE 797#define VC4_PACKET_LOAD_TILE_BUFFER_GENERAL_SIZE 798#define VC4_PACKET_GL_INDEXED_PRIMITIVE_SIZE 1499#define VC4_PACKET_GL_ARRAY_PRIMITIVE_SIZE 10100#define VC4_PACKET_COMPRESSED_PRIMITIVE_SIZE 1101#define VC4_PACKET_CLIPPED_COMPRESSED_PRIMITIVE_SIZE 1102#define VC4_PACKET_PRIMITIVE_LIST_FORMAT_SIZE 2103#define VC4_PACKET_GL_SHADER_STATE_SIZE 5104#define VC4_PACKET_NV_SHADER_STATE_SIZE 5105#define VC4_PACKET_VG_SHADER_STATE_SIZE 5106#define VC4_PACKET_CONFIGURATION_BITS_SIZE 4107#define VC4_PACKET_FLAT_SHADE_FLAGS_SIZE 5108#define VC4_PACKET_POINT_SIZE_SIZE 5109#define VC4_PACKET_LINE_WIDTH_SIZE 5110#define VC4_PACKET_RHT_X_BOUNDARY_SIZE 3111#define VC4_PACKET_DEPTH_OFFSET_SIZE 5112#define VC4_PACKET_CLIP_WINDOW_SIZE 9113#define VC4_PACKET_VIEWPORT_OFFSET_SIZE 5114#define VC4_PACKET_Z_CLIPPING_SIZE 9115#define VC4_PACKET_CLIPPER_XY_SCALING_SIZE 9116#define VC4_PACKET_CLIPPER_Z_SCALING_SIZE 9117#define VC4_PACKET_TILE_BINNING_MODE_CONFIG_SIZE 16118#define VC4_PACKET_TILE_RENDERING_MODE_CONFIG_SIZE 11119#define VC4_PACKET_CLEAR_COLORS_SIZE 14120#define VC4_PACKET_TILE_COORDINATES_SIZE 3121#define VC4_PACKET_GEM_HANDLES_SIZE 9122123/* Number of multisamples supported. */124#define VC4_MAX_SAMPLES 4125/* Size of a full resolution color or Z tile buffer load/store. */126#define VC4_TILE_BUFFER_SIZE (64 * 64 * 4)127128#define VC4_MASK(high, low) (((1 << ((high) - (low) + 1)) - 1) << (low))129/* Using the GNU statement expression extension */130#define VC4_SET_FIELD(value, field) \131({ \132uint32_t fieldval = (value) << field ## _SHIFT; \133assert((fieldval & ~ field ## _MASK) == 0); \134fieldval & field ## _MASK; \135})136137#define VC4_GET_FIELD(word, field) (((word) & field ## _MASK) >> field ## _SHIFT)138139/** @{140* Bits used by packets like VC4_PACKET_STORE_TILE_BUFFER_GENERAL and141* VC4_PACKET_TILE_RENDERING_MODE_CONFIG.142*/143#define VC4_TILING_FORMAT_LINEAR 0144#define VC4_TILING_FORMAT_T 1145#define VC4_TILING_FORMAT_LT 2146/** @} */147148/** @{149*150* low bits of VC4_PACKET_STORE_FULL_RES_TILE_BUFFER and151* VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER.152*/153#define VC4_LOADSTORE_FULL_RES_EOF (1 << 3)154#define VC4_LOADSTORE_FULL_RES_DISABLE_CLEAR_ALL (1 << 2)155#define VC4_LOADSTORE_FULL_RES_DISABLE_ZS (1 << 1)156#define VC4_LOADSTORE_FULL_RES_DISABLE_COLOR (1 << 0)157158/** @{159*160* low bits of VC4_PACKET_STORE_FULL_RES_TILE_BUFFER and161* VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER.162*/163#define VC4_LOADSTORE_FULL_RES_EOF (1 << 3)164#define VC4_LOADSTORE_FULL_RES_DISABLE_CLEAR_ALL (1 << 2)165#define VC4_LOADSTORE_FULL_RES_DISABLE_ZS (1 << 1)166#define VC4_LOADSTORE_FULL_RES_DISABLE_COLOR (1 << 0)167168/** @{169*170* byte 2 of VC4_PACKET_STORE_TILE_BUFFER_GENERAL and171* VC4_PACKET_LOAD_TILE_BUFFER_GENERAL (low bits of the address)172*/173174#define VC4_LOADSTORE_TILE_BUFFER_EOF (1 << 3)175#define VC4_LOADSTORE_TILE_BUFFER_DISABLE_FULL_VG_MASK (1 << 2)176#define VC4_LOADSTORE_TILE_BUFFER_DISABLE_FULL_ZS (1 << 1)177#define VC4_LOADSTORE_TILE_BUFFER_DISABLE_FULL_COLOR (1 << 0)178179/** @} */180181/** @{182*183* byte 0-1 of VC4_PACKET_STORE_TILE_BUFFER_GENERAL and184* VC4_PACKET_LOAD_TILE_BUFFER_GENERAL185*/186#define VC4_STORE_TILE_BUFFER_DISABLE_VG_MASK_CLEAR (1 << 15)187#define VC4_STORE_TILE_BUFFER_DISABLE_ZS_CLEAR (1 << 14)188#define VC4_STORE_TILE_BUFFER_DISABLE_COLOR_CLEAR (1 << 13)189#define VC4_STORE_TILE_BUFFER_DISABLE_SWAP (1 << 12)190191#define VC4_LOADSTORE_TILE_BUFFER_FORMAT_MASK VC4_MASK(9, 8)192#define VC4_LOADSTORE_TILE_BUFFER_FORMAT_SHIFT 8193#define VC4_LOADSTORE_TILE_BUFFER_RGBA8888 0194#define VC4_LOADSTORE_TILE_BUFFER_BGR565_DITHER 1195#define VC4_LOADSTORE_TILE_BUFFER_BGR565 2196/** @} */197198/** @{199*200* byte 0 of VC4_PACKET_STORE_TILE_BUFFER_GENERAL and201* VC4_PACKET_LOAD_TILE_BUFFER_GENERAL202*/203#define VC4_STORE_TILE_BUFFER_MODE_MASK VC4_MASK(7, 6)204#define VC4_STORE_TILE_BUFFER_MODE_SHIFT 6205#define VC4_STORE_TILE_BUFFER_MODE_SAMPLE0 (0 << 6)206#define VC4_STORE_TILE_BUFFER_MODE_DECIMATE_X4 (1 << 6)207#define VC4_STORE_TILE_BUFFER_MODE_DECIMATE_X16 (2 << 6)208209/** The values of the field are VC4_TILING_FORMAT_* */210#define VC4_LOADSTORE_TILE_BUFFER_TILING_MASK VC4_MASK(5, 4)211#define VC4_LOADSTORE_TILE_BUFFER_TILING_SHIFT 4212213#define VC4_LOADSTORE_TILE_BUFFER_BUFFER_MASK VC4_MASK(2, 0)214#define VC4_LOADSTORE_TILE_BUFFER_BUFFER_SHIFT 0215#define VC4_LOADSTORE_TILE_BUFFER_NONE 0216#define VC4_LOADSTORE_TILE_BUFFER_COLOR 1217#define VC4_LOADSTORE_TILE_BUFFER_ZS 2218#define VC4_LOADSTORE_TILE_BUFFER_Z 3219#define VC4_LOADSTORE_TILE_BUFFER_VG_MASK 4220#define VC4_LOADSTORE_TILE_BUFFER_FULL 5221/** @} */222223#define VC4_INDEX_BUFFER_U8 (0 << 4)224#define VC4_INDEX_BUFFER_U16 (1 << 4)225226/* This flag is only present in NV shader state. */227#define VC4_SHADER_FLAG_SHADED_CLIP_COORDS (1 << 3)228#define VC4_SHADER_FLAG_ENABLE_CLIPPING (1 << 2)229#define VC4_SHADER_FLAG_VS_POINT_SIZE (1 << 1)230#define VC4_SHADER_FLAG_FS_SINGLE_THREAD (1 << 0)231232/** @{ byte 2 of config bits. */233#define VC4_CONFIG_BITS_EARLY_Z_UPDATE (1 << 1)234#define VC4_CONFIG_BITS_EARLY_Z (1 << 0)235/** @} */236237/** @{ byte 1 of config bits. */238#define VC4_CONFIG_BITS_Z_UPDATE (1 << 7)239/** same values in this 3-bit field as PIPE_FUNC_* */240#define VC4_CONFIG_BITS_DEPTH_FUNC_SHIFT 4241#define VC4_CONFIG_BITS_COVERAGE_READ_LEAVE (1 << 3)242243#define VC4_CONFIG_BITS_COVERAGE_UPDATE_NONZERO (0 << 1)244#define VC4_CONFIG_BITS_COVERAGE_UPDATE_ODD (1 << 1)245#define VC4_CONFIG_BITS_COVERAGE_UPDATE_OR (2 << 1)246#define VC4_CONFIG_BITS_COVERAGE_UPDATE_ZERO (3 << 1)247248#define VC4_CONFIG_BITS_COVERAGE_PIPE_SELECT (1 << 0)249/** @} */250251/** @{ byte 0 of config bits. */252#define VC4_CONFIG_BITS_RASTERIZER_OVERSAMPLE_NONE (0 << 6)253#define VC4_CONFIG_BITS_RASTERIZER_OVERSAMPLE_4X (1 << 6)254#define VC4_CONFIG_BITS_RASTERIZER_OVERSAMPLE_16X (2 << 6)255256#define VC4_CONFIG_BITS_AA_POINTS_AND_LINES (1 << 4)257#define VC4_CONFIG_BITS_ENABLE_DEPTH_OFFSET (1 << 3)258#define VC4_CONFIG_BITS_CW_PRIMITIVES (1 << 2)259#define VC4_CONFIG_BITS_ENABLE_PRIM_BACK (1 << 1)260#define VC4_CONFIG_BITS_ENABLE_PRIM_FRONT (1 << 0)261/** @} */262263/** @{ bits in the last u8 of VC4_PACKET_TILE_BINNING_MODE_CONFIG */264#define VC4_BIN_CONFIG_DB_NON_MS (1 << 7)265266#define VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_MASK VC4_MASK(6, 5)267#define VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_SHIFT 5268#define VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_32 0269#define VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_64 1270#define VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_128 2271#define VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_256 3272273#define VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_MASK VC4_MASK(4, 3)274#define VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_SHIFT 3275#define VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_32 0276#define VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_64 1277#define VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_128 2278#define VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_256 3279280#define VC4_BIN_CONFIG_AUTO_INIT_TSDA (1 << 2)281#define VC4_BIN_CONFIG_TILE_BUFFER_64BIT (1 << 1)282#define VC4_BIN_CONFIG_MS_MODE_4X (1 << 0)283/** @} */284285/** @{ bits in the last u16 of VC4_PACKET_TILE_RENDERING_MODE_CONFIG */286#define VC4_RENDER_CONFIG_DB_NON_MS (1 << 12)287#define VC4_RENDER_CONFIG_EARLY_Z_COVERAGE_DISABLE (1 << 11)288#define VC4_RENDER_CONFIG_EARLY_Z_DIRECTION_G (1 << 10)289#define VC4_RENDER_CONFIG_COVERAGE_MODE (1 << 9)290#define VC4_RENDER_CONFIG_ENABLE_VG_MASK (1 << 8)291292/** The values of the field are VC4_TILING_FORMAT_* */293#define VC4_RENDER_CONFIG_MEMORY_FORMAT_MASK VC4_MASK(7, 6)294#define VC4_RENDER_CONFIG_MEMORY_FORMAT_SHIFT 6295296#define VC4_RENDER_CONFIG_DECIMATE_MODE_1X (0 << 4)297#define VC4_RENDER_CONFIG_DECIMATE_MODE_4X (1 << 4)298#define VC4_RENDER_CONFIG_DECIMATE_MODE_16X (2 << 4)299300#define VC4_RENDER_CONFIG_FORMAT_MASK VC4_MASK(3, 2)301#define VC4_RENDER_CONFIG_FORMAT_SHIFT 2302#define VC4_RENDER_CONFIG_FORMAT_BGR565_DITHERED 0303#define VC4_RENDER_CONFIG_FORMAT_RGBA8888 1304#define VC4_RENDER_CONFIG_FORMAT_BGR565 2305306#define VC4_RENDER_CONFIG_TILE_BUFFER_64BIT (1 << 1)307#define VC4_RENDER_CONFIG_MS_MODE_4X (1 << 0)308309#define VC4_PRIMITIVE_LIST_FORMAT_16_INDEX (1 << 4)310#define VC4_PRIMITIVE_LIST_FORMAT_32_XY (3 << 4)311#define VC4_PRIMITIVE_LIST_FORMAT_TYPE_POINTS (0 << 0)312#define VC4_PRIMITIVE_LIST_FORMAT_TYPE_LINES (1 << 0)313#define VC4_PRIMITIVE_LIST_FORMAT_TYPE_TRIANGLES (2 << 0)314#define VC4_PRIMITIVE_LIST_FORMAT_TYPE_RHT (3 << 0)315316enum vc4_texture_data_type {317VC4_TEXTURE_TYPE_RGBA8888 = 0,318VC4_TEXTURE_TYPE_RGBX8888 = 1,319VC4_TEXTURE_TYPE_RGBA4444 = 2,320VC4_TEXTURE_TYPE_RGBA5551 = 3,321VC4_TEXTURE_TYPE_RGB565 = 4,322VC4_TEXTURE_TYPE_LUMINANCE = 5,323VC4_TEXTURE_TYPE_ALPHA = 6,324VC4_TEXTURE_TYPE_LUMALPHA = 7,325VC4_TEXTURE_TYPE_ETC1 = 8,326VC4_TEXTURE_TYPE_S16F = 9,327VC4_TEXTURE_TYPE_S8 = 10,328VC4_TEXTURE_TYPE_S16 = 11,329VC4_TEXTURE_TYPE_BW1 = 12,330VC4_TEXTURE_TYPE_A4 = 13,331VC4_TEXTURE_TYPE_A1 = 14,332VC4_TEXTURE_TYPE_RGBA64 = 15,333VC4_TEXTURE_TYPE_RGBA32R = 16,334VC4_TEXTURE_TYPE_YUV422R = 17,335};336337#define VC4_TEX_P0_OFFSET_MASK VC4_MASK(31, 12)338#define VC4_TEX_P0_OFFSET_SHIFT 12339#define VC4_TEX_P0_CSWIZ_MASK VC4_MASK(11, 10)340#define VC4_TEX_P0_CSWIZ_SHIFT 10341#define VC4_TEX_P0_CMMODE_MASK VC4_MASK(9, 9)342#define VC4_TEX_P0_CMMODE_SHIFT 9343#define VC4_TEX_P0_FLIPY_MASK VC4_MASK(8, 8)344#define VC4_TEX_P0_FLIPY_SHIFT 8345#define VC4_TEX_P0_TYPE_MASK VC4_MASK(7, 4)346#define VC4_TEX_P0_TYPE_SHIFT 4347#define VC4_TEX_P0_MIPLVLS_MASK VC4_MASK(3, 0)348#define VC4_TEX_P0_MIPLVLS_SHIFT 0349350#define VC4_TEX_P1_TYPE4_MASK VC4_MASK(31, 31)351#define VC4_TEX_P1_TYPE4_SHIFT 31352#define VC4_TEX_P1_HEIGHT_MASK VC4_MASK(30, 20)353#define VC4_TEX_P1_HEIGHT_SHIFT 20354#define VC4_TEX_P1_ETCFLIP_MASK VC4_MASK(19, 19)355#define VC4_TEX_P1_ETCFLIP_SHIFT 19356#define VC4_TEX_P1_WIDTH_MASK VC4_MASK(18, 8)357#define VC4_TEX_P1_WIDTH_SHIFT 8358359#define VC4_TEX_P1_MAGFILT_MASK VC4_MASK(7, 7)360#define VC4_TEX_P1_MAGFILT_SHIFT 7361# define VC4_TEX_P1_MAGFILT_LINEAR 0362# define VC4_TEX_P1_MAGFILT_NEAREST 1363364#define VC4_TEX_P1_MINFILT_MASK VC4_MASK(6, 4)365#define VC4_TEX_P1_MINFILT_SHIFT 4366# define VC4_TEX_P1_MINFILT_LINEAR 0367# define VC4_TEX_P1_MINFILT_NEAREST 1368# define VC4_TEX_P1_MINFILT_NEAR_MIP_NEAR 2369# define VC4_TEX_P1_MINFILT_NEAR_MIP_LIN 3370# define VC4_TEX_P1_MINFILT_LIN_MIP_NEAR 4371# define VC4_TEX_P1_MINFILT_LIN_MIP_LIN 5372373#define VC4_TEX_P1_WRAP_T_MASK VC4_MASK(3, 2)374#define VC4_TEX_P1_WRAP_T_SHIFT 2375#define VC4_TEX_P1_WRAP_S_MASK VC4_MASK(1, 0)376#define VC4_TEX_P1_WRAP_S_SHIFT 0377# define VC4_TEX_P1_WRAP_REPEAT 0378# define VC4_TEX_P1_WRAP_CLAMP 1379# define VC4_TEX_P1_WRAP_MIRROR 2380# define VC4_TEX_P1_WRAP_BORDER 3381382#define VC4_TEX_P2_PTYPE_MASK VC4_MASK(31, 30)383#define VC4_TEX_P2_PTYPE_SHIFT 30384# define VC4_TEX_P2_PTYPE_IGNORED 0385# define VC4_TEX_P2_PTYPE_CUBE_MAP_STRIDE 1386# define VC4_TEX_P2_PTYPE_CHILD_IMAGE_DIMENSIONS 2387# define VC4_TEX_P2_PTYPE_CHILD_IMAGE_OFFSETS 3388389/* VC4_TEX_P2_PTYPE_CUBE_MAP_STRIDE bits */390#define VC4_TEX_P2_CMST_MASK VC4_MASK(29, 12)391#define VC4_TEX_P2_CMST_SHIFT 12392#define VC4_TEX_P2_BSLOD_MASK VC4_MASK(0, 0)393#define VC4_TEX_P2_BSLOD_SHIFT 0394395/* VC4_TEX_P2_PTYPE_CHILD_IMAGE_DIMENSIONS */396#define VC4_TEX_P2_CHEIGHT_MASK VC4_MASK(22, 12)397#define VC4_TEX_P2_CHEIGHT_SHIFT 12398#define VC4_TEX_P2_CWIDTH_MASK VC4_MASK(10, 0)399#define VC4_TEX_P2_CWIDTH_SHIFT 0400401/* VC4_TEX_P2_PTYPE_CHILD_IMAGE_OFFSETS */402#define VC4_TEX_P2_CYOFF_MASK VC4_MASK(22, 12)403#define VC4_TEX_P2_CYOFF_SHIFT 12404#define VC4_TEX_P2_CXOFF_MASK VC4_MASK(10, 0)405#define VC4_TEX_P2_CXOFF_SHIFT 0406407#endif /* VC4_PACKET_H */408409410