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PojavLauncherTeam
GitHub Repository: PojavLauncherTeam/mesa
Path: blob/21.2-virgl/src/gallium/drivers/vc4/vc4_screen.c
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/*
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* Copyright © 2014 Broadcom
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* Copyright (C) 2012 Rob Clark <[email protected]>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "util/os_misc.h"
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#include "pipe/p_defines.h"
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#include "pipe/p_screen.h"
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#include "pipe/p_state.h"
29
30
#include "util/u_cpu_detect.h"
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#include "util/u_debug.h"
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#include "util/u_memory.h"
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#include "util/format/u_format.h"
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#include "util/u_hash_table.h"
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#include "util/u_screen.h"
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#include "util/u_transfer_helper.h"
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#include "util/ralloc.h"
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#include <xf86drm.h>
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#include "drm-uapi/drm_fourcc.h"
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#include "drm-uapi/vc4_drm.h"
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#include "vc4_screen.h"
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#include "vc4_context.h"
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#include "vc4_resource.h"
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46
static const struct debug_named_value vc4_debug_options[] = {
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{ "cl", VC4_DEBUG_CL,
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"Dump command list during creation" },
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{ "surf", VC4_DEBUG_SURFACE,
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"Dump surface layouts" },
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{ "qpu", VC4_DEBUG_QPU,
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"Dump generated QPU instructions" },
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{ "qir", VC4_DEBUG_QIR,
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"Dump QPU IR during program compile" },
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{ "nir", VC4_DEBUG_NIR,
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"Dump NIR during program compile" },
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{ "tgsi", VC4_DEBUG_TGSI,
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"Dump TGSI during program compile" },
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{ "shaderdb", VC4_DEBUG_SHADERDB,
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"Dump program compile information for shader-db analysis" },
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{ "perf", VC4_DEBUG_PERF,
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"Print during performance-related events" },
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{ "norast", VC4_DEBUG_NORAST,
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"Skip actual hardware execution of commands" },
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{ "always_flush", VC4_DEBUG_ALWAYS_FLUSH,
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"Flush after each draw call" },
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{ "always_sync", VC4_DEBUG_ALWAYS_SYNC,
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"Wait for finish after each flush" },
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#ifdef USE_VC4_SIMULATOR
70
{ "dump", VC4_DEBUG_DUMP,
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"Write a GPU command stream trace file" },
72
#endif
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{ NULL }
74
};
75
76
DEBUG_GET_ONCE_FLAGS_OPTION(vc4_debug, "VC4_DEBUG", vc4_debug_options, 0)
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uint32_t vc4_debug;
78
79
static const char *
80
vc4_screen_get_name(struct pipe_screen *pscreen)
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{
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struct vc4_screen *screen = vc4_screen(pscreen);
83
84
if (!screen->name) {
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screen->name = ralloc_asprintf(screen,
86
"VC4 V3D %d.%d",
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screen->v3d_ver / 10,
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screen->v3d_ver % 10);
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}
90
91
return screen->name;
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}
93
94
static const char *
95
vc4_screen_get_vendor(struct pipe_screen *pscreen)
96
{
97
return "Broadcom";
98
}
99
100
static void
101
vc4_screen_destroy(struct pipe_screen *pscreen)
102
{
103
struct vc4_screen *screen = vc4_screen(pscreen);
104
105
_mesa_hash_table_destroy(screen->bo_handles, NULL);
106
vc4_bufmgr_destroy(pscreen);
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slab_destroy_parent(&screen->transfer_pool);
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if (screen->ro)
109
screen->ro->destroy(screen->ro);
110
111
#ifdef USE_VC4_SIMULATOR
112
vc4_simulator_destroy(screen);
113
#endif
114
115
u_transfer_helper_destroy(pscreen->transfer_helper);
116
117
close(screen->fd);
118
ralloc_free(pscreen);
119
}
120
121
static bool
122
vc4_has_feature(struct vc4_screen *screen, uint32_t feature)
123
{
124
struct drm_vc4_get_param p = {
125
.param = feature,
126
};
127
int ret = vc4_ioctl(screen->fd, DRM_IOCTL_VC4_GET_PARAM, &p);
128
129
if (ret != 0)
130
return false;
131
132
return p.value;
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}
134
135
static int
136
vc4_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
137
{
138
struct vc4_screen *screen = vc4_screen(pscreen);
139
140
switch (param) {
141
/* Supported features (boolean caps). */
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case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
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case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
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case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
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case PIPE_CAP_NPOT_TEXTURES:
146
case PIPE_CAP_BLEND_EQUATION_SEPARATE:
147
case PIPE_CAP_TEXTURE_MULTISAMPLE:
148
case PIPE_CAP_TEXTURE_SWIZZLE:
149
case PIPE_CAP_TEXTURE_BARRIER:
150
case PIPE_CAP_TGSI_TEXCOORD:
151
return 1;
152
153
case PIPE_CAP_NATIVE_FENCE_FD:
154
return screen->has_syncobj;
155
156
case PIPE_CAP_TILE_RASTER_ORDER:
157
return vc4_has_feature(screen,
158
DRM_VC4_PARAM_SUPPORTS_FIXED_RCL_ORDER);
159
160
/* lying for GL 2.0 */
161
case PIPE_CAP_OCCLUSION_QUERY:
162
case PIPE_CAP_POINT_SPRITE:
163
return 1;
164
165
case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
166
case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
167
case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
168
return 1;
169
170
case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
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case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
172
return 1;
173
174
/* Texturing. */
175
case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
176
return 2048;
177
case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
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return VC4_MAX_MIP_LEVELS;
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case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
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/* Note: Not supported in hardware, just faking it. */
181
return 5;
182
183
case PIPE_CAP_MAX_VARYINGS:
184
return 8;
185
186
case PIPE_CAP_VENDOR_ID:
187
return 0x14E4;
188
case PIPE_CAP_ACCELERATED:
189
return 1;
190
case PIPE_CAP_VIDEO_MEMORY: {
191
uint64_t system_memory;
192
193
if (!os_get_total_physical_memory(&system_memory))
194
return 0;
195
196
return (int)(system_memory >> 20);
197
}
198
case PIPE_CAP_UMA:
199
return 1;
200
201
case PIPE_CAP_ALPHA_TEST:
202
case PIPE_CAP_VERTEX_COLOR_CLAMPED:
203
case PIPE_CAP_TWO_SIDED_COLOR:
204
case PIPE_CAP_TEXRECT:
205
return 0;
206
207
default:
208
return u_pipe_screen_get_param_defaults(pscreen, param);
209
}
210
}
211
212
static float
213
vc4_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
214
{
215
switch (param) {
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case PIPE_CAPF_MAX_LINE_WIDTH:
217
case PIPE_CAPF_MAX_LINE_WIDTH_AA:
218
return 32;
219
220
case PIPE_CAPF_MAX_POINT_WIDTH:
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case PIPE_CAPF_MAX_POINT_WIDTH_AA:
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return 512.0f;
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case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
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return 0.0f;
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case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
227
return 0.0f;
228
229
case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
230
case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
231
case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
232
return 0.0f;
233
default:
234
fprintf(stderr, "unknown paramf %d\n", param);
235
return 0;
236
}
237
}
238
239
static int
240
vc4_screen_get_shader_param(struct pipe_screen *pscreen,
241
enum pipe_shader_type shader,
242
enum pipe_shader_cap param)
243
{
244
if (shader != PIPE_SHADER_VERTEX &&
245
shader != PIPE_SHADER_FRAGMENT) {
246
return 0;
247
}
248
249
/* this is probably not totally correct.. but it's a start: */
250
switch (param) {
251
case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
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case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
253
case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
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case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
255
return 16384;
256
257
case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
258
return vc4_screen(pscreen)->has_control_flow;
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case PIPE_SHADER_CAP_MAX_INPUTS:
261
return 8;
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case PIPE_SHADER_CAP_MAX_OUTPUTS:
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return shader == PIPE_SHADER_FRAGMENT ? 1 : 8;
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case PIPE_SHADER_CAP_MAX_TEMPS:
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return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
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case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
267
return 16 * 1024 * sizeof(float);
268
case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
269
return 1;
270
case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
271
return 0;
272
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
273
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
274
case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
275
return 0;
276
case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
277
return 1;
278
case PIPE_SHADER_CAP_SUBROUTINES:
279
return 0;
280
case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
281
return 0;
282
case PIPE_SHADER_CAP_INTEGERS:
283
return 1;
284
case PIPE_SHADER_CAP_INT64_ATOMICS:
285
case PIPE_SHADER_CAP_FP16:
286
case PIPE_SHADER_CAP_FP16_DERIVATIVES:
287
case PIPE_SHADER_CAP_FP16_CONST_BUFFERS:
288
case PIPE_SHADER_CAP_INT16:
289
case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
290
case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
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case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
292
case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
293
case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
294
case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
295
return 0;
296
case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
297
case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
298
return VC4_MAX_TEXTURE_SAMPLERS;
299
case PIPE_SHADER_CAP_PREFERRED_IR:
300
return PIPE_SHADER_IR_NIR;
301
case PIPE_SHADER_CAP_SUPPORTED_IRS:
302
return 1 << PIPE_SHADER_IR_NIR;
303
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
304
return 32;
305
case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
306
case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
307
case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
308
case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
309
case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
310
case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
311
return 0;
312
default:
313
fprintf(stderr, "unknown shader param %d\n", param);
314
return 0;
315
}
316
return 0;
317
}
318
319
static bool
320
vc4_screen_is_format_supported(struct pipe_screen *pscreen,
321
enum pipe_format format,
322
enum pipe_texture_target target,
323
unsigned sample_count,
324
unsigned storage_sample_count,
325
unsigned usage)
326
{
327
struct vc4_screen *screen = vc4_screen(pscreen);
328
329
if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
330
return false;
331
332
if (sample_count > 1 && sample_count != VC4_MAX_SAMPLES)
333
return false;
334
335
if (target >= PIPE_MAX_TEXTURE_TYPES) {
336
return false;
337
}
338
339
if (usage & PIPE_BIND_VERTEX_BUFFER) {
340
switch (format) {
341
case PIPE_FORMAT_R32G32B32A32_FLOAT:
342
case PIPE_FORMAT_R32G32B32_FLOAT:
343
case PIPE_FORMAT_R32G32_FLOAT:
344
case PIPE_FORMAT_R32_FLOAT:
345
case PIPE_FORMAT_R32G32B32A32_SNORM:
346
case PIPE_FORMAT_R32G32B32_SNORM:
347
case PIPE_FORMAT_R32G32_SNORM:
348
case PIPE_FORMAT_R32_SNORM:
349
case PIPE_FORMAT_R32G32B32A32_SSCALED:
350
case PIPE_FORMAT_R32G32B32_SSCALED:
351
case PIPE_FORMAT_R32G32_SSCALED:
352
case PIPE_FORMAT_R32_SSCALED:
353
case PIPE_FORMAT_R16G16B16A16_UNORM:
354
case PIPE_FORMAT_R16G16B16_UNORM:
355
case PIPE_FORMAT_R16G16_UNORM:
356
case PIPE_FORMAT_R16_UNORM:
357
case PIPE_FORMAT_R16G16B16A16_SNORM:
358
case PIPE_FORMAT_R16G16B16_SNORM:
359
case PIPE_FORMAT_R16G16_SNORM:
360
case PIPE_FORMAT_R16_SNORM:
361
case PIPE_FORMAT_R16G16B16A16_USCALED:
362
case PIPE_FORMAT_R16G16B16_USCALED:
363
case PIPE_FORMAT_R16G16_USCALED:
364
case PIPE_FORMAT_R16_USCALED:
365
case PIPE_FORMAT_R16G16B16A16_SSCALED:
366
case PIPE_FORMAT_R16G16B16_SSCALED:
367
case PIPE_FORMAT_R16G16_SSCALED:
368
case PIPE_FORMAT_R16_SSCALED:
369
case PIPE_FORMAT_R8G8B8A8_UNORM:
370
case PIPE_FORMAT_R8G8B8_UNORM:
371
case PIPE_FORMAT_R8G8_UNORM:
372
case PIPE_FORMAT_R8_UNORM:
373
case PIPE_FORMAT_R8G8B8A8_SNORM:
374
case PIPE_FORMAT_R8G8B8_SNORM:
375
case PIPE_FORMAT_R8G8_SNORM:
376
case PIPE_FORMAT_R8_SNORM:
377
case PIPE_FORMAT_R8G8B8A8_USCALED:
378
case PIPE_FORMAT_R8G8B8_USCALED:
379
case PIPE_FORMAT_R8G8_USCALED:
380
case PIPE_FORMAT_R8_USCALED:
381
case PIPE_FORMAT_R8G8B8A8_SSCALED:
382
case PIPE_FORMAT_R8G8B8_SSCALED:
383
case PIPE_FORMAT_R8G8_SSCALED:
384
case PIPE_FORMAT_R8_SSCALED:
385
break;
386
default:
387
return false;
388
}
389
}
390
391
if ((usage & PIPE_BIND_RENDER_TARGET) &&
392
!vc4_rt_format_supported(format)) {
393
return false;
394
}
395
396
if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
397
(!vc4_tex_format_supported(format) ||
398
(format == PIPE_FORMAT_ETC1_RGB8 && !screen->has_etc1))) {
399
return false;
400
}
401
402
if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
403
format != PIPE_FORMAT_S8_UINT_Z24_UNORM &&
404
format != PIPE_FORMAT_X8Z24_UNORM) {
405
return false;
406
}
407
408
if ((usage & PIPE_BIND_INDEX_BUFFER) &&
409
format != PIPE_FORMAT_R8_UINT &&
410
format != PIPE_FORMAT_R16_UINT) {
411
return false;
412
}
413
414
return true;
415
}
416
417
static const uint64_t *vc4_get_modifiers(struct pipe_screen *pscreen, int *num)
418
{
419
struct vc4_screen *screen = vc4_screen(pscreen);
420
static const uint64_t all_modifiers[] = {
421
DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED,
422
DRM_FORMAT_MOD_LINEAR,
423
};
424
int m;
425
426
/* We support both modifiers (tiled and linear) for all sampler
427
* formats, but if we don't have the DRM_VC4_GET_TILING ioctl
428
* we shouldn't advertise the tiled formats.
429
*/
430
if (screen->has_tiling_ioctl) {
431
m = 0;
432
*num = 2;
433
} else{
434
m = 1;
435
*num = 1;
436
}
437
438
return &all_modifiers[m];
439
}
440
441
static void
442
vc4_screen_query_dmabuf_modifiers(struct pipe_screen *pscreen,
443
enum pipe_format format, int max,
444
uint64_t *modifiers,
445
unsigned int *external_only,
446
int *count)
447
{
448
const uint64_t *available_modifiers;
449
int i;
450
bool tex_will_lower;
451
int num_modifiers;
452
453
available_modifiers = vc4_get_modifiers(pscreen, &num_modifiers);
454
455
if (!modifiers) {
456
*count = num_modifiers;
457
return;
458
}
459
460
*count = MIN2(max, num_modifiers);
461
tex_will_lower = !vc4_tex_format_supported(format);
462
for (i = 0; i < *count; i++) {
463
modifiers[i] = available_modifiers[i];
464
if (external_only)
465
external_only[i] = tex_will_lower;
466
}
467
}
468
469
static bool
470
vc4_screen_is_dmabuf_modifier_supported(struct pipe_screen *pscreen,
471
uint64_t modifier,
472
enum pipe_format format,
473
bool *external_only)
474
{
475
const uint64_t *available_modifiers;
476
int i, num_modifiers;
477
478
available_modifiers = vc4_get_modifiers(pscreen, &num_modifiers);
479
480
for (i = 0; i < num_modifiers; i++) {
481
if (modifier == available_modifiers[i]) {
482
if (external_only)
483
*external_only = !vc4_tex_format_supported(format);
484
485
return true;
486
}
487
}
488
489
return false;
490
}
491
492
static bool
493
vc4_get_chip_info(struct vc4_screen *screen)
494
{
495
struct drm_vc4_get_param ident0 = {
496
.param = DRM_VC4_PARAM_V3D_IDENT0,
497
};
498
struct drm_vc4_get_param ident1 = {
499
.param = DRM_VC4_PARAM_V3D_IDENT1,
500
};
501
int ret;
502
503
ret = vc4_ioctl(screen->fd, DRM_IOCTL_VC4_GET_PARAM, &ident0);
504
if (ret != 0) {
505
if (errno == EINVAL) {
506
/* Backwards compatibility with 2835 kernels which
507
* only do V3D 2.1.
508
*/
509
screen->v3d_ver = 21;
510
return true;
511
} else {
512
fprintf(stderr, "Couldn't get V3D IDENT0: %s\n",
513
strerror(errno));
514
return false;
515
}
516
}
517
ret = vc4_ioctl(screen->fd, DRM_IOCTL_VC4_GET_PARAM, &ident1);
518
if (ret != 0) {
519
fprintf(stderr, "Couldn't get V3D IDENT1: %s\n",
520
strerror(errno));
521
return false;
522
}
523
524
uint32_t major = (ident0.value >> 24) & 0xff;
525
uint32_t minor = (ident1.value >> 0) & 0xf;
526
screen->v3d_ver = major * 10 + minor;
527
528
if (screen->v3d_ver != 21 && screen->v3d_ver != 26) {
529
fprintf(stderr,
530
"V3D %d.%d not supported by this version of Mesa.\n",
531
screen->v3d_ver / 10,
532
screen->v3d_ver % 10);
533
return false;
534
}
535
536
return true;
537
}
538
539
struct pipe_screen *
540
vc4_screen_create(int fd, struct renderonly *ro)
541
{
542
struct vc4_screen *screen = rzalloc(NULL, struct vc4_screen);
543
uint64_t syncobj_cap = 0;
544
struct pipe_screen *pscreen;
545
int err;
546
547
pscreen = &screen->base;
548
549
pscreen->destroy = vc4_screen_destroy;
550
pscreen->get_param = vc4_screen_get_param;
551
pscreen->get_paramf = vc4_screen_get_paramf;
552
pscreen->get_shader_param = vc4_screen_get_shader_param;
553
pscreen->context_create = vc4_context_create;
554
pscreen->is_format_supported = vc4_screen_is_format_supported;
555
556
screen->fd = fd;
557
screen->ro = ro;
558
559
list_inithead(&screen->bo_cache.time_list);
560
(void) mtx_init(&screen->bo_handles_mutex, mtx_plain);
561
screen->bo_handles = util_hash_table_create_ptr_keys();
562
563
screen->has_control_flow =
564
vc4_has_feature(screen, DRM_VC4_PARAM_SUPPORTS_BRANCHES);
565
screen->has_etc1 =
566
vc4_has_feature(screen, DRM_VC4_PARAM_SUPPORTS_ETC1);
567
screen->has_threaded_fs =
568
vc4_has_feature(screen, DRM_VC4_PARAM_SUPPORTS_THREADED_FS);
569
screen->has_madvise =
570
vc4_has_feature(screen, DRM_VC4_PARAM_SUPPORTS_MADVISE);
571
screen->has_perfmon_ioctl =
572
vc4_has_feature(screen, DRM_VC4_PARAM_SUPPORTS_PERFMON);
573
574
err = drmGetCap(fd, DRM_CAP_SYNCOBJ, &syncobj_cap);
575
if (err == 0 && syncobj_cap)
576
screen->has_syncobj = true;
577
578
if (!vc4_get_chip_info(screen))
579
goto fail;
580
581
util_cpu_detect();
582
583
slab_create_parent(&screen->transfer_pool, sizeof(struct vc4_transfer), 16);
584
585
vc4_fence_screen_init(screen);
586
587
vc4_debug = debug_get_option_vc4_debug();
588
if (vc4_debug & VC4_DEBUG_SHADERDB)
589
vc4_debug |= VC4_DEBUG_NORAST;
590
591
#ifdef USE_VC4_SIMULATOR
592
vc4_simulator_init(screen);
593
#endif
594
595
vc4_resource_screen_init(pscreen);
596
597
pscreen->get_name = vc4_screen_get_name;
598
pscreen->get_vendor = vc4_screen_get_vendor;
599
pscreen->get_device_vendor = vc4_screen_get_vendor;
600
pscreen->get_compiler_options = vc4_screen_get_compiler_options;
601
pscreen->query_dmabuf_modifiers = vc4_screen_query_dmabuf_modifiers;
602
pscreen->is_dmabuf_modifier_supported = vc4_screen_is_dmabuf_modifier_supported;
603
604
if (screen->has_perfmon_ioctl) {
605
pscreen->get_driver_query_group_info = vc4_get_driver_query_group_info;
606
pscreen->get_driver_query_info = vc4_get_driver_query_info;
607
}
608
609
return pscreen;
610
611
fail:
612
close(fd);
613
ralloc_free(pscreen);
614
return NULL;
615
}
616
617