CoCalc -- virgl

GitHub Repository: PojavLauncherTeam/mesa
Path: blob/21.2-virgl/src/gallium/drivers/virgl/virgl_screen.c
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/*
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 * Copyright 2014, 2015 Red Hat.
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a
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 * copy of this software and associated documentation files (the "Software"),
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 * to deal in the Software without restriction, including without limitation
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 * on the rights to use, copy, modify, merge, publish, distribute, sub
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 * license, and/or sell copies of the Software, and to permit persons to whom
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 * the Software is furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice (including the next
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 * paragraph) shall be included in all copies or substantial portions of the
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 * Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
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 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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 * USE OR OTHER DEALINGS IN THE SOFTWARE.
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 */
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#include "util/u_memory.h"
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#include "util/format/u_format.h"
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#include "util/format/u_format_s3tc.h"
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#include "util/u_screen.h"
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#include "util/u_video.h"
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#include "util/u_math.h"
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#include "util/u_inlines.h"
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#include "util/os_time.h"
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#include "util/xmlconfig.h"
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#include "pipe/p_defines.h"
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#include "pipe/p_screen.h"
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#include "tgsi/tgsi_exec.h"
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#include "virgl_screen.h"
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#include "virgl_resource.h"
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#include "virgl_public.h"
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#include "virgl_context.h"
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#include "virtio-gpu/virgl_protocol.h"
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#include "virgl_encode.h"
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int virgl_debug = 0;
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static const struct debug_named_value virgl_debug_options[] = {
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   { "verbose",   VIRGL_DEBUG_VERBOSE,             NULL },
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   { "tgsi",      VIRGL_DEBUG_TGSI,                NULL },
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   { "noemubgra", VIRGL_DEBUG_NO_EMULATE_BGRA,     "Disable tweak to emulate BGRA as RGBA on GLES hosts"},
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   { "nobgraswz", VIRGL_DEBUG_NO_BGRA_DEST_SWIZZLE,"Disable tweak to swizzle emulated BGRA on GLES hosts" },
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   { "sync",      VIRGL_DEBUG_SYNC,                "Sync after every flush" },
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   { "xfer",      VIRGL_DEBUG_XFER,                "Do not optimize for transfers" },
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   DEBUG_NAMED_VALUE_END
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};
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DEBUG_GET_ONCE_FLAGS_OPTION(virgl_debug, "VIRGL_DEBUG", virgl_debug_options, 0)
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static const char *
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virgl_get_vendor(struct pipe_screen *screen)
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{
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   return "Mesa/X.org";
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}
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62

63
static const char *
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virgl_get_name(struct pipe_screen *screen)
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{
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   struct virgl_screen *vscreen = virgl_screen(screen);
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   if (vscreen->caps.caps.v2.host_feature_check_version >= 5)
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      return vscreen->caps.caps.v2.renderer;
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   return "virgl";
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}
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static int
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virgl_get_param(struct pipe_screen *screen, enum pipe_cap param)
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{
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   struct virgl_screen *vscreen = virgl_screen(screen);
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   switch (param) {
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   case PIPE_CAP_NPOT_TEXTURES:
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      return 1;
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   case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
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   case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
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   case PIPE_CAP_VERTEX_SHADER_SATURATE:
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      return 1;
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   case PIPE_CAP_ANISOTROPIC_FILTER:
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      return 0;
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   case PIPE_CAP_POINT_SPRITE:
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      return 1;
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   case PIPE_CAP_MAX_RENDER_TARGETS:
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      return vscreen->caps.caps.v1.max_render_targets;
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   case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
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      return vscreen->caps.caps.v1.max_dual_source_render_targets;
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   case PIPE_CAP_OCCLUSION_QUERY:
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      return vscreen->caps.caps.v1.bset.occlusion_query;
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   case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
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   case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
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      return vscreen->caps.caps.v1.bset.mirror_clamp;
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   case PIPE_CAP_TEXTURE_SWIZZLE:
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      return 1;
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   case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
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      if (vscreen->caps.caps.v2.max_texture_2d_size)
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         return vscreen->caps.caps.v2.max_texture_2d_size;
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      return 16384;
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   case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
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      if (vscreen->caps.caps.v2.max_texture_3d_size)
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         return 1 + util_logbase2(vscreen->caps.caps.v2.max_texture_3d_size);
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      return 9; /* 256 x 256 x 256 */
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   case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
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      if (vscreen->caps.caps.v2.max_texture_cube_size)
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         return 1 + util_logbase2(vscreen->caps.caps.v2.max_texture_cube_size);
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      return 13; /* 4K x 4K */
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   case PIPE_CAP_BLEND_EQUATION_SEPARATE:
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      return 1;
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   case PIPE_CAP_INDEP_BLEND_ENABLE:
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      return vscreen->caps.caps.v1.bset.indep_blend_enable;
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   case PIPE_CAP_INDEP_BLEND_FUNC:
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      return vscreen->caps.caps.v1.bset.indep_blend_func;
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   case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
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   case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
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   case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
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      return 1;
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   case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
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      return vscreen->caps.caps.v1.bset.fragment_coord_conventions;
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   case PIPE_CAP_DEPTH_CLIP_DISABLE:
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      if (vscreen->caps.caps.v1.bset.depth_clip_disable)
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         return 1;
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      if (vscreen->caps.caps.v2.host_feature_check_version >= 3)
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         return 2;
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      return 0;
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   case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
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      return vscreen->caps.caps.v1.max_streamout_buffers;
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   case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
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   case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
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      return 16*4;
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   case PIPE_CAP_PRIMITIVE_RESTART:
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   case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX:
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      return vscreen->caps.caps.v1.bset.primitive_restart;
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   case PIPE_CAP_SHADER_STENCIL_EXPORT:
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      return vscreen->caps.caps.v1.bset.shader_stencil_export;
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   case PIPE_CAP_TGSI_INSTANCEID:
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   case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
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      return 1;
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   case PIPE_CAP_SEAMLESS_CUBE_MAP:
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      return vscreen->caps.caps.v1.bset.seamless_cube_map;
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   case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
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      return vscreen->caps.caps.v1.bset.seamless_cube_map_per_texture;
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   case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
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      return vscreen->caps.caps.v1.max_texture_array_layers;
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   case PIPE_CAP_MIN_TEXEL_OFFSET:
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      return vscreen->caps.caps.v2.min_texel_offset;
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   case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
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      return vscreen->caps.caps.v2.min_texture_gather_offset;
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   case PIPE_CAP_MAX_TEXEL_OFFSET:
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      return vscreen->caps.caps.v2.max_texel_offset;
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   case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
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      return vscreen->caps.caps.v2.max_texture_gather_offset;
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   case PIPE_CAP_CONDITIONAL_RENDER:
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      return vscreen->caps.caps.v1.bset.conditional_render;
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   case PIPE_CAP_TEXTURE_BARRIER:
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      return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_TEXTURE_BARRIER;
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   case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
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      return 1;
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   case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
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   case PIPE_CAP_VERTEX_COLOR_CLAMPED:
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      return vscreen->caps.caps.v1.bset.color_clamping;
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   case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
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      return (vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_FBO_MIXED_COLOR_FORMATS) ||
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            (vscreen->caps.caps.v2.host_feature_check_version < 1);
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   case PIPE_CAP_GLSL_FEATURE_LEVEL:
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      return vscreen->caps.caps.v1.glsl_level;
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   case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
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      return MIN2(vscreen->caps.caps.v1.glsl_level, 140);
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   case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
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   case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
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      return 0;
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   case PIPE_CAP_COMPUTE:
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      return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_COMPUTE_SHADER;
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   case PIPE_CAP_USER_VERTEX_BUFFERS:
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      return 0;
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   case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
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      return vscreen->caps.caps.v2.uniform_buffer_offset_alignment;
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   case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
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   case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
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      return vscreen->caps.caps.v1.bset.streamout_pause_resume;
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   case PIPE_CAP_START_INSTANCE:
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      return vscreen->caps.caps.v1.bset.start_instance;
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   case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
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   case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
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   case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
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   case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
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   case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
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      return 0;
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   case PIPE_CAP_QUERY_TIMESTAMP:
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      return 1;
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   case PIPE_CAP_QUERY_TIME_ELAPSED:
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      return 1;
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   case PIPE_CAP_TGSI_TEXCOORD:
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      return 0;
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   case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
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      return VIRGL_MAP_BUFFER_ALIGNMENT;
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   case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
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      return vscreen->caps.caps.v1.max_tbo_size > 0;
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   case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
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      return vscreen->caps.caps.v2.texture_buffer_offset_alignment;
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   case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
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      return 0;
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   case PIPE_CAP_CUBE_MAP_ARRAY:
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      return vscreen->caps.caps.v1.bset.cube_map_array;
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   case PIPE_CAP_TEXTURE_MULTISAMPLE:
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      return vscreen->caps.caps.v1.bset.texture_multisample;
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   case PIPE_CAP_MAX_VIEWPORTS:
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      return vscreen->caps.caps.v1.max_viewports;
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   case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
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      return vscreen->caps.caps.v1.max_tbo_size;
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   case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
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   case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
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   case PIPE_CAP_ENDIANNESS:
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      return 0;
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   case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
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   case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
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      return 1;
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   case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
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      return 0;
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   case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
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      return vscreen->caps.caps.v2.max_geom_output_vertices;
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   case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
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      return vscreen->caps.caps.v2.max_geom_total_output_components;
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   case PIPE_CAP_TEXTURE_QUERY_LOD:
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      return vscreen->caps.caps.v1.bset.texture_query_lod;
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   case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
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      return vscreen->caps.caps.v1.max_texture_gather_components;
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   case PIPE_CAP_DRAW_INDIRECT:
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      return vscreen->caps.caps.v1.bset.has_indirect_draw;
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   case PIPE_CAP_SAMPLE_SHADING:
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   case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
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      return vscreen->caps.caps.v1.bset.has_sample_shading;
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   case PIPE_CAP_CULL_DISTANCE:
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      return vscreen->caps.caps.v1.bset.has_cull;
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   case PIPE_CAP_MAX_VERTEX_STREAMS:
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      return ((vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_TRANSFORM_FEEDBACK3) ||
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              (vscreen->caps.caps.v2.host_feature_check_version < 2)) ? 4 : 1;
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   case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
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      return vscreen->caps.caps.v1.bset.conditional_render_inverted;
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   case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
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      return vscreen->caps.caps.v1.bset.derivative_control;
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   case PIPE_CAP_POLYGON_OFFSET_CLAMP:
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      return vscreen->caps.caps.v1.bset.polygon_offset_clamp;
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   case PIPE_CAP_QUERY_SO_OVERFLOW:
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      return vscreen->caps.caps.v1.bset.transform_feedback_overflow_query;
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   case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
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      return vscreen->caps.caps.v2.shader_buffer_offset_alignment;
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   case PIPE_CAP_DOUBLES:
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      return vscreen->caps.caps.v1.bset.has_fp64 ||
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            (vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_FAKE_FP64);
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   case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
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      return vscreen->caps.caps.v2.max_shader_patch_varyings;
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   case PIPE_CAP_SAMPLER_VIEW_TARGET:
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      return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_TEXTURE_VIEW;
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   case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
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      return vscreen->caps.caps.v2.max_vertex_attrib_stride;
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   case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
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      return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_COPY_IMAGE;
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   case PIPE_CAP_TGSI_TXQS:
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      return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_TXQS;
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   case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
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      return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_FB_NO_ATTACH;
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   case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
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      return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_ROBUST_BUFFER_ACCESS;
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   case PIPE_CAP_FBFETCH:
269
      return (vscreen->caps.caps.v2.capability_bits &
270
              VIRGL_CAP_TGSI_FBFETCH) ? 1 : 0;
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   case PIPE_CAP_BLEND_EQUATION_ADVANCED:
272
      return vscreen->caps.caps.v2.capability_bits_v2 & VIRGL_CAP_V2_BLEND_EQUATION;
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   case PIPE_CAP_TGSI_CLOCK:
274
      return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_SHADER_CLOCK;
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   case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
276
      return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_TGSI_COMPONENTS;
277
   case PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS:
278
      return vscreen->caps.caps.v2.max_combined_shader_buffers;
279
   case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS:
280
      return vscreen->caps.caps.v2.max_combined_atomic_counters;
281
   case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS:
282
      return vscreen->caps.caps.v2.max_combined_atomic_counter_buffers;
283
   case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
284
   case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
285
      return 1; /* TODO: need to introduce a hw-cap for this */
286
   case PIPE_CAP_QUERY_BUFFER_OBJECT:
287
      return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_QBO;
288
   case PIPE_CAP_MAX_VARYINGS:
289
      if (vscreen->caps.caps.v1.glsl_level < 150)
290
         return vscreen->caps.caps.v2.max_vertex_attribs;
291
      return 32;
292
   case PIPE_CAP_FAKE_SW_MSAA:
293
      /* If the host supports only one sample (e.g., if it is using softpipe),
294
       * fake multisampling to able to advertise higher GL versions. */
295
      return (vscreen->caps.caps.v1.max_samples == 1) ? 1 : 0;
296
   case PIPE_CAP_MULTI_DRAW_INDIRECT:
297
      return !!(vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_MULTI_DRAW_INDIRECT);
298
   case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
299
      return !!(vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_INDIRECT_PARAMS);
300
   case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
301
      return (vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_ARB_BUFFER_STORAGE) &&
302
             (vscreen->caps.caps.v2.host_feature_check_version >= 4) &&
303
              vscreen->vws->supports_coherent;
304
   case PIPE_CAP_PCI_GROUP:
305
   case PIPE_CAP_PCI_BUS:
306
   case PIPE_CAP_PCI_DEVICE:
307
   case PIPE_CAP_PCI_FUNCTION:
308
   case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
309
   case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
310
      return 0;
311
   case PIPE_CAP_CLEAR_TEXTURE:
312
      return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_CLEAR_TEXTURE;
313
   case PIPE_CAP_CLIP_HALFZ:
314
      return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_CLIP_HALFZ;
315
   case PIPE_CAP_MAX_GS_INVOCATIONS:
316
      return 32;
317
   case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
318
      return 1 << 27;
319
   case PIPE_CAP_VENDOR_ID:
320
      return 0x1af4;
321
   case PIPE_CAP_DEVICE_ID:
322
      return 0x1010;
323
   case PIPE_CAP_ACCELERATED:
324
      return 1;
325
   case PIPE_CAP_UMA:
326
   case PIPE_CAP_VIDEO_MEMORY:
327
      if (vscreen->caps.caps.v2.capability_bits_v2 & VIRGL_CAP_V2_VIDEO_MEMORY)
328
         return vscreen->caps.caps.v2.max_video_memory;
329
      return 0;
330
   case PIPE_CAP_NATIVE_FENCE_FD:
331
      return vscreen->vws->supports_fences;
332
   case PIPE_CAP_DEST_SURFACE_SRGB_CONTROL:
333
      return (vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_SRGB_WRITE_CONTROL) ||
334
            (vscreen->caps.caps.v2.host_feature_check_version < 1);
335
   case PIPE_CAP_TGSI_SKIP_SHRINK_IO_ARRAYS:
336
      return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_INDIRECT_INPUT_ADDR;
337
   case PIPE_CAP_SHAREABLE_SHADERS:
338
      /* Shader creation emits the shader through the context's command buffer
339
       * in virgl_encode_shader_state().
340
       */
341
      return 0;
342
   case PIPE_CAP_QUERY_MEMORY_INFO:
343
      return vscreen->caps.caps.v2.capability_bits_v2 & VIRGL_CAP_V2_MEMINFO;
344
   case PIPE_CAP_STRING_MARKER:
345
       return vscreen->caps.caps.v2.capability_bits_v2 & VIRGL_CAP_V2_STRING_MARKER;
346
   case PIPE_CAP_SURFACE_SAMPLE_COUNT:
347
       return vscreen->caps.caps.v2.capability_bits_v2 & VIRGL_CAP_V2_IMPLICIT_MSAA;
348
   default:
349
      return u_pipe_screen_get_param_defaults(screen, param);
350
   }
351
}
352

353
static int
354
virgl_get_shader_param(struct pipe_screen *screen,
355
                       enum pipe_shader_type shader,
356
                       enum pipe_shader_cap param)
357
{
358
   struct virgl_screen *vscreen = virgl_screen(screen);
359

360
   if ((shader == PIPE_SHADER_TESS_CTRL || shader == PIPE_SHADER_TESS_EVAL) &&
361
       !vscreen->caps.caps.v1.bset.has_tessellation_shaders)
362
      return 0;
363

364
   if (shader == PIPE_SHADER_COMPUTE &&
365
       !(vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_COMPUTE_SHADER))
366
     return 0;
367

368
   switch(shader)
369
   {
370
   case PIPE_SHADER_FRAGMENT:
371
   case PIPE_SHADER_VERTEX:
372
   case PIPE_SHADER_GEOMETRY:
373
   case PIPE_SHADER_TESS_CTRL:
374
   case PIPE_SHADER_TESS_EVAL:
375
   case PIPE_SHADER_COMPUTE:
376
      switch (param) {
377
      case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
378
      case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
379
      case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
380
      case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
381
         return INT_MAX;
382
      case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
383
      case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
384
      case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
385
         return 1;
386
      case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
387
      case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
388
         return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_INDIRECT_INPUT_ADDR;
389
      case PIPE_SHADER_CAP_MAX_INPUTS:
390
         if (vscreen->caps.caps.v1.glsl_level < 150)
391
            return vscreen->caps.caps.v2.max_vertex_attribs;
392
         return (shader == PIPE_SHADER_VERTEX ||
393
                 shader == PIPE_SHADER_GEOMETRY) ? vscreen->caps.caps.v2.max_vertex_attribs : 32;
394
      case PIPE_SHADER_CAP_MAX_OUTPUTS:
395
         if (shader == PIPE_SHADER_FRAGMENT)
396
            return vscreen->caps.caps.v1.max_render_targets;
397
         return vscreen->caps.caps.v2.max_vertex_outputs;
398
     // case PIPE_SHADER_CAP_MAX_CONSTS:
399
     //    return 4096;
400
      case PIPE_SHADER_CAP_MAX_TEMPS:
401
         return 256;
402
      case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
403
         return vscreen->caps.caps.v1.max_uniform_blocks;
404
    //  case PIPE_SHADER_CAP_MAX_ADDRS:
405
     //    return 1;
406
      case PIPE_SHADER_CAP_SUBROUTINES:
407
         return 1;
408
      case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
409
            return 16;
410
      case PIPE_SHADER_CAP_INTEGERS:
411
         return vscreen->caps.caps.v1.glsl_level >= 130;
412
      case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
413
         return 32;
414
      case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
415
         return 4096 * sizeof(float[4]);
416
      case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
417
         if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE)
418
            return vscreen->caps.caps.v2.max_shader_buffer_frag_compute;
419
         else
420
            return vscreen->caps.caps.v2.max_shader_buffer_other_stages;
421
      case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
422
         if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE)
423
            return vscreen->caps.caps.v2.max_shader_image_frag_compute;
424
         else
425
            return vscreen->caps.caps.v2.max_shader_image_other_stages;
426
      case PIPE_SHADER_CAP_SUPPORTED_IRS:
427
         return (1 << PIPE_SHADER_IR_TGSI);
428
      case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
429
         return vscreen->caps.caps.v2.max_atomic_counters[shader];
430
      case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
431
         return vscreen->caps.caps.v2.max_atomic_counter_buffers[shader];
432
      case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
433
      case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
434
      case PIPE_SHADER_CAP_INT64_ATOMICS:
435
      case PIPE_SHADER_CAP_FP16:
436
      case PIPE_SHADER_CAP_FP16_DERIVATIVES:
437
      case PIPE_SHADER_CAP_FP16_CONST_BUFFERS:
438
      case PIPE_SHADER_CAP_INT16:
439
      case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
440
         return 0;
441
      default:
442
         return 0;
443
      }
444
   default:
445
      return 0;
446
   }
447
}
448

449
static float
450
virgl_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
451
{
452
   struct virgl_screen *vscreen = virgl_screen(screen);
453
   switch (param) {
454
   case PIPE_CAPF_MAX_LINE_WIDTH:
455
      return vscreen->caps.caps.v2.max_aliased_line_width;
456
   case PIPE_CAPF_MAX_LINE_WIDTH_AA:
457
      return vscreen->caps.caps.v2.max_smooth_line_width;
458
   case PIPE_CAPF_MAX_POINT_WIDTH:
459
      return vscreen->caps.caps.v2.max_aliased_point_size;
460
   case PIPE_CAPF_MAX_POINT_WIDTH_AA:
461
      return vscreen->caps.caps.v2.max_smooth_point_size;
462
   case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
463
      return 16.0;
464
   case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
465
      return vscreen->caps.caps.v2.max_texture_lod_bias;
466
   case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
467
   case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
468
   case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
469
      return 0.0f;
470
   }
471
   /* should only get here on unhandled cases */
472
   debug_printf("Unexpected PIPE_CAPF %d query\n", param);
473
   return 0.0;
474
}
475

476
static int
477
virgl_get_compute_param(struct pipe_screen *screen,
478
                        enum pipe_shader_ir ir_type,
479
                        enum pipe_compute_cap param,
480
                        void *ret)
481
{
482
   struct virgl_screen *vscreen = virgl_screen(screen);
483
   if (!(vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_COMPUTE_SHADER))
484
      return 0;
485
   switch (param) {
486
   case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
487
      if (ret) {
488
         uint64_t *grid_size = ret;
489
         grid_size[0] = vscreen->caps.caps.v2.max_compute_grid_size[0];
490
         grid_size[1] = vscreen->caps.caps.v2.max_compute_grid_size[1];
491
         grid_size[2] = vscreen->caps.caps.v2.max_compute_grid_size[2];
492
      }
493
      return 3 * sizeof(uint64_t) ;
494
   case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
495
      if (ret) {
496
         uint64_t *block_size = ret;
497
         block_size[0] = vscreen->caps.caps.v2.max_compute_block_size[0];
498
         block_size[1] = vscreen->caps.caps.v2.max_compute_block_size[1];
499
         block_size[2] = vscreen->caps.caps.v2.max_compute_block_size[2];
500
      }
501
      return 3 * sizeof(uint64_t);
502
   case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
503
      if (ret) {
504
         uint64_t *max_threads_per_block = ret;
505
         *max_threads_per_block = vscreen->caps.caps.v2.max_compute_work_group_invocations;
506
      }
507
      return sizeof(uint64_t);
508
   case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
509
      if (ret) {
510
         uint64_t *max_local_size = ret;
511
         /* Value reported by the closed source driver. */
512
         *max_local_size = vscreen->caps.caps.v2.max_compute_shared_memory_size;
513
      }
514
      return sizeof(uint64_t);
515
   default:
516
      break;
517
   }
518
   return 0;
519
}
520

521
static bool
522
has_format_bit(struct virgl_supported_format_mask *mask,
523
               enum virgl_formats fmt)
524
{
525
   assert(fmt < VIRGL_FORMAT_MAX);
526
   unsigned val = (unsigned)fmt;
527
   unsigned idx = val / 32;
528
   unsigned bit = val % 32;
529
   assert(idx < ARRAY_SIZE(mask->bitmask));
530
   return (mask->bitmask[idx] & (1u << bit)) != 0;
531
}
532

533
bool
534
virgl_has_readback_format(struct pipe_screen *screen,
535
                          enum virgl_formats fmt)
536
{
537
   struct virgl_screen *vscreen = virgl_screen(screen);
538
   return has_format_bit(&vscreen->caps.caps.v2.supported_readback_formats,
539
                         fmt);
540
}
541

542
static bool
543
virgl_is_vertex_format_supported(struct pipe_screen *screen,
544
                                 enum pipe_format format)
545
{
546
   struct virgl_screen *vscreen = virgl_screen(screen);
547
   const struct util_format_description *format_desc;
548
   int i;
549

550
   format_desc = util_format_description(format);
551
   if (!format_desc)
552
      return false;
553

554
   if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
555
      int vformat = VIRGL_FORMAT_R11G11B10_FLOAT;
556
      int big = vformat / 32;
557
      int small = vformat % 32;
558
      if (!(vscreen->caps.caps.v1.vertexbuffer.bitmask[big] & (1 << small)))
559
         return false;
560
      return true;
561
   }
562

563
   /* Find the first non-VOID channel. */
564
   for (i = 0; i < 4; i++) {
565
      if (format_desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
566
         break;
567
      }
568
   }
569

570
   if (i == 4)
571
      return false;
572

573
   if (format_desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
574
      return false;
575

576
   if (format_desc->channel[i].type == UTIL_FORMAT_TYPE_FIXED)
577
      return false;
578
   return true;
579
}
580

581
static bool
582
virgl_format_check_bitmask(enum pipe_format format,
583
                           uint32_t bitmask[16],
584
                           bool may_emulate_bgra)
585
{
586
   enum virgl_formats vformat = pipe_to_virgl_format(format);
587
   int big = vformat / 32;
588
   int small = vformat % 32;
589
   if ((bitmask[big] & (1 << small)))
590
      return true;
591

592
   /* On GLES hosts we don't advertise BGRx_SRGB, but we may be able
593
    * emulate it by using a swizzled RGBx */
594
   if (may_emulate_bgra) {
595
      if (format == PIPE_FORMAT_B8G8R8A8_SRGB)
596
         format = PIPE_FORMAT_R8G8B8A8_SRGB;
597
      else if (format == PIPE_FORMAT_B8G8R8X8_SRGB)
598
         format = PIPE_FORMAT_R8G8B8X8_SRGB;
599
      else {
600
         return false;
601
      }
602

603
      vformat = pipe_to_virgl_format(format);
604
      big = vformat / 32;
605
      small = vformat % 32;
606
      if (bitmask[big] & (1 << small))
607
         return true;
608
   }
609
   return false;
610
}
611

612
/**
613
 * Query format support for creating a texture, drawing surface, etc.
614
 * \param format  the format to test
615
 * \param type  one of PIPE_TEXTURE, PIPE_SURFACE
616
 */
617
static bool
618
virgl_is_format_supported( struct pipe_screen *screen,
619
                                 enum pipe_format format,
620
                                 enum pipe_texture_target target,
621
                                 unsigned sample_count,
622
                                 unsigned storage_sample_count,
623
                                 unsigned bind)
624
{
625
   struct virgl_screen *vscreen = virgl_screen(screen);
626
   const struct util_format_description *format_desc;
627
   int i;
628

629
   union virgl_caps *caps = &vscreen->caps.caps; 
630
   boolean may_emulate_bgra = (caps->v2.capability_bits &
631
                               VIRGL_CAP_APP_TWEAK_SUPPORT) &&
632
                               vscreen->tweak_gles_emulate_bgra;
633

634
   if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
635
      return false;
636

637
   if (!util_is_power_of_two_or_zero(sample_count))
638
      return false;
639

640
   assert(target == PIPE_BUFFER ||
641
          target == PIPE_TEXTURE_1D ||
642
          target == PIPE_TEXTURE_1D_ARRAY ||
643
          target == PIPE_TEXTURE_2D ||
644
          target == PIPE_TEXTURE_2D_ARRAY ||
645
          target == PIPE_TEXTURE_RECT ||
646
          target == PIPE_TEXTURE_3D ||
647
          target == PIPE_TEXTURE_CUBE ||
648
          target == PIPE_TEXTURE_CUBE_ARRAY);
649

650
   format_desc = util_format_description(format);
651
   if (!format_desc)
652
      return false;
653

654
   if (util_format_is_intensity(format))
655
      return false;
656

657
   if (sample_count > 1) {
658
      if (!caps->v1.bset.texture_multisample)
659
         return false;
660

661
      if (bind & PIPE_BIND_SHADER_IMAGE) {
662
         if (sample_count > caps->v2.max_image_samples)
663
            return false;
664
      }
665

666
      if (sample_count > caps->v1.max_samples)
667
         return false;
668
   }
669

670
   if (bind & PIPE_BIND_VERTEX_BUFFER) {
671
      return virgl_is_vertex_format_supported(screen, format);
672
   }
673

674
   if (util_format_is_compressed(format) && target == PIPE_BUFFER)
675
      return false;
676

677
   /* Allow 3-comp 32 bit textures only for TBOs (needed for ARB_tbo_rgb32) */
678
   if ((format == PIPE_FORMAT_R32G32B32_FLOAT ||
679
       format == PIPE_FORMAT_R32G32B32_SINT ||
680
       format == PIPE_FORMAT_R32G32B32_UINT) &&
681
       target != PIPE_BUFFER)
682
      return false;
683

684
   if ((format_desc->layout == UTIL_FORMAT_LAYOUT_RGTC ||
685
        format_desc->layout == UTIL_FORMAT_LAYOUT_ETC ||
686
        format_desc->layout == UTIL_FORMAT_LAYOUT_S3TC) &&
687
       target == PIPE_TEXTURE_3D)
688
      return false;
689

690

691
   if (bind & PIPE_BIND_RENDER_TARGET) {
692
      /* For ARB_framebuffer_no_attachments. */
693
      if (format == PIPE_FORMAT_NONE)
694
         return TRUE;
695

696
      if (format_desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS)
697
         return false;
698

699
      /*
700
       * Although possible, it is unnatural to render into compressed or YUV
701
       * surfaces. So disable these here to avoid going into weird paths
702
       * inside gallium frontends.
703
       */
704
      if (format_desc->block.width != 1 ||
705
          format_desc->block.height != 1)
706
         return false;
707

708
      if (!virgl_format_check_bitmask(format,
709
                                      caps->v1.render.bitmask,
710
                                      may_emulate_bgra))
711
         return false;
712
   }
713

714
   if (bind & PIPE_BIND_DEPTH_STENCIL) {
715
      if (format_desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
716
         return false;
717
   }
718

719
   if (bind & PIPE_BIND_SCANOUT) {
720
      if (!virgl_format_check_bitmask(format, caps->v2.scanout.bitmask, false))
721
         return false;
722
   }
723

724
   /*
725
    * All other operations (sampling, transfer, etc).
726
    */
727

728
   if (format_desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
729
      goto out_lookup;
730
   }
731
   if (format_desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
732
      goto out_lookup;
733
   }
734
   if (format_desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
735
      goto out_lookup;
736
   }
737
   if (format_desc->layout == UTIL_FORMAT_LAYOUT_ETC) {
738
      goto out_lookup;
739
   }
740

741
   if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
742
      goto out_lookup;
743
   } else if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
744
      goto out_lookup;
745
   }
746

747
   if (format_desc->layout == UTIL_FORMAT_LAYOUT_ASTC) {
748
     goto out_lookup;
749
   }
750

751
   /* Find the first non-VOID channel. */
752
   for (i = 0; i < 4; i++) {
753
      if (format_desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
754
         break;
755
      }
756
   }
757

758
   if (i == 4)
759
      return false;
760

761
   /* no L4A4 */
762
   if (format_desc->nr_channels < 4 && format_desc->channel[i].size == 4)
763
      return false;
764

765
 out_lookup:
766
   return virgl_format_check_bitmask(format,
767
                                     caps->v1.sampler.bitmask,
768
                                     may_emulate_bgra);
769
}
770

771
static void virgl_flush_frontbuffer(struct pipe_screen *screen,
772
                                    struct pipe_context *ctx,
773
                                      struct pipe_resource *res,
774
                                      unsigned level, unsigned layer,
775
                                    void *winsys_drawable_handle, struct pipe_box *sub_box)
776
{
777
   struct virgl_screen *vscreen = virgl_screen(screen);
778
   struct virgl_winsys *vws = vscreen->vws;
779
   struct virgl_resource *vres = virgl_resource(res);
780

781
   if (vws->flush_frontbuffer)
782
      vws->flush_frontbuffer(vws, vres->hw_res, level, layer, winsys_drawable_handle,
783
                             sub_box);
784
}
785

786
static void virgl_fence_reference(struct pipe_screen *screen,
787
                                  struct pipe_fence_handle **ptr,
788
                                  struct pipe_fence_handle *fence)
789
{
790
   struct virgl_screen *vscreen = virgl_screen(screen);
791
   struct virgl_winsys *vws = vscreen->vws;
792

793
   vws->fence_reference(vws, ptr, fence);
794
}
795

796
static bool virgl_fence_finish(struct pipe_screen *screen,
797
                               struct pipe_context *ctx,
798
                               struct pipe_fence_handle *fence,
799
                               uint64_t timeout)
800
{
801
   struct virgl_screen *vscreen = virgl_screen(screen);
802
   struct virgl_winsys *vws = vscreen->vws;
803

804
   return vws->fence_wait(vws, fence, timeout);
805
}
806

807
static int virgl_fence_get_fd(struct pipe_screen *screen,
808
            struct pipe_fence_handle *fence)
809
{
810
   struct virgl_screen *vscreen = virgl_screen(screen);
811
   struct virgl_winsys *vws = vscreen->vws;
812

813
   return vws->fence_get_fd(vws, fence);
814
}
815

816
static uint64_t
817
virgl_get_timestamp(struct pipe_screen *_screen)
818
{
819
   return os_time_get_nano();
820
}
821

822
static void
823
virgl_destroy_screen(struct pipe_screen *screen)
824
{
825
   struct virgl_screen *vscreen = virgl_screen(screen);
826
   struct virgl_winsys *vws = vscreen->vws;
827

828
   slab_destroy_parent(&vscreen->transfer_pool);
829

830
   if (vws)
831
      vws->destroy(vws);
832

833
   disk_cache_destroy(vscreen->disk_cache);
834

835
   FREE(vscreen);
836
}
837

838
static void
839
fixup_formats(union virgl_caps *caps, struct virgl_supported_format_mask *mask)
840
{
841
   const size_t size = ARRAY_SIZE(mask->bitmask);
842
   for (int i = 0; i < size; ++i) {
843
      if (mask->bitmask[i] != 0)
844
         return; /* we got some formats, we definitely have a new protocol */
845
   }
846

847
   /* old protocol used; fall back to considering all sampleable formats valid
848
    * readback-formats
849
    */
850
   for (int i = 0; i < size; ++i)
851
      mask->bitmask[i] = caps->v1.sampler.bitmask[i];
852
}
853

854
static void virgl_query_memory_info(struct pipe_screen *screen, struct pipe_memory_info *info)
855
{
856
   struct virgl_screen *vscreen = virgl_screen(screen);
857
   struct pipe_context *ctx = screen->context_create(screen, NULL, 0);
858
   struct virgl_context *vctx = virgl_context(ctx);
859
   struct virgl_resource *res;
860
   struct virgl_memory_info virgl_info = {0};
861
   const static struct pipe_resource templ = {
862
      .target = PIPE_BUFFER,
863
      .format = PIPE_FORMAT_R8_UNORM,
864
      .bind = PIPE_BIND_CUSTOM,
865
      .width0 = sizeof(struct virgl_memory_info),
866
      .height0 = 1,
867
      .depth0 = 1,
868
      .array_size = 1,
869
      .last_level = 0,
870
      .nr_samples = 0,
871
      .flags = 0
872
   };
873

874
   res = (struct virgl_resource*) screen->resource_create(screen, &templ);
875

876
   virgl_encode_get_memory_info(vctx, res);
877
   ctx->flush(ctx, NULL, 0);
878
   vscreen->vws->resource_wait(vscreen->vws, res->hw_res);
879
   pipe_buffer_read(ctx, &res->b, 0, sizeof(struct virgl_memory_info), &virgl_info);
880

881
   info->avail_device_memory = virgl_info.avail_device_memory;
882
   info->avail_staging_memory = virgl_info.avail_staging_memory;
883
   info->device_memory_evicted = virgl_info.device_memory_evicted;
884
   info->nr_device_memory_evictions = virgl_info.nr_device_memory_evictions;
885
   info->total_device_memory = virgl_info.total_device_memory;
886
   info->total_staging_memory = virgl_info.total_staging_memory;
887

888
   screen->resource_destroy(screen, &res->b);
889
   ctx->destroy(ctx);
890
}
891

892
static struct disk_cache *virgl_get_disk_shader_cache (struct pipe_screen *pscreen)
893
{
894
   struct virgl_screen *screen = virgl_screen(pscreen);
895

896
   return screen->disk_cache;
897
}
898

899
static void virgl_disk_cache_create(struct virgl_screen *screen)
900
{
901
//#ifndef __APPLE__
902
//   const struct build_id_note *note =
903
//      build_id_find_nhdr_for_addr(virgl_disk_cache_create);
904
//   assert(note && build_id_length(note) == 20); /* sha1 */
905
//
906
//   const uint8_t *id_sha1 = build_id_data(note);
907
//   assert(id_sha1);
908
//
909
//   char timestamp[41];
910
//   _mesa_sha1_format(timestamp, id_sha1);
911
//
912
//   screen->disk_cache = disk_cache_create("virgl", timestamp, 0);
913
//#else
914
//   screen->disk_cache = disk_cache_create("virgl", "??? (build_id unimplemented)", 0);
915
//#endif
916

917
   screen->disk_cache = disk_cache_create("virgl", "unknown", 0);
918
}
919

920
static void
921
fixup_renderer(union virgl_caps *caps)
922
{
923
   if (caps->v2.host_feature_check_version < 5)
924
      return;
925

926
   char renderer[64];
927
   int renderer_len = snprintf(renderer, sizeof(renderer), "virgl (%s)",
928
                               caps->v2.renderer);
929
   if (renderer_len >= 64) {
930
      memcpy(renderer + 59, "...)", 4);
931
      renderer_len = 63;
932
   }
933
   memcpy(caps->v2.renderer, renderer, renderer_len + 1);
934
}
935

936
struct pipe_screen *
937
virgl_create_screen(struct virgl_winsys *vws, const struct pipe_screen_config *config)
938
{
939
   struct virgl_screen *screen = CALLOC_STRUCT(virgl_screen);
940

941
   const char *VIRGL_GLES_EMULATE_BGRA = "gles_emulate_bgra";
942
   const char *VIRGL_GLES_APPLY_BGRA_DEST_SWIZZLE = "gles_apply_bgra_dest_swizzle";
943
   const char *VIRGL_GLES_SAMPLES_PASSED_VALUE = "gles_samples_passed_value";
944

945
   if (!screen)
946
      return NULL;
947

948
   virgl_debug = debug_get_option_virgl_debug();
949

950
   if (config && config->options) {
951
      screen->tweak_gles_emulate_bgra =
952
            driQueryOptionb(config->options, VIRGL_GLES_EMULATE_BGRA);
953
      screen->tweak_gles_apply_bgra_dest_swizzle =
954
            driQueryOptionb(config->options, VIRGL_GLES_APPLY_BGRA_DEST_SWIZZLE);
955
      screen->tweak_gles_tf3_value =
956
            driQueryOptioni(config->options, VIRGL_GLES_SAMPLES_PASSED_VALUE);
957
   }
958
   screen->tweak_gles_emulate_bgra &= !(virgl_debug & VIRGL_DEBUG_NO_EMULATE_BGRA);
959
   screen->tweak_gles_apply_bgra_dest_swizzle &= !(virgl_debug & VIRGL_DEBUG_NO_BGRA_DEST_SWIZZLE);
960

961
   screen->vws = vws;
962
   screen->base.get_name = virgl_get_name;
963
   screen->base.get_vendor = virgl_get_vendor;
964
   screen->base.get_param = virgl_get_param;
965
   screen->base.get_shader_param = virgl_get_shader_param;
966
   screen->base.get_compute_param = virgl_get_compute_param;
967
   screen->base.get_paramf = virgl_get_paramf;
968
   screen->base.is_format_supported = virgl_is_format_supported;
969
   screen->base.destroy = virgl_destroy_screen;
970
   screen->base.context_create = virgl_context_create;
971
   screen->base.flush_frontbuffer = virgl_flush_frontbuffer;
972
   screen->base.get_timestamp = virgl_get_timestamp;
973
   screen->base.fence_reference = virgl_fence_reference;
974
   //screen->base.fence_signalled = virgl_fence_signalled;
975
   screen->base.fence_finish = virgl_fence_finish;
976
   screen->base.fence_get_fd = virgl_fence_get_fd;
977
   screen->base.query_memory_info = virgl_query_memory_info;
978
   screen->base.get_disk_shader_cache = virgl_get_disk_shader_cache;
979

980
   virgl_init_screen_resource_functions(&screen->base);
981

982
   vws->get_caps(vws, &screen->caps);
983
   fixup_formats(&screen->caps.caps,
984
                 &screen->caps.caps.v2.supported_readback_formats);
985
   fixup_formats(&screen->caps.caps, &screen->caps.caps.v2.scanout);
986
   fixup_renderer(&screen->caps.caps);
987

988
   union virgl_caps *caps = &screen->caps.caps;
989
   screen->tweak_gles_emulate_bgra &= !virgl_format_check_bitmask(PIPE_FORMAT_B8G8R8A8_SRGB, caps->v1.render.bitmask, false);
990
   screen->refcnt = 1;
991

992
   slab_create_parent(&screen->transfer_pool, sizeof(struct virgl_transfer), 16);
993

994
   virgl_disk_cache_create(screen);
995
   return &screen->base;
996
}
997

998
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