Path: blob/21.2-virgl/src/gallium/drivers/virgl/virgl_winsys.h
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/*1* Copyright 2014, 2015 Red Hat.2*3* Permission is hereby granted, free of charge, to any person obtaining a4* copy of this software and associated documentation files (the "Software"),5* to deal in the Software without restriction, including without limitation6* on the rights to use, copy, modify, merge, publish, distribute, sub7* license, and/or sell copies of the Software, and to permit persons to whom8* the Software is furnished to do so, subject to the following conditions:9*10* The above copyright notice and this permission notice (including the next11* paragraph) shall be included in all copies or substantial portions of the12* Software.13*14* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL17* THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,18* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR19* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE20* USE OR OTHER DEALINGS IN THE SOFTWARE.21*/22#ifndef VIRGL_WINSYS_H23#define VIRGL_WINSYS_H2425#include "pipe/p_defines.h"26#include "virtio-gpu/virgl_hw.h"2728struct pipe_box;29struct pipe_fence_handle;30struct winsys_handle;31struct virgl_hw_res;3233#define VIRGL_MAX_TBUF_DWORDS 102434#define VIRGL_MAX_CMDBUF_DWORDS ((64 * 1024) + VIRGL_MAX_TBUF_DWORDS)35#define VIRGL_MAX_PLANE_COUNT 33637struct virgl_drm_caps {38union virgl_caps caps;39};4041struct virgl_cmd_buf {42unsigned cdw;43uint32_t *buf;44};4546struct virgl_winsys {47unsigned pci_id;48int supports_fences; /* In/Out fences are supported */49int supports_encoded_transfers; /* Encoded transfers are supported */50int supports_coherent; /* Coherent memory is supported */5152void (*destroy)(struct virgl_winsys *vws);5354int (*transfer_put)(struct virgl_winsys *vws,55struct virgl_hw_res *res,56const struct pipe_box *box,57uint32_t stride, uint32_t layer_stride,58uint32_t buf_offset, uint32_t level);5960int (*transfer_get)(struct virgl_winsys *vws,61struct virgl_hw_res *res,62const struct pipe_box *box,63uint32_t stride, uint32_t layer_stride,64uint32_t buf_offset, uint32_t level);6566struct virgl_hw_res *(*resource_create)(struct virgl_winsys *vws,67enum pipe_texture_target target,68uint32_t format, uint32_t bind,69uint32_t width, uint32_t height,70uint32_t depth, uint32_t array_size,71uint32_t last_level, uint32_t nr_samples,72uint32_t flags, uint32_t size);7374void (*resource_reference)(struct virgl_winsys *qws,75struct virgl_hw_res **dres,76struct virgl_hw_res *sres);7778void *(*resource_map)(struct virgl_winsys *vws, struct virgl_hw_res *res);79void (*resource_wait)(struct virgl_winsys *vws, struct virgl_hw_res *res);80boolean (*resource_is_busy)(struct virgl_winsys *vws,81struct virgl_hw_res *res);8283struct virgl_hw_res *(*resource_create_from_handle)(struct virgl_winsys *vws,84struct winsys_handle *whandle,85uint32_t *plane,86uint32_t *stride,87uint32_t *plane_offset,88uint64_t *modifier,89uint32_t *blob_mem);90void (*resource_set_type)(struct virgl_winsys *vws,91struct virgl_hw_res *res,92uint32_t format, uint32_t bind,93uint32_t width, uint32_t height,94uint32_t usage, uint64_t modifier,95uint32_t plane_count,96const uint32_t *plane_strides,97const uint32_t *plane_offsets);9899boolean (*resource_get_handle)(struct virgl_winsys *vws,100struct virgl_hw_res *res,101uint32_t stride,102struct winsys_handle *whandle);103104struct virgl_cmd_buf *(*cmd_buf_create)(struct virgl_winsys *ws, uint32_t size);105void (*cmd_buf_destroy)(struct virgl_cmd_buf *buf);106107void (*emit_res)(struct virgl_winsys *vws, struct virgl_cmd_buf *buf, struct virgl_hw_res *res, boolean write_buffer);108int (*submit_cmd)(struct virgl_winsys *vws, struct virgl_cmd_buf *buf,109struct pipe_fence_handle **fence);110111boolean (*res_is_referenced)(struct virgl_winsys *vws,112struct virgl_cmd_buf *buf,113struct virgl_hw_res *res);114115int (*get_caps)(struct virgl_winsys *vws, struct virgl_drm_caps *caps);116117/* fence */118struct pipe_fence_handle *(*cs_create_fence)(struct virgl_winsys *vws, int fd);119bool (*fence_wait)(struct virgl_winsys *vws,120struct pipe_fence_handle *fence,121uint64_t timeout);122123void (*fence_reference)(struct virgl_winsys *vws,124struct pipe_fence_handle **dst,125struct pipe_fence_handle *src);126127/* for sw paths */128void (*flush_frontbuffer)(struct virgl_winsys *vws,129struct virgl_hw_res *res,130unsigned level, unsigned layer,131void *winsys_drawable_handle,132struct pipe_box *sub_box);133void (*fence_server_sync)(struct virgl_winsys *vws,134struct virgl_cmd_buf *cbuf,135struct pipe_fence_handle *fence);136137int (*fence_get_fd)(struct virgl_winsys *vws,138struct pipe_fence_handle *fence);139};140141/* this defaults all newer caps,142* the kernel will overwrite these if newer version is available.143*/144static inline void virgl_ws_fill_new_caps_defaults(struct virgl_drm_caps *caps)145{146caps->caps.v2.min_aliased_point_size = 1.f;147caps->caps.v2.max_aliased_point_size = 255.f;148caps->caps.v2.min_smooth_point_size = 1.f;149caps->caps.v2.max_smooth_point_size = 190.f;150caps->caps.v2.min_aliased_line_width = 1.f;151caps->caps.v2.max_aliased_line_width = 10.f;152caps->caps.v2.min_smooth_line_width = 0.f;153caps->caps.v2.max_smooth_line_width = 10.f;154caps->caps.v2.max_texture_lod_bias = 15.0f;155caps->caps.v2.max_geom_output_vertices = 256;156caps->caps.v2.max_geom_total_output_components = 1024;157caps->caps.v2.max_vertex_outputs = 32;158caps->caps.v2.max_vertex_attribs = 16;159caps->caps.v2.max_shader_patch_varyings = 30;160caps->caps.v2.min_texel_offset = -8;161caps->caps.v2.max_texel_offset = 7;162caps->caps.v2.min_texture_gather_offset = -8;163caps->caps.v2.max_texture_gather_offset = 7;164caps->caps.v2.texture_buffer_offset_alignment = 0;165caps->caps.v2.uniform_buffer_offset_alignment = 256;166caps->caps.v2.shader_buffer_offset_alignment = 32;167caps->caps.v2.capability_bits = 0;168caps->caps.v2.max_vertex_attrib_stride = 0;169caps->caps.v2.max_image_samples = 0;170caps->caps.v2.max_compute_work_group_invocations = 0;171caps->caps.v2.max_compute_shared_memory_size = 0;172caps->caps.v2.host_feature_check_version = 0;173}174175extern enum virgl_formats pipe_to_virgl_format(enum pipe_format format);176177#endif178179180