Path: blob/21.2-virgl/src/gallium/drivers/zink/zink_context.h
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/*1* Copyright 2018 Collabora Ltd.2*3* Permission is hereby granted, free of charge, to any person obtaining a4* copy of this software and associated documentation files (the "Software"),5* to deal in the Software without restriction, including without limitation6* on the rights to use, copy, modify, merge, publish, distribute, sub7* license, and/or sell copies of the Software, and to permit persons to whom8* the Software is furnished to do so, subject to the following conditions:9*10* The above copyright notice and this permission notice (including the next11* paragraph) shall be included in all copies or substantial portions of the12* Software.13*14* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL17* THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,18* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR19* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE20* USE OR OTHER DEALINGS IN THE SOFTWARE.21*/2223#ifndef ZINK_CONTEXT_H24#define ZINK_CONTEXT_H2526#define ZINK_SHADER_COUNT (PIPE_SHADER_TYPES - 1)2728#define ZINK_DEFAULT_MAX_DESCS 50002930#include "zink_clear.h"31#include "zink_pipeline.h"32#include "zink_batch.h"33#include "zink_compiler.h"34#include "zink_descriptors.h"35#include "zink_surface.h"3637#include "pipe/p_context.h"38#include "pipe/p_state.h"39#include "util/u_rect.h"40#include "util/u_threaded_context.h"4142#include "util/slab.h"43#include "util/list.h"44#include "util/u_dynarray.h"4546#include <vulkan/vulkan.h>4748#ifdef __cplusplus49extern "C" {50#endif5152struct blitter_context;53struct list_head;5455struct zink_blend_state;56struct zink_depth_stencil_alpha_state;57struct zink_gfx_program;58struct zink_rasterizer_state;59struct zink_resource;60struct zink_vertex_elements_state;6162enum zink_blit_flags {63ZINK_BLIT_NORMAL = 1 << 0,64ZINK_BLIT_SAVE_FS = 1 << 1,65ZINK_BLIT_SAVE_FB = 1 << 2,66ZINK_BLIT_SAVE_TEXTURES = 1 << 3,67ZINK_BLIT_NO_COND_RENDER = 1 << 4,68};6970struct zink_sampler_state {71VkSampler sampler;72uint32_t hash;73struct zink_descriptor_refs desc_set_refs;74struct zink_batch_usage *batch_uses;75bool custom_border_color;76};7778struct zink_buffer_view {79struct pipe_reference reference;80VkBufferViewCreateInfo bvci;81VkBufferView buffer_view;82uint32_t hash;83struct zink_batch_usage *batch_uses;84struct zink_descriptor_refs desc_set_refs;85};8687struct zink_sampler_view {88struct pipe_sampler_view base;89union {90struct zink_surface *image_view;91struct zink_buffer_view *buffer_view;92};93};9495struct zink_image_view {96struct pipe_image_view base;97union {98struct zink_surface *surface;99struct zink_buffer_view *buffer_view;100};101};102103static inline struct zink_sampler_view *104zink_sampler_view(struct pipe_sampler_view *pview)105{106return (struct zink_sampler_view *)pview;107}108109struct zink_so_target {110struct pipe_stream_output_target base;111struct pipe_resource *counter_buffer;112VkDeviceSize counter_buffer_offset;113uint32_t stride;114bool counter_buffer_valid;115};116117static inline struct zink_so_target *118zink_so_target(struct pipe_stream_output_target *so_target)119{120return (struct zink_so_target *)so_target;121}122123struct zink_viewport_state {124struct pipe_viewport_state viewport_states[PIPE_MAX_VIEWPORTS];125struct pipe_scissor_state scissor_states[PIPE_MAX_VIEWPORTS];126uint8_t num_viewports;127};128129130struct zink_descriptor_surface {131union {132struct zink_surface *surface;133struct zink_buffer_view *bufferview;134};135bool is_buffer;136};137138struct zink_context {139struct pipe_context base;140struct threaded_context *tc;141struct slab_child_pool transfer_pool;142struct slab_child_pool transfer_pool_unsync;143struct blitter_context *blitter;144145struct pipe_device_reset_callback reset;146147uint32_t curr_batch; //the current batch id148149simple_mtx_t batch_mtx;150struct zink_fence *deferred_fence;151struct zink_fence *last_fence; //the last command buffer submitted152struct hash_table batch_states; //submitted batch states153struct util_dynarray free_batch_states; //unused batch states154VkDeviceSize resource_size; //the accumulated size of resources in submitted buffers155struct zink_batch batch;156157unsigned shader_has_inlinable_uniforms_mask;158unsigned inlinable_uniforms_valid_mask;159uint32_t inlinable_uniforms[PIPE_SHADER_TYPES][MAX_INLINABLE_UNIFORMS];160161struct pipe_constant_buffer ubos[PIPE_SHADER_TYPES][PIPE_MAX_CONSTANT_BUFFERS];162struct pipe_shader_buffer ssbos[PIPE_SHADER_TYPES][PIPE_MAX_SHADER_BUFFERS];163uint32_t writable_ssbos[PIPE_SHADER_TYPES];164struct zink_image_view image_views[PIPE_SHADER_TYPES][PIPE_MAX_SHADER_IMAGES];165166struct pipe_framebuffer_state fb_state;167168struct zink_vertex_elements_state *element_state;169struct zink_rasterizer_state *rast_state;170struct zink_depth_stencil_alpha_state *dsa_state;171172struct hash_table desc_set_layouts[ZINK_DESCRIPTOR_TYPES];173bool pipeline_changed[2]; //gfx, compute174175struct zink_shader *gfx_stages[ZINK_SHADER_COUNT];176struct zink_shader *last_vertex_stage;177struct zink_gfx_pipeline_state gfx_pipeline_state;178enum pipe_prim_type gfx_prim_mode;179struct hash_table *program_cache;180struct zink_gfx_program *curr_program;181182struct zink_descriptor_data *dd;183184struct zink_shader *compute_stage;185struct zink_compute_pipeline_state compute_pipeline_state;186struct hash_table *compute_program_cache;187struct zink_compute_program *curr_compute;188189unsigned dirty_shader_stages : 6; /* mask of changed shader stages */190bool last_vertex_stage_dirty;191192struct hash_table *render_pass_cache;193bool new_swapchain;194bool fb_changed;195bool rp_changed;196197struct zink_framebuffer *framebuffer;198struct zink_framebuffer_clear fb_clears[PIPE_MAX_COLOR_BUFS + 1];199uint16_t clears_enabled;200uint16_t rp_clears_enabled;201202struct pipe_vertex_buffer vertex_buffers[PIPE_MAX_ATTRIBS];203bool vertex_buffers_dirty;204205void *sampler_states[PIPE_SHADER_TYPES][PIPE_MAX_SAMPLERS];206struct pipe_sampler_view *sampler_views[PIPE_SHADER_TYPES][PIPE_MAX_SAMPLERS];207208struct zink_viewport_state vp_state;209bool vp_state_changed;210bool scissor_changed;211212float line_width;213float blend_constants[4];214215bool sample_locations_changed;216VkSampleLocationEXT vk_sample_locations[PIPE_MAX_SAMPLE_LOCATION_GRID_SIZE * PIPE_MAX_SAMPLE_LOCATION_GRID_SIZE];217uint8_t sample_locations[2 * 4 * 8 * 16];218219bool drawid_broken;220221struct pipe_stencil_ref stencil_ref;222223union {224struct {225float default_inner_level[2];226float default_outer_level[4];227};228float tess_levels[6];229};230231struct list_head suspended_queries;232struct list_head primitives_generated_queries;233bool queries_disabled, render_condition_active;234struct {235struct zink_query *query;236bool inverted;237} render_condition;238239struct pipe_resource *dummy_vertex_buffer;240struct pipe_resource *dummy_xfb_buffer;241struct pipe_surface *dummy_surface;242struct zink_buffer_view *dummy_bufferview;243244struct {245/* descriptor info */246VkDescriptorBufferInfo ubos[PIPE_SHADER_TYPES][PIPE_MAX_CONSTANT_BUFFERS];247uint32_t push_valid;248uint8_t num_ubos[PIPE_SHADER_TYPES];249250VkDescriptorBufferInfo ssbos[PIPE_SHADER_TYPES][PIPE_MAX_SHADER_BUFFERS];251uint8_t num_ssbos[PIPE_SHADER_TYPES];252253VkDescriptorImageInfo textures[PIPE_SHADER_TYPES][PIPE_MAX_SAMPLERS];254VkBufferView tbos[PIPE_SHADER_TYPES][PIPE_MAX_SAMPLERS];255uint8_t num_samplers[PIPE_SHADER_TYPES];256uint8_t num_sampler_views[PIPE_SHADER_TYPES];257258VkDescriptorImageInfo images[PIPE_SHADER_TYPES][PIPE_MAX_SHADER_IMAGES];259VkBufferView texel_images[PIPE_SHADER_TYPES][PIPE_MAX_SHADER_IMAGES];260uint8_t num_images[PIPE_SHADER_TYPES];261262struct zink_resource *descriptor_res[ZINK_DESCRIPTOR_TYPES][PIPE_SHADER_TYPES][PIPE_MAX_SAMPLERS];263struct zink_descriptor_surface sampler_surfaces[PIPE_SHADER_TYPES][PIPE_MAX_SAMPLERS];264struct zink_descriptor_surface image_surfaces[PIPE_SHADER_TYPES][PIPE_MAX_SHADER_IMAGES];265} di;266bool descriptor_refs_dirty[2];267struct set *need_barriers[2]; //gfx, compute268struct set update_barriers[2][2]; //[gfx, compute][current, next]269uint8_t barrier_set_idx[2];270271uint32_t num_so_targets;272struct pipe_stream_output_target *so_targets[PIPE_MAX_SO_OUTPUTS];273bool dirty_so_targets;274bool xfb_barrier;275bool first_frame_done;276bool have_timelines;277278bool is_device_lost;279bool rast_state_changed : 1;280bool dsa_state_changed : 1;281bool stencil_ref_changed : 1;282};283284static inline struct zink_context *285zink_context(struct pipe_context *context)286{287return (struct zink_context *)context;288}289290static inline bool291zink_fb_clear_enabled(const struct zink_context *ctx, unsigned idx)292{293if (idx == PIPE_MAX_COLOR_BUFS)294return ctx->clears_enabled & PIPE_CLEAR_DEPTHSTENCIL;295return ctx->clears_enabled & (PIPE_CLEAR_COLOR0 << idx);296}297298struct zink_batch *299zink_batch_rp(struct zink_context *ctx);300301struct zink_batch *302zink_batch_no_rp(struct zink_context *ctx);303304void305zink_fence_wait(struct pipe_context *ctx);306307void308zink_wait_on_batch(struct zink_context *ctx, uint32_t batch_id);309310bool311zink_check_batch_completion(struct zink_context *ctx, uint32_t batch_id);312313void314zink_flush_queue(struct zink_context *ctx);315316void317zink_maybe_flush_or_stall(struct zink_context *ctx);318319bool320zink_resource_access_is_write(VkAccessFlags flags);321322void323zink_resource_buffer_barrier(struct zink_context *ctx, struct zink_batch *batch, struct zink_resource *res, VkAccessFlags flags, VkPipelineStageFlags pipeline);324void325zink_fake_buffer_barrier(struct zink_resource *res, VkAccessFlags flags, VkPipelineStageFlags pipeline);326bool327zink_resource_image_needs_barrier(struct zink_resource *res, VkImageLayout new_layout, VkAccessFlags flags, VkPipelineStageFlags pipeline);328bool329zink_resource_image_barrier_init(VkImageMemoryBarrier *imb, struct zink_resource *res, VkImageLayout new_layout, VkAccessFlags flags, VkPipelineStageFlags pipeline);330void331zink_resource_image_barrier(struct zink_context *ctx, struct zink_batch *batch, struct zink_resource *res,332VkImageLayout new_layout, VkAccessFlags flags, VkPipelineStageFlags pipeline);333334bool335zink_resource_needs_barrier(struct zink_resource *res, VkImageLayout layout, VkAccessFlags flags, VkPipelineStageFlags pipeline);336void337zink_resource_barrier(struct zink_context *ctx, struct zink_batch *batch, struct zink_resource *res, VkImageLayout layout, VkAccessFlags flags, VkPipelineStageFlags pipeline);338339void340zink_begin_render_pass(struct zink_context *ctx,341struct zink_batch *batch);342343VkPipelineStageFlags344zink_pipeline_flags_from_stage(VkShaderStageFlagBits stage);345346VkShaderStageFlagBits347zink_shader_stage(enum pipe_shader_type type);348349struct pipe_context *350zink_context_create(struct pipe_screen *pscreen, void *priv, unsigned flags);351352void353zink_context_query_init(struct pipe_context *ctx);354355void356zink_blit_begin(struct zink_context *ctx, enum zink_blit_flags flags);357358void359zink_blit(struct pipe_context *pctx,360const struct pipe_blit_info *info);361362bool363zink_blit_region_fills(struct u_rect region, unsigned width, unsigned height);364365bool366zink_blit_region_covers(struct u_rect region, struct u_rect covers);367368static inline struct u_rect369zink_rect_from_box(const struct pipe_box *box)370{371return (struct u_rect){box->x, box->x + box->width, box->y, box->y + box->height};372}373374void375zink_resource_rebind(struct zink_context *ctx, struct zink_resource *res);376377void378zink_rebind_framebuffer(struct zink_context *ctx, struct zink_resource *res);379380void381zink_draw_vbo(struct pipe_context *pctx,382const struct pipe_draw_info *dinfo,383unsigned drawid_offset,384const struct pipe_draw_indirect_info *indirect,385const struct pipe_draw_start_count_bias *draws,386unsigned num_draws);387388void389zink_launch_grid(struct pipe_context *pctx, const struct pipe_grid_info *info);390391void392zink_copy_buffer(struct zink_context *ctx, struct zink_batch *batch, struct zink_resource *dst, struct zink_resource *src,393unsigned dst_offset, unsigned src_offset, unsigned size);394395void396zink_copy_image_buffer(struct zink_context *ctx, struct zink_batch *batch, struct zink_resource *dst, struct zink_resource *src,397unsigned dst_level, unsigned dstx, unsigned dsty, unsigned dstz,398unsigned src_level, const struct pipe_box *src_box, enum pipe_map_flags map_flags);399400void401zink_destroy_buffer_view(struct zink_screen *screen, struct zink_buffer_view *buffer_view);402403void404debug_describe_zink_buffer_view(char *buf, const struct zink_buffer_view *ptr);405406static inline void407zink_buffer_view_reference(struct zink_screen *screen,408struct zink_buffer_view **dst,409struct zink_buffer_view *src)410{411struct zink_buffer_view *old_dst = dst ? *dst : NULL;412413if (pipe_reference_described(old_dst ? &old_dst->reference : NULL, &src->reference,414(debug_reference_descriptor)debug_describe_zink_buffer_view))415zink_destroy_buffer_view(screen, old_dst);416if (dst) *dst = src;417}418419void420zink_update_descriptor_refs(struct zink_context *ctx, bool compute);421422void423zink_init_vk_sample_locations(struct zink_context *ctx, VkSampleLocationsInfoEXT *loc);424425426static inline VkPipelineStageFlags427zink_pipeline_flags_from_pipe_stage(enum pipe_shader_type pstage)428{429switch (pstage) {430case PIPE_SHADER_VERTEX:431return VK_PIPELINE_STAGE_VERTEX_SHADER_BIT;432case PIPE_SHADER_FRAGMENT:433return VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT;434case PIPE_SHADER_GEOMETRY:435return VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT;436case PIPE_SHADER_TESS_CTRL:437return VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT;438case PIPE_SHADER_TESS_EVAL:439return VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT;440case PIPE_SHADER_COMPUTE:441return VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT;442default:443unreachable("unknown shader stage");444}445}446447#ifdef __cplusplus448}449#endif450451#endif452453454