Path: blob/21.2-virgl/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h
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/*1* Copyright © 2009 Corbin Simpson2* Copyright © 2015 Advanced Micro Devices, Inc.3* All Rights Reserved.4*5* Permission is hereby granted, free of charge, to any person obtaining6* a copy of this software and associated documentation files (the7* "Software"), to deal in the Software without restriction, including8* without limitation the rights to use, copy, modify, merge, publish,9* distribute, sub license, and/or sell copies of the Software, and to10* permit persons to whom the Software is furnished to do so, subject to11* the following conditions:12*13* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,14* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES15* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND16* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS17* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER18* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE20* USE OR OTHER DEALINGS IN THE SOFTWARE.21*22* The above copyright notice and this permission notice (including the23* next paragraph) shall be included in all copies or substantial portions24* of the Software.25*/2627#ifndef AMDGPU_WINSYS_H28#define AMDGPU_WINSYS_H2930#include "pipebuffer/pb_cache.h"31#include "pipebuffer/pb_slab.h"32#include "gallium/drivers/radeon/radeon_winsys.h"33#include "util/simple_mtx.h"34#include "util/u_queue.h"35#include <amdgpu.h>3637struct amdgpu_cs;3839#define NUM_SLAB_ALLOCATORS 34041struct amdgpu_screen_winsys {42struct radeon_winsys base;43struct amdgpu_winsys *aws;44int fd;45struct pipe_reference reference;46struct amdgpu_screen_winsys *next;4748/* Maps a BO to its KMS handle valid for this DRM file descriptor49* Protected by amdgpu_winsys::sws_list_lock50*/51struct hash_table *kms_handles;52};5354struct amdgpu_winsys {55struct pipe_reference reference;5657/* File descriptor which was passed to amdgpu_device_initialize */58int fd;5960struct pb_cache bo_cache;6162/* Each slab buffer can only contain suballocations of equal sizes, so we63* need to layer the allocators, so that we don't waste too much memory.64*/65struct pb_slabs bo_slabs[NUM_SLAB_ALLOCATORS];66struct pb_slabs bo_slabs_encrypted[NUM_SLAB_ALLOCATORS];6768amdgpu_device_handle dev;6970simple_mtx_t bo_fence_lock;7172int num_cs; /* The number of command streams created. */73unsigned num_total_rejected_cs;74uint32_t surf_index_color;75uint32_t surf_index_fmask;76uint32_t next_bo_unique_id;77uint64_t allocated_vram;78uint64_t allocated_gtt;79uint64_t mapped_vram;80uint64_t mapped_gtt;81uint64_t slab_wasted_vram;82uint64_t slab_wasted_gtt;83uint64_t buffer_wait_time; /* time spent in buffer_wait in ns */84uint64_t num_gfx_IBs;85uint64_t num_sdma_IBs;86uint64_t num_mapped_buffers;87uint64_t gfx_bo_list_counter;88uint64_t gfx_ib_size_counter;8990struct radeon_info info;9192/* multithreaded IB submission */93struct util_queue cs_queue;9495struct amdgpu_gpu_info amdinfo;96struct ac_addrlib *addrlib;9798bool check_vm;99bool noop_cs;100bool reserve_vmid;101bool zero_all_vram_allocs;102#if DEBUG103bool debug_all_bos;104105/* List of all allocated buffers */106simple_mtx_t global_bo_list_lock;107struct list_head global_bo_list;108unsigned num_buffers;109#endif110111/* Single-linked list of all structs amdgpu_screen_winsys referencing this112* struct amdgpu_winsys113*/114simple_mtx_t sws_list_lock;115struct amdgpu_screen_winsys *sws_list;116117/* For returning the same amdgpu_winsys_bo instance for exported118* and re-imported buffers. */119struct hash_table *bo_export_table;120simple_mtx_t bo_export_table_lock;121122/* Since most winsys functions require struct radeon_winsys *, dummy_ws.base is used123* for invoking them because sws_list can be NULL.124*/125struct amdgpu_screen_winsys dummy_ws;126};127128static inline struct amdgpu_screen_winsys *129amdgpu_screen_winsys(struct radeon_winsys *base)130{131return (struct amdgpu_screen_winsys*)base;132}133134static inline struct amdgpu_winsys *135amdgpu_winsys(struct radeon_winsys *base)136{137return amdgpu_screen_winsys(base)->aws;138}139140void amdgpu_surface_init_functions(struct amdgpu_screen_winsys *ws);141142#endif143144145