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PojavLauncherTeam
GitHub Repository: PojavLauncherTeam/mesa
Path: blob/21.2-virgl/src/intel/compiler/brw_disasm.c
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/*
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* Copyright © 2008 Keith Packard
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*
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* Permission to use, copy, modify, distribute, and sell this software and its
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* documentation for any purpose is hereby granted without fee, provided that
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* the above copyright notice appear in all copies and that both that copyright
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* notice and this permission notice appear in supporting documentation, and
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* that the name of the copyright holders not be used in advertising or
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* publicity pertaining to distribution of the software without specific,
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* written prior permission. The copyright holders make no representations
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* about the suitability of this software for any purpose. It is provided "as
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* is" without express or implied warranty.
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*
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* THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
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* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
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* EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
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* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
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* DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
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* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
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* OF THIS SOFTWARE.
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*/
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#include <stdio.h>
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#include <string.h>
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#include <stdarg.h>
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#include "brw_eu_defines.h"
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#include "brw_inst.h"
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#include "brw_shader.h"
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#include "brw_reg.h"
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#include "brw_inst.h"
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#include "brw_eu.h"
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#include "util/half_float.h"
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bool
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brw_has_jip(const struct intel_device_info *devinfo, enum opcode opcode)
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{
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if (devinfo->ver < 6)
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return false;
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return opcode == BRW_OPCODE_IF ||
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opcode == BRW_OPCODE_ELSE ||
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opcode == BRW_OPCODE_ENDIF ||
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opcode == BRW_OPCODE_WHILE ||
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opcode == BRW_OPCODE_BREAK ||
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opcode == BRW_OPCODE_CONTINUE ||
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opcode == BRW_OPCODE_HALT;
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}
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bool
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brw_has_uip(const struct intel_device_info *devinfo, enum opcode opcode)
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{
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if (devinfo->ver < 6)
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return false;
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return (devinfo->ver >= 7 && opcode == BRW_OPCODE_IF) ||
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(devinfo->ver >= 8 && opcode == BRW_OPCODE_ELSE) ||
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opcode == BRW_OPCODE_BREAK ||
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opcode == BRW_OPCODE_CONTINUE ||
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opcode == BRW_OPCODE_HALT;
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}
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static bool
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has_branch_ctrl(const struct intel_device_info *devinfo, enum opcode opcode)
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{
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if (devinfo->ver < 8)
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return false;
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return opcode == BRW_OPCODE_IF ||
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opcode == BRW_OPCODE_ELSE;
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/* opcode == BRW_OPCODE_GOTO; */
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}
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static bool
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is_logic_instruction(unsigned opcode)
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{
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return opcode == BRW_OPCODE_AND ||
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opcode == BRW_OPCODE_NOT ||
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opcode == BRW_OPCODE_OR ||
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opcode == BRW_OPCODE_XOR;
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}
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static bool
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is_send(unsigned opcode)
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{
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return opcode == BRW_OPCODE_SEND ||
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opcode == BRW_OPCODE_SENDC ||
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opcode == BRW_OPCODE_SENDS ||
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opcode == BRW_OPCODE_SENDSC;
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}
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static bool
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is_split_send(UNUSED const struct intel_device_info *devinfo, unsigned opcode)
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{
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if (devinfo->ver >= 12)
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return is_send(opcode);
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else
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return opcode == BRW_OPCODE_SENDS ||
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opcode == BRW_OPCODE_SENDSC;
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}
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const char *const conditional_modifier[16] = {
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[BRW_CONDITIONAL_NONE] = "",
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[BRW_CONDITIONAL_Z] = ".z",
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[BRW_CONDITIONAL_NZ] = ".nz",
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[BRW_CONDITIONAL_G] = ".g",
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[BRW_CONDITIONAL_GE] = ".ge",
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[BRW_CONDITIONAL_L] = ".l",
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[BRW_CONDITIONAL_LE] = ".le",
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[BRW_CONDITIONAL_R] = ".r",
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[BRW_CONDITIONAL_O] = ".o",
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[BRW_CONDITIONAL_U] = ".u",
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};
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static const char *const m_negate[2] = {
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[0] = "",
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[1] = "-",
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};
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static const char *const _abs[2] = {
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[0] = "",
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[1] = "(abs)",
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};
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static const char *const m_bitnot[2] = { "", "~" };
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static const char *const vert_stride[16] = {
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[0] = "0",
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[1] = "1",
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[2] = "2",
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[3] = "4",
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[4] = "8",
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[5] = "16",
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[6] = "32",
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[15] = "VxH",
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};
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static const char *const width[8] = {
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[0] = "1",
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[1] = "2",
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[2] = "4",
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[3] = "8",
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[4] = "16",
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};
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static const char *const horiz_stride[4] = {
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[0] = "0",
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[1] = "1",
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[2] = "2",
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[3] = "4"
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};
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static const char *const chan_sel[4] = {
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[0] = "x",
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[1] = "y",
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[2] = "z",
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[3] = "w",
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};
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static const char *const debug_ctrl[2] = {
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[0] = "",
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[1] = ".breakpoint"
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};
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static const char *const saturate[2] = {
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[0] = "",
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[1] = ".sat"
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};
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static const char *const cmpt_ctrl[2] = {
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[0] = "",
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[1] = "compacted"
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};
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static const char *const accwr[2] = {
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[0] = "",
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[1] = "AccWrEnable"
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};
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static const char *const branch_ctrl[2] = {
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[0] = "",
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[1] = "BranchCtrl"
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};
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static const char *const wectrl[2] = {
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[0] = "",
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[1] = "WE_all"
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};
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static const char *const exec_size[8] = {
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[0] = "1",
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[1] = "2",
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[2] = "4",
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[3] = "8",
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[4] = "16",
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[5] = "32"
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};
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static const char *const pred_inv[2] = {
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[0] = "+",
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[1] = "-"
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};
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const char *const pred_ctrl_align16[16] = {
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[1] = "",
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[2] = ".x",
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[3] = ".y",
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[4] = ".z",
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[5] = ".w",
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[6] = ".any4h",
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[7] = ".all4h",
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};
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static const char *const pred_ctrl_align1[16] = {
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[BRW_PREDICATE_NORMAL] = "",
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[BRW_PREDICATE_ALIGN1_ANYV] = ".anyv",
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[BRW_PREDICATE_ALIGN1_ALLV] = ".allv",
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[BRW_PREDICATE_ALIGN1_ANY2H] = ".any2h",
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[BRW_PREDICATE_ALIGN1_ALL2H] = ".all2h",
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[BRW_PREDICATE_ALIGN1_ANY4H] = ".any4h",
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[BRW_PREDICATE_ALIGN1_ALL4H] = ".all4h",
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[BRW_PREDICATE_ALIGN1_ANY8H] = ".any8h",
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[BRW_PREDICATE_ALIGN1_ALL8H] = ".all8h",
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[BRW_PREDICATE_ALIGN1_ANY16H] = ".any16h",
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[BRW_PREDICATE_ALIGN1_ALL16H] = ".all16h",
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[BRW_PREDICATE_ALIGN1_ANY32H] = ".any32h",
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[BRW_PREDICATE_ALIGN1_ALL32H] = ".all32h",
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};
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static const char *const thread_ctrl[4] = {
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[BRW_THREAD_NORMAL] = "",
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[BRW_THREAD_ATOMIC] = "atomic",
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[BRW_THREAD_SWITCH] = "switch",
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};
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static const char *const compr_ctrl[4] = {
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[0] = "",
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[1] = "sechalf",
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[2] = "compr",
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[3] = "compr4",
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};
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static const char *const dep_ctrl[4] = {
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[0] = "",
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[1] = "NoDDClr",
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[2] = "NoDDChk",
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[3] = "NoDDClr,NoDDChk",
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};
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static const char *const mask_ctrl[4] = {
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[0] = "",
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[1] = "nomask",
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};
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static const char *const access_mode[2] = {
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[0] = "align1",
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[1] = "align16",
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};
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static const char *const reg_file[4] = {
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[0] = "A",
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[1] = "g",
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[2] = "m",
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[3] = "imm",
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};
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static const char *const writemask[16] = {
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[0x0] = ".",
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[0x1] = ".x",
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[0x2] = ".y",
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[0x3] = ".xy",
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[0x4] = ".z",
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[0x5] = ".xz",
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[0x6] = ".yz",
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[0x7] = ".xyz",
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[0x8] = ".w",
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[0x9] = ".xw",
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[0xa] = ".yw",
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[0xb] = ".xyw",
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[0xc] = ".zw",
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[0xd] = ".xzw",
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[0xe] = ".yzw",
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[0xf] = "",
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};
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static const char *const end_of_thread[2] = {
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[0] = "",
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[1] = "EOT"
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};
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/* SFIDs on Gfx4-5 */
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static const char *const gfx4_sfid[16] = {
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[BRW_SFID_NULL] = "null",
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[BRW_SFID_MATH] = "math",
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[BRW_SFID_SAMPLER] = "sampler",
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[BRW_SFID_MESSAGE_GATEWAY] = "gateway",
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[BRW_SFID_DATAPORT_READ] = "read",
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[BRW_SFID_DATAPORT_WRITE] = "write",
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[BRW_SFID_URB] = "urb",
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[BRW_SFID_THREAD_SPAWNER] = "thread_spawner",
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[BRW_SFID_VME] = "vme",
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};
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static const char *const gfx6_sfid[16] = {
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[BRW_SFID_NULL] = "null",
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[BRW_SFID_MATH] = "math",
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[BRW_SFID_SAMPLER] = "sampler",
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[BRW_SFID_MESSAGE_GATEWAY] = "gateway",
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[BRW_SFID_URB] = "urb",
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[BRW_SFID_THREAD_SPAWNER] = "thread_spawner",
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[GFX6_SFID_DATAPORT_SAMPLER_CACHE] = "dp_sampler",
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[GFX6_SFID_DATAPORT_RENDER_CACHE] = "render",
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[GFX6_SFID_DATAPORT_CONSTANT_CACHE] = "const",
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[GFX7_SFID_DATAPORT_DATA_CACHE] = "data",
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[GFX7_SFID_PIXEL_INTERPOLATOR] = "pixel interp",
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[HSW_SFID_DATAPORT_DATA_CACHE_1] = "dp data 1",
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[HSW_SFID_CRE] = "cre",
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[GEN_RT_SFID_RAY_TRACE_ACCELERATOR] = "rt accel",
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[GFX12_SFID_SLM] = "slm",
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[GFX12_SFID_TGM] = "tgm",
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[GFX12_SFID_UGM] = "ugm",
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};
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static const char *const gfx7_gateway_subfuncid[8] = {
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[BRW_MESSAGE_GATEWAY_SFID_OPEN_GATEWAY] = "open",
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[BRW_MESSAGE_GATEWAY_SFID_CLOSE_GATEWAY] = "close",
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[BRW_MESSAGE_GATEWAY_SFID_FORWARD_MSG] = "forward msg",
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[BRW_MESSAGE_GATEWAY_SFID_GET_TIMESTAMP] = "get timestamp",
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[BRW_MESSAGE_GATEWAY_SFID_BARRIER_MSG] = "barrier msg",
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[BRW_MESSAGE_GATEWAY_SFID_UPDATE_GATEWAY_STATE] = "update state",
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[BRW_MESSAGE_GATEWAY_SFID_MMIO_READ_WRITE] = "mmio read/write",
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};
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static const char *const gfx4_dp_read_port_msg_type[4] = {
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[0b00] = "OWord Block Read",
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[0b01] = "OWord Dual Block Read",
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[0b10] = "Media Block Read",
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[0b11] = "DWord Scattered Read",
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};
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static const char *const g45_dp_read_port_msg_type[8] = {
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[0b000] = "OWord Block Read",
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[0b010] = "OWord Dual Block Read",
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[0b100] = "Media Block Read",
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[0b110] = "DWord Scattered Read",
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[0b001] = "Render Target UNORM Read",
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[0b011] = "AVC Loop Filter Read",
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};
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static const char *const dp_write_port_msg_type[8] = {
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[0b000] = "OWord block write",
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[0b001] = "OWord dual block write",
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[0b010] = "media block write",
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[0b011] = "DWord scattered write",
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[0b100] = "RT write",
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[0b101] = "streamed VB write",
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[0b110] = "RT UNORM write", /* G45+ */
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[0b111] = "flush render cache",
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};
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static const char *const dp_rc_msg_type_gfx6[16] = {
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[BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ] = "OWORD block read",
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[GFX6_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ] = "RT UNORM read",
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[GFX6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ] = "OWORD dual block read",
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[GFX6_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ] = "media block read",
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[GFX6_DATAPORT_READ_MESSAGE_OWORD_UNALIGN_BLOCK_READ] =
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"OWORD unaligned block read",
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[GFX6_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ] = "DWORD scattered read",
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[GFX6_DATAPORT_WRITE_MESSAGE_DWORD_ATOMIC_WRITE] = "DWORD atomic write",
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[GFX6_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE] = "OWORD block write",
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[GFX6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE] =
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"OWORD dual block write",
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[GFX6_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE] = "media block write",
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[GFX6_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE] =
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"DWORD scattered write",
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[GFX6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE] = "RT write",
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[GFX6_DATAPORT_WRITE_MESSAGE_STREAMED_VB_WRITE] = "streamed VB write",
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[GFX6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_UNORM_WRITE] = "RT UNORM write",
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};
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static const char *const dp_rc_msg_type_gfx7[16] = {
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[GFX7_DATAPORT_RC_MEDIA_BLOCK_READ] = "media block read",
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[GFX7_DATAPORT_RC_TYPED_SURFACE_READ] = "typed surface read",
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[GFX7_DATAPORT_RC_TYPED_ATOMIC_OP] = "typed atomic op",
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[GFX7_DATAPORT_RC_MEMORY_FENCE] = "memory fence",
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[GFX7_DATAPORT_RC_MEDIA_BLOCK_WRITE] = "media block write",
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[GFX7_DATAPORT_RC_RENDER_TARGET_WRITE] = "RT write",
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[GFX7_DATAPORT_RC_TYPED_SURFACE_WRITE] = "typed surface write"
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};
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static const char *const dp_rc_msg_type_gfx9[16] = {
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[GFX9_DATAPORT_RC_RENDER_TARGET_WRITE] = "RT write",
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[GFX9_DATAPORT_RC_RENDER_TARGET_READ] = "RT read"
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};
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static const char *const *
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dp_rc_msg_type(const struct intel_device_info *devinfo)
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{
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return (devinfo->ver >= 9 ? dp_rc_msg_type_gfx9 :
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devinfo->ver >= 7 ? dp_rc_msg_type_gfx7 :
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devinfo->ver >= 6 ? dp_rc_msg_type_gfx6 :
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dp_write_port_msg_type);
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}
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static const char *const m_rt_write_subtype[] = {
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[0b000] = "SIMD16",
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[0b001] = "SIMD16/RepData",
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[0b010] = "SIMD8/DualSrcLow",
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[0b011] = "SIMD8/DualSrcHigh",
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[0b100] = "SIMD8",
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[0b101] = "SIMD8/ImageWrite", /* Gfx6+ */
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[0b111] = "SIMD16/RepData-111", /* no idea how this is different than 1 */
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};
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static const char *const dp_dc0_msg_type_gfx7[16] = {
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[GFX7_DATAPORT_DC_OWORD_BLOCK_READ] = "DC OWORD block read",
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[GFX7_DATAPORT_DC_UNALIGNED_OWORD_BLOCK_READ] =
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"DC unaligned OWORD block read",
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[GFX7_DATAPORT_DC_OWORD_DUAL_BLOCK_READ] = "DC OWORD dual block read",
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[GFX7_DATAPORT_DC_DWORD_SCATTERED_READ] = "DC DWORD scattered read",
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[GFX7_DATAPORT_DC_BYTE_SCATTERED_READ] = "DC byte scattered read",
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[GFX7_DATAPORT_DC_UNTYPED_SURFACE_READ] = "DC untyped surface read",
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[GFX7_DATAPORT_DC_UNTYPED_ATOMIC_OP] = "DC untyped atomic",
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[GFX7_DATAPORT_DC_MEMORY_FENCE] = "DC mfence",
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[GFX7_DATAPORT_DC_OWORD_BLOCK_WRITE] = "DC OWORD block write",
426
[GFX7_DATAPORT_DC_OWORD_DUAL_BLOCK_WRITE] = "DC OWORD dual block write",
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[GFX7_DATAPORT_DC_DWORD_SCATTERED_WRITE] = "DC DWORD scatterd write",
428
[GFX7_DATAPORT_DC_BYTE_SCATTERED_WRITE] = "DC byte scattered write",
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[GFX7_DATAPORT_DC_UNTYPED_SURFACE_WRITE] = "DC untyped surface write",
430
};
431
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static const char *const dp_oword_block_rw[8] = {
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[BRW_DATAPORT_OWORD_BLOCK_1_OWORDLOW] = "1-low",
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[BRW_DATAPORT_OWORD_BLOCK_1_OWORDHIGH] = "1-high",
435
[BRW_DATAPORT_OWORD_BLOCK_2_OWORDS] = "2",
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[BRW_DATAPORT_OWORD_BLOCK_4_OWORDS] = "4",
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[BRW_DATAPORT_OWORD_BLOCK_8_OWORDS] = "8",
438
};
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static const char *const dp_dc1_msg_type_hsw[32] = {
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[HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_READ] = "untyped surface read",
442
[HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP] = "DC untyped atomic op",
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[HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2] =
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"DC untyped 4x2 atomic op",
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[HSW_DATAPORT_DC_PORT1_MEDIA_BLOCK_READ] = "DC media block read",
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[HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_READ] = "DC typed surface read",
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[HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP] = "DC typed atomic",
448
[HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP_SIMD4X2] = "DC typed 4x2 atomic op",
449
[HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_WRITE] = "DC untyped surface write",
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[HSW_DATAPORT_DC_PORT1_MEDIA_BLOCK_WRITE] = "DC media block write",
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[HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP] = "DC atomic counter op",
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[HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP_SIMD4X2] =
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"DC 4x2 atomic counter op",
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[HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_WRITE] = "DC typed surface write",
455
[GFX9_DATAPORT_DC_PORT1_A64_SCATTERED_READ] = "DC A64 scattered read",
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[GFX8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_READ] = "DC A64 untyped surface read",
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[GFX8_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_OP] = "DC A64 untyped atomic op",
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[GFX9_DATAPORT_DC_PORT1_A64_OWORD_BLOCK_READ] = "DC A64 oword block read",
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[GFX9_DATAPORT_DC_PORT1_A64_OWORD_BLOCK_WRITE] = "DC A64 oword block write",
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[GFX8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_WRITE] = "DC A64 untyped surface write",
461
[GFX8_DATAPORT_DC_PORT1_A64_SCATTERED_WRITE] = "DC A64 scattered write",
462
[GFX9_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_FLOAT_OP] =
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"DC untyped atomic float op",
464
[GFX9_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_FLOAT_OP] =
465
"DC A64 untyped atomic float op",
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[GFX12_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_HALF_INT_OP] =
467
"DC A64 untyped atomic half-integer op",
468
[GFX12_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_HALF_FLOAT_OP] =
469
"DC A64 untyped atomic half-float op",
470
};
471
472
static const char *const aop[16] = {
473
[BRW_AOP_AND] = "and",
474
[BRW_AOP_OR] = "or",
475
[BRW_AOP_XOR] = "xor",
476
[BRW_AOP_MOV] = "mov",
477
[BRW_AOP_INC] = "inc",
478
[BRW_AOP_DEC] = "dec",
479
[BRW_AOP_ADD] = "add",
480
[BRW_AOP_SUB] = "sub",
481
[BRW_AOP_REVSUB] = "revsub",
482
[BRW_AOP_IMAX] = "imax",
483
[BRW_AOP_IMIN] = "imin",
484
[BRW_AOP_UMAX] = "umax",
485
[BRW_AOP_UMIN] = "umin",
486
[BRW_AOP_CMPWR] = "cmpwr",
487
[BRW_AOP_PREDEC] = "predec",
488
};
489
490
static const char *const aop_float[4] = {
491
[BRW_AOP_FMAX] = "fmax",
492
[BRW_AOP_FMIN] = "fmin",
493
[BRW_AOP_FCMPWR] = "fcmpwr",
494
};
495
496
static const char * const pixel_interpolator_msg_types[4] = {
497
[GFX7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET] = "per_message_offset",
498
[GFX7_PIXEL_INTERPOLATOR_LOC_SAMPLE] = "sample_position",
499
[GFX7_PIXEL_INTERPOLATOR_LOC_CENTROID] = "centroid",
500
[GFX7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET] = "per_slot_offset",
501
};
502
503
static const char *const math_function[16] = {
504
[BRW_MATH_FUNCTION_INV] = "inv",
505
[BRW_MATH_FUNCTION_LOG] = "log",
506
[BRW_MATH_FUNCTION_EXP] = "exp",
507
[BRW_MATH_FUNCTION_SQRT] = "sqrt",
508
[BRW_MATH_FUNCTION_RSQ] = "rsq",
509
[BRW_MATH_FUNCTION_SIN] = "sin",
510
[BRW_MATH_FUNCTION_COS] = "cos",
511
[BRW_MATH_FUNCTION_SINCOS] = "sincos",
512
[BRW_MATH_FUNCTION_FDIV] = "fdiv",
513
[BRW_MATH_FUNCTION_POW] = "pow",
514
[BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER] = "intdivmod",
515
[BRW_MATH_FUNCTION_INT_DIV_QUOTIENT] = "intdiv",
516
[BRW_MATH_FUNCTION_INT_DIV_REMAINDER] = "intmod",
517
[GFX8_MATH_FUNCTION_INVM] = "invm",
518
[GFX8_MATH_FUNCTION_RSQRTM] = "rsqrtm",
519
};
520
521
static const char *const sync_function[16] = {
522
[TGL_SYNC_NOP] = "nop",
523
[TGL_SYNC_ALLRD] = "allrd",
524
[TGL_SYNC_ALLWR] = "allwr",
525
[TGL_SYNC_BAR] = "bar",
526
[TGL_SYNC_HOST] = "host",
527
};
528
529
static const char *const math_saturate[2] = {
530
[0] = "",
531
[1] = "sat"
532
};
533
534
static const char *const math_signed[2] = {
535
[0] = "",
536
[1] = "signed"
537
};
538
539
static const char *const math_scalar[2] = {
540
[0] = "",
541
[1] = "scalar"
542
};
543
544
static const char *const math_precision[2] = {
545
[0] = "",
546
[1] = "partial_precision"
547
};
548
549
static const char *const gfx5_urb_opcode[] = {
550
[0] = "urb_write",
551
[1] = "ff_sync",
552
};
553
554
static const char *const gfx7_urb_opcode[] = {
555
[BRW_URB_OPCODE_WRITE_HWORD] = "write HWord",
556
[BRW_URB_OPCODE_WRITE_OWORD] = "write OWord",
557
[BRW_URB_OPCODE_READ_HWORD] = "read HWord",
558
[BRW_URB_OPCODE_READ_OWORD] = "read OWord",
559
[GFX7_URB_OPCODE_ATOMIC_MOV] = "atomic mov", /* Gfx7+ */
560
[GFX7_URB_OPCODE_ATOMIC_INC] = "atomic inc", /* Gfx7+ */
561
[GFX8_URB_OPCODE_ATOMIC_ADD] = "atomic add", /* Gfx8+ */
562
[GFX8_URB_OPCODE_SIMD8_WRITE] = "SIMD8 write", /* Gfx8+ */
563
[GFX8_URB_OPCODE_SIMD8_READ] = "SIMD8 read", /* Gfx8+ */
564
/* [9-15] - reserved */
565
};
566
567
static const char *const urb_swizzle[4] = {
568
[BRW_URB_SWIZZLE_NONE] = "",
569
[BRW_URB_SWIZZLE_INTERLEAVE] = "interleave",
570
[BRW_URB_SWIZZLE_TRANSPOSE] = "transpose",
571
};
572
573
static const char *const urb_allocate[2] = {
574
[0] = "",
575
[1] = "allocate"
576
};
577
578
static const char *const urb_used[2] = {
579
[0] = "",
580
[1] = "used"
581
};
582
583
static const char *const urb_complete[2] = {
584
[0] = "",
585
[1] = "complete"
586
};
587
588
static const char *const gfx5_sampler_msg_type[] = {
589
[GFX5_SAMPLER_MESSAGE_SAMPLE] = "sample",
590
[GFX5_SAMPLER_MESSAGE_SAMPLE_BIAS] = "sample_b",
591
[GFX5_SAMPLER_MESSAGE_SAMPLE_LOD] = "sample_l",
592
[GFX5_SAMPLER_MESSAGE_SAMPLE_COMPARE] = "sample_c",
593
[GFX5_SAMPLER_MESSAGE_SAMPLE_DERIVS] = "sample_d",
594
[GFX5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE] = "sample_b_c",
595
[GFX5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE] = "sample_l_c",
596
[GFX5_SAMPLER_MESSAGE_SAMPLE_LD] = "ld",
597
[GFX7_SAMPLER_MESSAGE_SAMPLE_GATHER4] = "gather4",
598
[GFX5_SAMPLER_MESSAGE_LOD] = "lod",
599
[GFX5_SAMPLER_MESSAGE_SAMPLE_RESINFO] = "resinfo",
600
[GFX6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO] = "sampleinfo",
601
[GFX7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C] = "gather4_c",
602
[GFX7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO] = "gather4_po",
603
[GFX7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C] = "gather4_po_c",
604
[HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE] = "sample_d_c",
605
[GFX9_SAMPLER_MESSAGE_SAMPLE_LZ] = "sample_lz",
606
[GFX9_SAMPLER_MESSAGE_SAMPLE_C_LZ] = "sample_c_lz",
607
[GFX9_SAMPLER_MESSAGE_SAMPLE_LD_LZ] = "ld_lz",
608
[GFX9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W] = "ld2dms_w",
609
[GFX7_SAMPLER_MESSAGE_SAMPLE_LD_MCS] = "ld_mcs",
610
[GFX7_SAMPLER_MESSAGE_SAMPLE_LD2DMS] = "ld2dms",
611
[GFX7_SAMPLER_MESSAGE_SAMPLE_LD2DSS] = "ld2dss",
612
};
613
614
static const char *const gfx5_sampler_simd_mode[4] = {
615
[BRW_SAMPLER_SIMD_MODE_SIMD4X2] = "SIMD4x2",
616
[BRW_SAMPLER_SIMD_MODE_SIMD8] = "SIMD8",
617
[BRW_SAMPLER_SIMD_MODE_SIMD16] = "SIMD16",
618
[BRW_SAMPLER_SIMD_MODE_SIMD32_64] = "SIMD32/64",
619
};
620
621
static const char *const sampler_target_format[4] = {
622
[0] = "F",
623
[2] = "UD",
624
[3] = "D"
625
};
626
627
static const char *const lsc_operation[] = {
628
[LSC_OP_LOAD] = "load",
629
[LSC_OP_LOAD_CMASK] = "load_cmask",
630
[LSC_OP_STORE] = "store",
631
[LSC_OP_STORE_CMASK] = "store_cmask",
632
[LSC_OP_FENCE] = "fence",
633
[LSC_OP_ATOMIC_INC] = "atomic_inc",
634
[LSC_OP_ATOMIC_DEC] = "atomic_dec",
635
[LSC_OP_ATOMIC_LOAD] = "atomic_load",
636
[LSC_OP_ATOMIC_STORE] = "atomic_store",
637
[LSC_OP_ATOMIC_ADD] = "atomic_add",
638
[LSC_OP_ATOMIC_SUB] = "atomic_sub",
639
[LSC_OP_ATOMIC_MIN] = "atomic_min",
640
[LSC_OP_ATOMIC_MAX] = "atomic_max",
641
[LSC_OP_ATOMIC_UMIN] = "atomic_umin",
642
[LSC_OP_ATOMIC_UMAX] = "atomic_umax",
643
[LSC_OP_ATOMIC_CMPXCHG] = "atomic_cmpxchg",
644
[LSC_OP_ATOMIC_FADD] = "atomic_fadd",
645
[LSC_OP_ATOMIC_FSUB] = "atomic_fsub",
646
[LSC_OP_ATOMIC_FMIN] = "atomic_fmin",
647
[LSC_OP_ATOMIC_FMAX] = "atomic_fmax",
648
[LSC_OP_ATOMIC_FCMPXCHG] = "atomic_fcmpxchg",
649
[LSC_OP_ATOMIC_AND] = "atomic_and",
650
[LSC_OP_ATOMIC_OR] = "atomic_or",
651
[LSC_OP_ATOMIC_XOR] = "atomic_xor",
652
};
653
654
static const char *const lsc_addr_surface_type[] = {
655
[LSC_ADDR_SURFTYPE_FLAT] = "flat",
656
[LSC_ADDR_SURFTYPE_BSS] = "bss",
657
[LSC_ADDR_SURFTYPE_SS] = "ss",
658
[LSC_ADDR_SURFTYPE_BTI] = "bti",
659
};
660
661
static const char* const lsc_fence_scope[] = {
662
[LSC_FENCE_THREADGROUP] = "threadgroup",
663
[LSC_FENCE_LOCAL] = "local",
664
[LSC_FENCE_TILE] = "tile",
665
[LSC_FENCE_GPU] = "gpu",
666
[LSC_FENCE_ALL_GPU] = "all_gpu",
667
[LSC_FENCE_SYSTEM_RELEASE] = "system_release",
668
[LSC_FENCE_SYSTEM_ACQUIRE] = "system_acquire",
669
};
670
671
static const char* const lsc_flush_type[] = {
672
[LSC_FLUSH_TYPE_NONE] = "none",
673
[LSC_FLUSH_TYPE_EVICT] = "evict",
674
[LSC_FLUSH_TYPE_INVALIDATE] = "invalidate",
675
[LSC_FLUSH_TYPE_DISCARD] = "discard",
676
[LSC_FLUSH_TYPE_CLEAN] = "clean",
677
[LSC_FLUSH_TYPE_L3ONLY] = "l3only",
678
};
679
680
static const char* const lsc_addr_size[] = {
681
[LSC_ADDR_SIZE_A16] = "a16",
682
[LSC_ADDR_SIZE_A32] = "a32",
683
[LSC_ADDR_SIZE_A64] = "a64",
684
};
685
686
static const char* const lsc_backup_fence_routing[] = {
687
[LSC_NORMAL_ROUTING] = "normal_routing",
688
[LSC_ROUTE_TO_LSC] = "route_to_lsc",
689
};
690
691
static const char* const lsc_data_size[] = {
692
[LSC_DATA_SIZE_D8] = "d8",
693
[LSC_DATA_SIZE_D16] = "d16",
694
[LSC_DATA_SIZE_D32] = "d32",
695
[LSC_DATA_SIZE_D64] = "d64",
696
[LSC_DATA_SIZE_D8U32] = "d8u32",
697
[LSC_DATA_SIZE_D16U32] = "d16u32",
698
[LSC_DATA_SIZE_D16BF32] = "d16bf32",
699
};
700
701
static const char* const lsc_vect_size_str[] = {
702
[LSC_VECT_SIZE_V1] = "V1",
703
[LSC_VECT_SIZE_V2] = "V2",
704
[LSC_VECT_SIZE_V3] = "V3",
705
[LSC_VECT_SIZE_V4] = "V4",
706
[LSC_VECT_SIZE_V8] = "V8",
707
[LSC_VECT_SIZE_V16] = "V16",
708
[LSC_VECT_SIZE_V32] = "V32",
709
[LSC_VECT_SIZE_V64] = "V64",
710
};
711
712
static const char* const lsc_cmask_str[] = {
713
[LSC_CMASK_X] = "x",
714
[LSC_CMASK_Y] = "y",
715
[LSC_CMASK_XY] = "xy",
716
[LSC_CMASK_Z] = "z",
717
[LSC_CMASK_XZ] = "xz",
718
[LSC_CMASK_YZ] = "yz",
719
[LSC_CMASK_XYZ] = "xyz",
720
[LSC_CMASK_W] = "w",
721
[LSC_CMASK_XW] = "xw",
722
[LSC_CMASK_YW] = "yw",
723
[LSC_CMASK_XYW] = "xyw",
724
[LSC_CMASK_ZW] = "zw",
725
[LSC_CMASK_XZW] = "xzw",
726
[LSC_CMASK_YZW] = "yzw",
727
[LSC_CMASK_XYZW] = "xyzw",
728
};
729
730
static const char* const lsc_cache_load[] = {
731
[LSC_CACHE_LOAD_L1STATE_L3MOCS] = "L1STATE_L3MOCS",
732
[LSC_CACHE_LOAD_L1UC_L3UC] = "L1UC_L3UC",
733
[LSC_CACHE_LOAD_L1UC_L3C] = "L1UC_L3C",
734
[LSC_CACHE_LOAD_L1C_L3UC] = "L1C_L3UC",
735
[LSC_CACHE_LOAD_L1C_L3C] = "L1C_L3C",
736
[LSC_CACHE_LOAD_L1S_L3UC] = "L1S_L3UC",
737
[LSC_CACHE_LOAD_L1S_L3C] = "L1S_L3C",
738
[LSC_CACHE_LOAD_L1IAR_L3C] = "L1IAR_L3C",
739
};
740
741
static const char* const lsc_cache_store[] = {
742
[LSC_CACHE_STORE_L1STATE_L3MOCS] = "L1STATE_L3MOCS",
743
[LSC_CACHE_STORE_L1UC_L3UC] = "L1UC_L3UC",
744
[LSC_CACHE_STORE_L1UC_L3WB] = "L1UC_L3WB",
745
[LSC_CACHE_STORE_L1WT_L3UC] = "L1WT_L3UC",
746
[LSC_CACHE_STORE_L1WT_L3WB] = "L1WT_L3WB",
747
[LSC_CACHE_STORE_L1S_L3UC] = "L1S_L3UC",
748
[LSC_CACHE_STORE_L1S_L3WB] = "L1S_L3WB",
749
[LSC_CACHE_STORE_L1WB_L3WB] = "L1WB_L3WB",
750
};
751
752
static int column;
753
754
static int
755
string(FILE *file, const char *string)
756
{
757
fputs(string, file);
758
column += strlen(string);
759
return 0;
760
}
761
762
static int
763
format(FILE *f, const char *format, ...) PRINTFLIKE(2, 3);
764
765
static int
766
format(FILE *f, const char *format, ...)
767
{
768
char buf[1024];
769
va_list args;
770
va_start(args, format);
771
772
vsnprintf(buf, sizeof(buf) - 1, format, args);
773
va_end(args);
774
string(f, buf);
775
return 0;
776
}
777
778
static int
779
newline(FILE *f)
780
{
781
putc('\n', f);
782
column = 0;
783
return 0;
784
}
785
786
static int
787
pad(FILE *f, int c)
788
{
789
do
790
string(f, " ");
791
while (column < c);
792
return 0;
793
}
794
795
static int
796
control(FILE *file, const char *name, const char *const ctrl[],
797
unsigned id, int *space)
798
{
799
if (!ctrl[id]) {
800
fprintf(file, "*** invalid %s value %d ", name, id);
801
return 1;
802
}
803
if (ctrl[id][0]) {
804
if (space && *space)
805
string(file, " ");
806
string(file, ctrl[id]);
807
if (space)
808
*space = 1;
809
}
810
return 0;
811
}
812
813
static int
814
print_opcode(FILE *file, const struct intel_device_info *devinfo,
815
enum opcode id)
816
{
817
const struct opcode_desc *desc = brw_opcode_desc(devinfo, id);
818
if (!desc) {
819
format(file, "*** invalid opcode value %d ", id);
820
return 1;
821
}
822
string(file, desc->name);
823
return 0;
824
}
825
826
static int
827
reg(FILE *file, unsigned _reg_file, unsigned _reg_nr)
828
{
829
int err = 0;
830
831
/* Clear the Compr4 instruction compression bit. */
832
if (_reg_file == BRW_MESSAGE_REGISTER_FILE)
833
_reg_nr &= ~BRW_MRF_COMPR4;
834
835
if (_reg_file == BRW_ARCHITECTURE_REGISTER_FILE) {
836
switch (_reg_nr & 0xf0) {
837
case BRW_ARF_NULL:
838
string(file, "null");
839
break;
840
case BRW_ARF_ADDRESS:
841
format(file, "a%d", _reg_nr & 0x0f);
842
break;
843
case BRW_ARF_ACCUMULATOR:
844
format(file, "acc%d", _reg_nr & 0x0f);
845
break;
846
case BRW_ARF_FLAG:
847
format(file, "f%d", _reg_nr & 0x0f);
848
break;
849
case BRW_ARF_MASK:
850
format(file, "mask%d", _reg_nr & 0x0f);
851
break;
852
case BRW_ARF_MASK_STACK:
853
format(file, "ms%d", _reg_nr & 0x0f);
854
break;
855
case BRW_ARF_MASK_STACK_DEPTH:
856
format(file, "msd%d", _reg_nr & 0x0f);
857
break;
858
case BRW_ARF_STATE:
859
format(file, "sr%d", _reg_nr & 0x0f);
860
break;
861
case BRW_ARF_CONTROL:
862
format(file, "cr%d", _reg_nr & 0x0f);
863
break;
864
case BRW_ARF_NOTIFICATION_COUNT:
865
format(file, "n%d", _reg_nr & 0x0f);
866
break;
867
case BRW_ARF_IP:
868
string(file, "ip");
869
return -1;
870
break;
871
case BRW_ARF_TDR:
872
format(file, "tdr0");
873
return -1;
874
case BRW_ARF_TIMESTAMP:
875
format(file, "tm%d", _reg_nr & 0x0f);
876
break;
877
default:
878
format(file, "ARF%d", _reg_nr);
879
break;
880
}
881
} else {
882
err |= control(file, "src reg file", reg_file, _reg_file, NULL);
883
format(file, "%d", _reg_nr);
884
}
885
return err;
886
}
887
888
static int
889
dest(FILE *file, const struct intel_device_info *devinfo, const brw_inst *inst)
890
{
891
enum brw_reg_type type = brw_inst_dst_type(devinfo, inst);
892
unsigned elem_size = brw_reg_type_to_size(type);
893
int err = 0;
894
895
if (is_split_send(devinfo, brw_inst_opcode(devinfo, inst))) {
896
/* These are fixed for split sends */
897
type = BRW_REGISTER_TYPE_UD;
898
elem_size = 4;
899
if (devinfo->ver >= 12) {
900
err |= reg(file, brw_inst_send_dst_reg_file(devinfo, inst),
901
brw_inst_dst_da_reg_nr(devinfo, inst));
902
string(file, brw_reg_type_to_letters(type));
903
} else if (brw_inst_dst_address_mode(devinfo, inst) == BRW_ADDRESS_DIRECT) {
904
err |= reg(file, brw_inst_send_dst_reg_file(devinfo, inst),
905
brw_inst_dst_da_reg_nr(devinfo, inst));
906
unsigned subreg_nr = brw_inst_dst_da16_subreg_nr(devinfo, inst);
907
if (subreg_nr)
908
format(file, ".%u", subreg_nr);
909
string(file, brw_reg_type_to_letters(type));
910
} else {
911
string(file, "g[a0");
912
if (brw_inst_dst_ia_subreg_nr(devinfo, inst))
913
format(file, ".%"PRIu64, brw_inst_dst_ia_subreg_nr(devinfo, inst) /
914
elem_size);
915
if (brw_inst_send_dst_ia16_addr_imm(devinfo, inst))
916
format(file, " %d", brw_inst_send_dst_ia16_addr_imm(devinfo, inst));
917
string(file, "]<");
918
string(file, brw_reg_type_to_letters(type));
919
}
920
} else if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
921
if (brw_inst_dst_address_mode(devinfo, inst) == BRW_ADDRESS_DIRECT) {
922
err |= reg(file, brw_inst_dst_reg_file(devinfo, inst),
923
brw_inst_dst_da_reg_nr(devinfo, inst));
924
if (err == -1)
925
return 0;
926
if (brw_inst_dst_da1_subreg_nr(devinfo, inst))
927
format(file, ".%"PRIu64, brw_inst_dst_da1_subreg_nr(devinfo, inst) /
928
elem_size);
929
string(file, "<");
930
err |= control(file, "horiz stride", horiz_stride,
931
brw_inst_dst_hstride(devinfo, inst), NULL);
932
string(file, ">");
933
string(file, brw_reg_type_to_letters(type));
934
} else {
935
string(file, "g[a0");
936
if (brw_inst_dst_ia_subreg_nr(devinfo, inst))
937
format(file, ".%"PRIu64, brw_inst_dst_ia_subreg_nr(devinfo, inst) /
938
elem_size);
939
if (brw_inst_dst_ia1_addr_imm(devinfo, inst))
940
format(file, " %d", brw_inst_dst_ia1_addr_imm(devinfo, inst));
941
string(file, "]<");
942
err |= control(file, "horiz stride", horiz_stride,
943
brw_inst_dst_hstride(devinfo, inst), NULL);
944
string(file, ">");
945
string(file, brw_reg_type_to_letters(type));
946
}
947
} else {
948
if (brw_inst_dst_address_mode(devinfo, inst) == BRW_ADDRESS_DIRECT) {
949
err |= reg(file, brw_inst_dst_reg_file(devinfo, inst),
950
brw_inst_dst_da_reg_nr(devinfo, inst));
951
if (err == -1)
952
return 0;
953
if (brw_inst_dst_da16_subreg_nr(devinfo, inst))
954
format(file, ".%u", 16 / elem_size);
955
string(file, "<1>");
956
err |= control(file, "writemask", writemask,
957
brw_inst_da16_writemask(devinfo, inst), NULL);
958
string(file, brw_reg_type_to_letters(type));
959
} else {
960
err = 1;
961
string(file, "Indirect align16 address mode not supported");
962
}
963
}
964
965
return 0;
966
}
967
968
static int
969
dest_3src(FILE *file, const struct intel_device_info *devinfo,
970
const brw_inst *inst)
971
{
972
bool is_align1 = brw_inst_3src_access_mode(devinfo, inst) == BRW_ALIGN_1;
973
int err = 0;
974
uint32_t reg_file;
975
unsigned subreg_nr;
976
enum brw_reg_type type;
977
978
if (devinfo->ver < 10 && is_align1)
979
return 0;
980
981
if (devinfo->ver == 6 && brw_inst_3src_a16_dst_reg_file(devinfo, inst))
982
reg_file = BRW_MESSAGE_REGISTER_FILE;
983
else if (devinfo->ver >= 12)
984
reg_file = brw_inst_3src_a1_dst_reg_file(devinfo, inst);
985
else if (is_align1 && brw_inst_3src_a1_dst_reg_file(devinfo, inst))
986
reg_file = BRW_ARCHITECTURE_REGISTER_FILE;
987
else
988
reg_file = BRW_GENERAL_REGISTER_FILE;
989
990
err |= reg(file, reg_file, brw_inst_3src_dst_reg_nr(devinfo, inst));
991
if (err == -1)
992
return 0;
993
994
if (is_align1) {
995
type = brw_inst_3src_a1_dst_type(devinfo, inst);
996
subreg_nr = brw_inst_3src_a1_dst_subreg_nr(devinfo, inst);
997
} else {
998
type = brw_inst_3src_a16_dst_type(devinfo, inst);
999
subreg_nr = brw_inst_3src_a16_dst_subreg_nr(devinfo, inst) * 4;
1000
}
1001
subreg_nr /= brw_reg_type_to_size(type);
1002
1003
if (subreg_nr)
1004
format(file, ".%u", subreg_nr);
1005
string(file, "<1>");
1006
1007
if (!is_align1) {
1008
err |= control(file, "writemask", writemask,
1009
brw_inst_3src_a16_dst_writemask(devinfo, inst), NULL);
1010
}
1011
string(file, brw_reg_type_to_letters(type));
1012
1013
return 0;
1014
}
1015
1016
static int
1017
src_align1_region(FILE *file,
1018
unsigned _vert_stride, unsigned _width,
1019
unsigned _horiz_stride)
1020
{
1021
int err = 0;
1022
string(file, "<");
1023
err |= control(file, "vert stride", vert_stride, _vert_stride, NULL);
1024
string(file, ",");
1025
err |= control(file, "width", width, _width, NULL);
1026
string(file, ",");
1027
err |= control(file, "horiz_stride", horiz_stride, _horiz_stride, NULL);
1028
string(file, ">");
1029
return err;
1030
}
1031
1032
static int
1033
src_da1(FILE *file,
1034
const struct intel_device_info *devinfo,
1035
unsigned opcode,
1036
enum brw_reg_type type, unsigned _reg_file,
1037
unsigned _vert_stride, unsigned _width, unsigned _horiz_stride,
1038
unsigned reg_num, unsigned sub_reg_num, unsigned __abs,
1039
unsigned _negate)
1040
{
1041
int err = 0;
1042
1043
if (devinfo->ver >= 8 && is_logic_instruction(opcode))
1044
err |= control(file, "bitnot", m_bitnot, _negate, NULL);
1045
else
1046
err |= control(file, "negate", m_negate, _negate, NULL);
1047
1048
err |= control(file, "abs", _abs, __abs, NULL);
1049
1050
err |= reg(file, _reg_file, reg_num);
1051
if (err == -1)
1052
return 0;
1053
if (sub_reg_num) {
1054
unsigned elem_size = brw_reg_type_to_size(type);
1055
format(file, ".%d", sub_reg_num / elem_size); /* use formal style like spec */
1056
}
1057
src_align1_region(file, _vert_stride, _width, _horiz_stride);
1058
string(file, brw_reg_type_to_letters(type));
1059
return err;
1060
}
1061
1062
static int
1063
src_ia1(FILE *file,
1064
const struct intel_device_info *devinfo,
1065
unsigned opcode,
1066
enum brw_reg_type type,
1067
int _addr_imm,
1068
unsigned _addr_subreg_nr,
1069
unsigned _negate,
1070
unsigned __abs,
1071
unsigned _horiz_stride, unsigned _width, unsigned _vert_stride)
1072
{
1073
int err = 0;
1074
1075
if (devinfo->ver >= 8 && is_logic_instruction(opcode))
1076
err |= control(file, "bitnot", m_bitnot, _negate, NULL);
1077
else
1078
err |= control(file, "negate", m_negate, _negate, NULL);
1079
1080
err |= control(file, "abs", _abs, __abs, NULL);
1081
1082
string(file, "g[a0");
1083
if (_addr_subreg_nr)
1084
format(file, ".%d", _addr_subreg_nr);
1085
if (_addr_imm)
1086
format(file, " %d", _addr_imm);
1087
string(file, "]");
1088
src_align1_region(file, _vert_stride, _width, _horiz_stride);
1089
string(file, brw_reg_type_to_letters(type));
1090
return err;
1091
}
1092
1093
static int
1094
src_swizzle(FILE *file, unsigned swiz)
1095
{
1096
unsigned x = BRW_GET_SWZ(swiz, BRW_CHANNEL_X);
1097
unsigned y = BRW_GET_SWZ(swiz, BRW_CHANNEL_Y);
1098
unsigned z = BRW_GET_SWZ(swiz, BRW_CHANNEL_Z);
1099
unsigned w = BRW_GET_SWZ(swiz, BRW_CHANNEL_W);
1100
int err = 0;
1101
1102
if (x == y && x == z && x == w) {
1103
string(file, ".");
1104
err |= control(file, "channel select", chan_sel, x, NULL);
1105
} else if (swiz != BRW_SWIZZLE_XYZW) {
1106
string(file, ".");
1107
err |= control(file, "channel select", chan_sel, x, NULL);
1108
err |= control(file, "channel select", chan_sel, y, NULL);
1109
err |= control(file, "channel select", chan_sel, z, NULL);
1110
err |= control(file, "channel select", chan_sel, w, NULL);
1111
}
1112
return err;
1113
}
1114
1115
static int
1116
src_da16(FILE *file,
1117
const struct intel_device_info *devinfo,
1118
unsigned opcode,
1119
enum brw_reg_type type,
1120
unsigned _reg_file,
1121
unsigned _vert_stride,
1122
unsigned _reg_nr,
1123
unsigned _subreg_nr,
1124
unsigned __abs,
1125
unsigned _negate,
1126
unsigned swz_x, unsigned swz_y, unsigned swz_z, unsigned swz_w)
1127
{
1128
int err = 0;
1129
1130
if (devinfo->ver >= 8 && is_logic_instruction(opcode))
1131
err |= control(file, "bitnot", m_bitnot, _negate, NULL);
1132
else
1133
err |= control(file, "negate", m_negate, _negate, NULL);
1134
1135
err |= control(file, "abs", _abs, __abs, NULL);
1136
1137
err |= reg(file, _reg_file, _reg_nr);
1138
if (err == -1)
1139
return 0;
1140
if (_subreg_nr) {
1141
unsigned elem_size = brw_reg_type_to_size(type);
1142
1143
/* bit4 for subreg number byte addressing. Make this same meaning as
1144
in da1 case, so output looks consistent. */
1145
format(file, ".%d", 16 / elem_size);
1146
}
1147
string(file, "<");
1148
err |= control(file, "vert stride", vert_stride, _vert_stride, NULL);
1149
string(file, ">");
1150
err |= src_swizzle(file, BRW_SWIZZLE4(swz_x, swz_y, swz_z, swz_w));
1151
string(file, brw_reg_type_to_letters(type));
1152
return err;
1153
}
1154
1155
static enum brw_vertical_stride
1156
vstride_from_align1_3src_vstride(const struct intel_device_info *devinfo,
1157
enum gfx10_align1_3src_vertical_stride vstride)
1158
{
1159
switch (vstride) {
1160
case BRW_ALIGN1_3SRC_VERTICAL_STRIDE_0: return BRW_VERTICAL_STRIDE_0;
1161
case BRW_ALIGN1_3SRC_VERTICAL_STRIDE_2:
1162
if (devinfo->ver >= 12)
1163
return BRW_VERTICAL_STRIDE_1;
1164
else
1165
return BRW_VERTICAL_STRIDE_2;
1166
case BRW_ALIGN1_3SRC_VERTICAL_STRIDE_4: return BRW_VERTICAL_STRIDE_4;
1167
case BRW_ALIGN1_3SRC_VERTICAL_STRIDE_8: return BRW_VERTICAL_STRIDE_8;
1168
default:
1169
unreachable("not reached");
1170
}
1171
}
1172
1173
static enum brw_horizontal_stride
1174
hstride_from_align1_3src_hstride(enum gfx10_align1_3src_src_horizontal_stride hstride)
1175
{
1176
switch (hstride) {
1177
case BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_0: return BRW_HORIZONTAL_STRIDE_0;
1178
case BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_1: return BRW_HORIZONTAL_STRIDE_1;
1179
case BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_2: return BRW_HORIZONTAL_STRIDE_2;
1180
case BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_4: return BRW_HORIZONTAL_STRIDE_4;
1181
default:
1182
unreachable("not reached");
1183
}
1184
}
1185
1186
static enum brw_vertical_stride
1187
vstride_from_align1_3src_hstride(enum gfx10_align1_3src_src_horizontal_stride hstride)
1188
{
1189
switch (hstride) {
1190
case BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_0: return BRW_VERTICAL_STRIDE_0;
1191
case BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_1: return BRW_VERTICAL_STRIDE_1;
1192
case BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_2: return BRW_VERTICAL_STRIDE_2;
1193
case BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_4: return BRW_VERTICAL_STRIDE_4;
1194
default:
1195
unreachable("not reached");
1196
}
1197
}
1198
1199
/* From "GFX10 Regioning Rules for Align1 Ternary Operations" in the
1200
* "Register Region Restrictions" documentation
1201
*/
1202
static enum brw_width
1203
implied_width(enum brw_vertical_stride _vert_stride,
1204
enum brw_horizontal_stride _horiz_stride)
1205
{
1206
/* "1. Width is 1 when Vertical and Horizontal Strides are both zero." */
1207
if (_vert_stride == BRW_VERTICAL_STRIDE_0 &&
1208
_horiz_stride == BRW_HORIZONTAL_STRIDE_0) {
1209
return BRW_WIDTH_1;
1210
1211
/* "2. Width is equal to vertical stride when Horizontal Stride is zero." */
1212
} else if (_horiz_stride == BRW_HORIZONTAL_STRIDE_0) {
1213
switch (_vert_stride) {
1214
case BRW_VERTICAL_STRIDE_2: return BRW_WIDTH_2;
1215
case BRW_VERTICAL_STRIDE_4: return BRW_WIDTH_4;
1216
case BRW_VERTICAL_STRIDE_8: return BRW_WIDTH_8;
1217
case BRW_VERTICAL_STRIDE_0:
1218
default:
1219
unreachable("not reached");
1220
}
1221
1222
} else {
1223
/* FINISHME: Implement these: */
1224
1225
/* "3. Width is equal to Vertical Stride/Horizontal Stride when both
1226
* Strides are non-zero.
1227
*
1228
* 4. Vertical Stride must not be zero if Horizontal Stride is non-zero.
1229
* This implies Vertical Stride is always greater than Horizontal
1230
* Stride."
1231
*
1232
* Given these statements and the knowledge that the stride and width
1233
* values are encoded in logarithmic form, we can perform the division
1234
* by just subtracting.
1235
*/
1236
return _vert_stride - _horiz_stride;
1237
}
1238
}
1239
1240
static int
1241
src0_3src(FILE *file, const struct intel_device_info *devinfo,
1242
const brw_inst *inst)
1243
{
1244
int err = 0;
1245
unsigned reg_nr, subreg_nr;
1246
enum brw_reg_file _file;
1247
enum brw_reg_type type;
1248
enum brw_vertical_stride _vert_stride;
1249
enum brw_width _width;
1250
enum brw_horizontal_stride _horiz_stride;
1251
bool is_scalar_region;
1252
bool is_align1 = brw_inst_3src_access_mode(devinfo, inst) == BRW_ALIGN_1;
1253
1254
if (devinfo->ver < 10 && is_align1)
1255
return 0;
1256
1257
if (is_align1) {
1258
if (devinfo->ver >= 12 && !brw_inst_3src_a1_src0_is_imm(devinfo, inst)) {
1259
_file = brw_inst_3src_a1_src0_reg_file(devinfo, inst);
1260
} else if (brw_inst_3src_a1_src0_reg_file(devinfo, inst) ==
1261
BRW_ALIGN1_3SRC_GENERAL_REGISTER_FILE) {
1262
_file = BRW_GENERAL_REGISTER_FILE;
1263
} else if (brw_inst_3src_a1_src0_type(devinfo, inst) ==
1264
BRW_REGISTER_TYPE_NF) {
1265
_file = BRW_ARCHITECTURE_REGISTER_FILE;
1266
} else {
1267
_file = BRW_IMMEDIATE_VALUE;
1268
uint16_t imm_val = brw_inst_3src_a1_src0_imm(devinfo, inst);
1269
enum brw_reg_type type = brw_inst_3src_a1_src0_type(devinfo, inst);
1270
1271
if (type == BRW_REGISTER_TYPE_W) {
1272
format(file, "%dW", imm_val);
1273
} else if (type == BRW_REGISTER_TYPE_UW) {
1274
format(file, "0x%04xUW", imm_val);
1275
} else if (type == BRW_REGISTER_TYPE_HF) {
1276
format(file, "0x%04xHF", imm_val);
1277
}
1278
return 0;
1279
}
1280
1281
reg_nr = brw_inst_3src_src0_reg_nr(devinfo, inst);
1282
subreg_nr = brw_inst_3src_a1_src0_subreg_nr(devinfo, inst);
1283
type = brw_inst_3src_a1_src0_type(devinfo, inst);
1284
_vert_stride = vstride_from_align1_3src_vstride(
1285
devinfo, brw_inst_3src_a1_src0_vstride(devinfo, inst));
1286
_horiz_stride = hstride_from_align1_3src_hstride(
1287
brw_inst_3src_a1_src0_hstride(devinfo, inst));
1288
_width = implied_width(_vert_stride, _horiz_stride);
1289
} else {
1290
_file = BRW_GENERAL_REGISTER_FILE;
1291
reg_nr = brw_inst_3src_src0_reg_nr(devinfo, inst);
1292
subreg_nr = brw_inst_3src_a16_src0_subreg_nr(devinfo, inst) * 4;
1293
type = brw_inst_3src_a16_src_type(devinfo, inst);
1294
1295
if (brw_inst_3src_a16_src0_rep_ctrl(devinfo, inst)) {
1296
_vert_stride = BRW_VERTICAL_STRIDE_0;
1297
_width = BRW_WIDTH_1;
1298
_horiz_stride = BRW_HORIZONTAL_STRIDE_0;
1299
} else {
1300
_vert_stride = BRW_VERTICAL_STRIDE_4;
1301
_width = BRW_WIDTH_4;
1302
_horiz_stride = BRW_HORIZONTAL_STRIDE_1;
1303
}
1304
}
1305
is_scalar_region = _vert_stride == BRW_VERTICAL_STRIDE_0 &&
1306
_width == BRW_WIDTH_1 &&
1307
_horiz_stride == BRW_HORIZONTAL_STRIDE_0;
1308
1309
subreg_nr /= brw_reg_type_to_size(type);
1310
1311
err |= control(file, "negate", m_negate,
1312
brw_inst_3src_src0_negate(devinfo, inst), NULL);
1313
err |= control(file, "abs", _abs, brw_inst_3src_src0_abs(devinfo, inst), NULL);
1314
1315
err |= reg(file, _file, reg_nr);
1316
if (err == -1)
1317
return 0;
1318
if (subreg_nr || is_scalar_region)
1319
format(file, ".%d", subreg_nr);
1320
src_align1_region(file, _vert_stride, _width, _horiz_stride);
1321
if (!is_scalar_region && !is_align1)
1322
err |= src_swizzle(file, brw_inst_3src_a16_src0_swizzle(devinfo, inst));
1323
string(file, brw_reg_type_to_letters(type));
1324
return err;
1325
}
1326
1327
static int
1328
src1_3src(FILE *file, const struct intel_device_info *devinfo,
1329
const brw_inst *inst)
1330
{
1331
int err = 0;
1332
unsigned reg_nr, subreg_nr;
1333
enum brw_reg_file _file;
1334
enum brw_reg_type type;
1335
enum brw_vertical_stride _vert_stride;
1336
enum brw_width _width;
1337
enum brw_horizontal_stride _horiz_stride;
1338
bool is_scalar_region;
1339
bool is_align1 = brw_inst_3src_access_mode(devinfo, inst) == BRW_ALIGN_1;
1340
1341
if (devinfo->ver < 10 && is_align1)
1342
return 0;
1343
1344
if (is_align1) {
1345
if (devinfo->ver >= 12) {
1346
_file = brw_inst_3src_a1_src1_reg_file(devinfo, inst);
1347
} else if (brw_inst_3src_a1_src1_reg_file(devinfo, inst) ==
1348
BRW_ALIGN1_3SRC_GENERAL_REGISTER_FILE) {
1349
_file = BRW_GENERAL_REGISTER_FILE;
1350
} else {
1351
_file = BRW_ARCHITECTURE_REGISTER_FILE;
1352
}
1353
1354
reg_nr = brw_inst_3src_src1_reg_nr(devinfo, inst);
1355
subreg_nr = brw_inst_3src_a1_src1_subreg_nr(devinfo, inst);
1356
type = brw_inst_3src_a1_src1_type(devinfo, inst);
1357
1358
_vert_stride = vstride_from_align1_3src_vstride(
1359
devinfo, brw_inst_3src_a1_src1_vstride(devinfo, inst));
1360
_horiz_stride = hstride_from_align1_3src_hstride(
1361
brw_inst_3src_a1_src1_hstride(devinfo, inst));
1362
_width = implied_width(_vert_stride, _horiz_stride);
1363
} else {
1364
_file = BRW_GENERAL_REGISTER_FILE;
1365
reg_nr = brw_inst_3src_src1_reg_nr(devinfo, inst);
1366
subreg_nr = brw_inst_3src_a16_src1_subreg_nr(devinfo, inst) * 4;
1367
type = brw_inst_3src_a16_src_type(devinfo, inst);
1368
1369
if (brw_inst_3src_a16_src1_rep_ctrl(devinfo, inst)) {
1370
_vert_stride = BRW_VERTICAL_STRIDE_0;
1371
_width = BRW_WIDTH_1;
1372
_horiz_stride = BRW_HORIZONTAL_STRIDE_0;
1373
} else {
1374
_vert_stride = BRW_VERTICAL_STRIDE_4;
1375
_width = BRW_WIDTH_4;
1376
_horiz_stride = BRW_HORIZONTAL_STRIDE_1;
1377
}
1378
}
1379
is_scalar_region = _vert_stride == BRW_VERTICAL_STRIDE_0 &&
1380
_width == BRW_WIDTH_1 &&
1381
_horiz_stride == BRW_HORIZONTAL_STRIDE_0;
1382
1383
subreg_nr /= brw_reg_type_to_size(type);
1384
1385
err |= control(file, "negate", m_negate,
1386
brw_inst_3src_src1_negate(devinfo, inst), NULL);
1387
err |= control(file, "abs", _abs, brw_inst_3src_src1_abs(devinfo, inst), NULL);
1388
1389
err |= reg(file, _file, reg_nr);
1390
if (err == -1)
1391
return 0;
1392
if (subreg_nr || is_scalar_region)
1393
format(file, ".%d", subreg_nr);
1394
src_align1_region(file, _vert_stride, _width, _horiz_stride);
1395
if (!is_scalar_region && !is_align1)
1396
err |= src_swizzle(file, brw_inst_3src_a16_src1_swizzle(devinfo, inst));
1397
string(file, brw_reg_type_to_letters(type));
1398
return err;
1399
}
1400
1401
static int
1402
src2_3src(FILE *file, const struct intel_device_info *devinfo,
1403
const brw_inst *inst)
1404
{
1405
int err = 0;
1406
unsigned reg_nr, subreg_nr;
1407
enum brw_reg_file _file;
1408
enum brw_reg_type type;
1409
enum brw_vertical_stride _vert_stride;
1410
enum brw_width _width;
1411
enum brw_horizontal_stride _horiz_stride;
1412
bool is_scalar_region;
1413
bool is_align1 = brw_inst_3src_access_mode(devinfo, inst) == BRW_ALIGN_1;
1414
1415
if (devinfo->ver < 10 && is_align1)
1416
return 0;
1417
1418
if (is_align1) {
1419
if (devinfo->ver >= 12 && !brw_inst_3src_a1_src2_is_imm(devinfo, inst)) {
1420
_file = brw_inst_3src_a1_src2_reg_file(devinfo, inst);
1421
} else if (brw_inst_3src_a1_src2_reg_file(devinfo, inst) ==
1422
BRW_ALIGN1_3SRC_GENERAL_REGISTER_FILE) {
1423
_file = BRW_GENERAL_REGISTER_FILE;
1424
} else {
1425
_file = BRW_IMMEDIATE_VALUE;
1426
uint16_t imm_val = brw_inst_3src_a1_src2_imm(devinfo, inst);
1427
enum brw_reg_type type = brw_inst_3src_a1_src2_type(devinfo, inst);
1428
1429
if (type == BRW_REGISTER_TYPE_W) {
1430
format(file, "%dW", imm_val);
1431
} else if (type == BRW_REGISTER_TYPE_UW) {
1432
format(file, "0x%04xUW", imm_val);
1433
} else if (type == BRW_REGISTER_TYPE_HF) {
1434
format(file, "0x%04xHF", imm_val);
1435
}
1436
return 0;
1437
}
1438
1439
reg_nr = brw_inst_3src_src2_reg_nr(devinfo, inst);
1440
subreg_nr = brw_inst_3src_a1_src2_subreg_nr(devinfo, inst);
1441
type = brw_inst_3src_a1_src2_type(devinfo, inst);
1442
/* FINISHME: No vertical stride on src2. Is using the hstride in place
1443
* correct? Doesn't seem like it, since there's hstride=1 but
1444
* no vstride=1.
1445
*/
1446
_vert_stride = vstride_from_align1_3src_hstride(
1447
brw_inst_3src_a1_src2_hstride(devinfo, inst));
1448
_horiz_stride = hstride_from_align1_3src_hstride(
1449
brw_inst_3src_a1_src2_hstride(devinfo, inst));
1450
_width = implied_width(_vert_stride, _horiz_stride);
1451
} else {
1452
_file = BRW_GENERAL_REGISTER_FILE;
1453
reg_nr = brw_inst_3src_src2_reg_nr(devinfo, inst);
1454
subreg_nr = brw_inst_3src_a16_src2_subreg_nr(devinfo, inst) * 4;
1455
type = brw_inst_3src_a16_src_type(devinfo, inst);
1456
1457
if (brw_inst_3src_a16_src2_rep_ctrl(devinfo, inst)) {
1458
_vert_stride = BRW_VERTICAL_STRIDE_0;
1459
_width = BRW_WIDTH_1;
1460
_horiz_stride = BRW_HORIZONTAL_STRIDE_0;
1461
} else {
1462
_vert_stride = BRW_VERTICAL_STRIDE_4;
1463
_width = BRW_WIDTH_4;
1464
_horiz_stride = BRW_HORIZONTAL_STRIDE_1;
1465
}
1466
}
1467
is_scalar_region = _vert_stride == BRW_VERTICAL_STRIDE_0 &&
1468
_width == BRW_WIDTH_1 &&
1469
_horiz_stride == BRW_HORIZONTAL_STRIDE_0;
1470
1471
subreg_nr /= brw_reg_type_to_size(type);
1472
1473
err |= control(file, "negate", m_negate,
1474
brw_inst_3src_src2_negate(devinfo, inst), NULL);
1475
err |= control(file, "abs", _abs, brw_inst_3src_src2_abs(devinfo, inst), NULL);
1476
1477
err |= reg(file, _file, reg_nr);
1478
if (err == -1)
1479
return 0;
1480
if (subreg_nr || is_scalar_region)
1481
format(file, ".%d", subreg_nr);
1482
src_align1_region(file, _vert_stride, _width, _horiz_stride);
1483
if (!is_scalar_region && !is_align1)
1484
err |= src_swizzle(file, brw_inst_3src_a16_src2_swizzle(devinfo, inst));
1485
string(file, brw_reg_type_to_letters(type));
1486
return err;
1487
}
1488
1489
static int
1490
imm(FILE *file, const struct intel_device_info *devinfo, enum brw_reg_type type,
1491
const brw_inst *inst)
1492
{
1493
switch (type) {
1494
case BRW_REGISTER_TYPE_UQ:
1495
format(file, "0x%016"PRIx64"UQ", brw_inst_imm_uq(devinfo, inst));
1496
break;
1497
case BRW_REGISTER_TYPE_Q:
1498
format(file, "0x%016"PRIx64"Q", brw_inst_imm_uq(devinfo, inst));
1499
break;
1500
case BRW_REGISTER_TYPE_UD:
1501
format(file, "0x%08xUD", brw_inst_imm_ud(devinfo, inst));
1502
break;
1503
case BRW_REGISTER_TYPE_D:
1504
format(file, "%dD", brw_inst_imm_d(devinfo, inst));
1505
break;
1506
case BRW_REGISTER_TYPE_UW:
1507
format(file, "0x%04xUW", (uint16_t) brw_inst_imm_ud(devinfo, inst));
1508
break;
1509
case BRW_REGISTER_TYPE_W:
1510
format(file, "%dW", (int16_t) brw_inst_imm_d(devinfo, inst));
1511
break;
1512
case BRW_REGISTER_TYPE_UV:
1513
format(file, "0x%08xUV", brw_inst_imm_ud(devinfo, inst));
1514
break;
1515
case BRW_REGISTER_TYPE_VF:
1516
format(file, "0x%"PRIx64"VF", brw_inst_bits(inst, 127, 96));
1517
pad(file, 48);
1518
format(file, "/* [%-gF, %-gF, %-gF, %-gF]VF */",
1519
brw_vf_to_float(brw_inst_imm_ud(devinfo, inst)),
1520
brw_vf_to_float(brw_inst_imm_ud(devinfo, inst) >> 8),
1521
brw_vf_to_float(brw_inst_imm_ud(devinfo, inst) >> 16),
1522
brw_vf_to_float(brw_inst_imm_ud(devinfo, inst) >> 24));
1523
break;
1524
case BRW_REGISTER_TYPE_V:
1525
format(file, "0x%08xV", brw_inst_imm_ud(devinfo, inst));
1526
break;
1527
case BRW_REGISTER_TYPE_F:
1528
/* The DIM instruction's src0 uses an F type but contains a
1529
* 64-bit immediate
1530
*/
1531
if (brw_inst_opcode(devinfo, inst) == BRW_OPCODE_DIM) {
1532
format(file, "0x%"PRIx64"F", brw_inst_bits(inst, 127, 64));
1533
pad(file, 48);
1534
format(file, "/* %-gF */", brw_inst_imm_df(devinfo, inst));
1535
} else {
1536
format(file, "0x%"PRIx64"F", brw_inst_bits(inst, 127, 96));
1537
pad(file, 48);
1538
format(file, " /* %-gF */", brw_inst_imm_f(devinfo, inst));
1539
}
1540
break;
1541
case BRW_REGISTER_TYPE_DF:
1542
format(file, "0x%016"PRIx64"DF", brw_inst_bits(inst, 127, 64));
1543
pad(file, 48);
1544
format(file, "/* %-gDF */", brw_inst_imm_df(devinfo, inst));
1545
break;
1546
case BRW_REGISTER_TYPE_HF:
1547
string(file, "Half Float IMM");
1548
break;
1549
case BRW_REGISTER_TYPE_NF:
1550
case BRW_REGISTER_TYPE_UB:
1551
case BRW_REGISTER_TYPE_B:
1552
format(file, "*** invalid immediate type %d ", type);
1553
}
1554
return 0;
1555
}
1556
1557
static int
1558
src_sends_da(FILE *file,
1559
const struct intel_device_info *devinfo,
1560
enum brw_reg_type type,
1561
enum brw_reg_file _reg_file,
1562
unsigned _reg_nr,
1563
unsigned _reg_subnr)
1564
{
1565
int err = 0;
1566
1567
err |= reg(file, _reg_file, _reg_nr);
1568
if (err == -1)
1569
return 0;
1570
if (_reg_subnr)
1571
format(file, ".1");
1572
string(file, brw_reg_type_to_letters(type));
1573
1574
return err;
1575
}
1576
1577
static int
1578
src_sends_ia(FILE *file,
1579
const struct intel_device_info *devinfo,
1580
enum brw_reg_type type,
1581
int _addr_imm,
1582
unsigned _addr_subreg_nr)
1583
{
1584
string(file, "g[a0");
1585
if (_addr_subreg_nr)
1586
format(file, ".1");
1587
if (_addr_imm)
1588
format(file, " %d", _addr_imm);
1589
string(file, "]");
1590
string(file, brw_reg_type_to_letters(type));
1591
1592
return 0;
1593
}
1594
1595
static int
1596
src_send_desc_ia(FILE *file,
1597
const struct intel_device_info *devinfo,
1598
unsigned _addr_subreg_nr)
1599
{
1600
string(file, "a0");
1601
if (_addr_subreg_nr)
1602
format(file, ".%d", _addr_subreg_nr);
1603
format(file, "<0>UD");
1604
1605
return 0;
1606
}
1607
1608
static int
1609
src0(FILE *file, const struct intel_device_info *devinfo, const brw_inst *inst)
1610
{
1611
if (is_split_send(devinfo, brw_inst_opcode(devinfo, inst))) {
1612
if (devinfo->ver >= 12) {
1613
return src_sends_da(file,
1614
devinfo,
1615
BRW_REGISTER_TYPE_UD,
1616
brw_inst_send_src0_reg_file(devinfo, inst),
1617
brw_inst_src0_da_reg_nr(devinfo, inst),
1618
0);
1619
} else if (brw_inst_send_src0_address_mode(devinfo, inst) == BRW_ADDRESS_DIRECT) {
1620
return src_sends_da(file,
1621
devinfo,
1622
BRW_REGISTER_TYPE_UD,
1623
BRW_GENERAL_REGISTER_FILE,
1624
brw_inst_src0_da_reg_nr(devinfo, inst),
1625
brw_inst_src0_da16_subreg_nr(devinfo, inst));
1626
} else {
1627
return src_sends_ia(file,
1628
devinfo,
1629
BRW_REGISTER_TYPE_UD,
1630
brw_inst_send_src0_ia16_addr_imm(devinfo, inst),
1631
brw_inst_src0_ia_subreg_nr(devinfo, inst));
1632
}
1633
} else if (brw_inst_src0_reg_file(devinfo, inst) == BRW_IMMEDIATE_VALUE) {
1634
return imm(file, devinfo, brw_inst_src0_type(devinfo, inst), inst);
1635
} else if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
1636
if (brw_inst_src0_address_mode(devinfo, inst) == BRW_ADDRESS_DIRECT) {
1637
return src_da1(file,
1638
devinfo,
1639
brw_inst_opcode(devinfo, inst),
1640
brw_inst_src0_type(devinfo, inst),
1641
brw_inst_src0_reg_file(devinfo, inst),
1642
brw_inst_src0_vstride(devinfo, inst),
1643
brw_inst_src0_width(devinfo, inst),
1644
brw_inst_src0_hstride(devinfo, inst),
1645
brw_inst_src0_da_reg_nr(devinfo, inst),
1646
brw_inst_src0_da1_subreg_nr(devinfo, inst),
1647
brw_inst_src0_abs(devinfo, inst),
1648
brw_inst_src0_negate(devinfo, inst));
1649
} else {
1650
return src_ia1(file,
1651
devinfo,
1652
brw_inst_opcode(devinfo, inst),
1653
brw_inst_src0_type(devinfo, inst),
1654
brw_inst_src0_ia1_addr_imm(devinfo, inst),
1655
brw_inst_src0_ia_subreg_nr(devinfo, inst),
1656
brw_inst_src0_negate(devinfo, inst),
1657
brw_inst_src0_abs(devinfo, inst),
1658
brw_inst_src0_hstride(devinfo, inst),
1659
brw_inst_src0_width(devinfo, inst),
1660
brw_inst_src0_vstride(devinfo, inst));
1661
}
1662
} else {
1663
if (brw_inst_src0_address_mode(devinfo, inst) == BRW_ADDRESS_DIRECT) {
1664
return src_da16(file,
1665
devinfo,
1666
brw_inst_opcode(devinfo, inst),
1667
brw_inst_src0_type(devinfo, inst),
1668
brw_inst_src0_reg_file(devinfo, inst),
1669
brw_inst_src0_vstride(devinfo, inst),
1670
brw_inst_src0_da_reg_nr(devinfo, inst),
1671
brw_inst_src0_da16_subreg_nr(devinfo, inst),
1672
brw_inst_src0_abs(devinfo, inst),
1673
brw_inst_src0_negate(devinfo, inst),
1674
brw_inst_src0_da16_swiz_x(devinfo, inst),
1675
brw_inst_src0_da16_swiz_y(devinfo, inst),
1676
brw_inst_src0_da16_swiz_z(devinfo, inst),
1677
brw_inst_src0_da16_swiz_w(devinfo, inst));
1678
} else {
1679
string(file, "Indirect align16 address mode not supported");
1680
return 1;
1681
}
1682
}
1683
}
1684
1685
static int
1686
src1(FILE *file, const struct intel_device_info *devinfo, const brw_inst *inst)
1687
{
1688
if (is_split_send(devinfo, brw_inst_opcode(devinfo, inst))) {
1689
return src_sends_da(file,
1690
devinfo,
1691
BRW_REGISTER_TYPE_UD,
1692
brw_inst_send_src1_reg_file(devinfo, inst),
1693
brw_inst_send_src1_reg_nr(devinfo, inst),
1694
0 /* subreg_nr */);
1695
} else if (brw_inst_src1_reg_file(devinfo, inst) == BRW_IMMEDIATE_VALUE) {
1696
return imm(file, devinfo, brw_inst_src1_type(devinfo, inst), inst);
1697
} else if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
1698
if (brw_inst_src1_address_mode(devinfo, inst) == BRW_ADDRESS_DIRECT) {
1699
return src_da1(file,
1700
devinfo,
1701
brw_inst_opcode(devinfo, inst),
1702
brw_inst_src1_type(devinfo, inst),
1703
brw_inst_src1_reg_file(devinfo, inst),
1704
brw_inst_src1_vstride(devinfo, inst),
1705
brw_inst_src1_width(devinfo, inst),
1706
brw_inst_src1_hstride(devinfo, inst),
1707
brw_inst_src1_da_reg_nr(devinfo, inst),
1708
brw_inst_src1_da1_subreg_nr(devinfo, inst),
1709
brw_inst_src1_abs(devinfo, inst),
1710
brw_inst_src1_negate(devinfo, inst));
1711
} else {
1712
return src_ia1(file,
1713
devinfo,
1714
brw_inst_opcode(devinfo, inst),
1715
brw_inst_src1_type(devinfo, inst),
1716
brw_inst_src1_ia1_addr_imm(devinfo, inst),
1717
brw_inst_src1_ia_subreg_nr(devinfo, inst),
1718
brw_inst_src1_negate(devinfo, inst),
1719
brw_inst_src1_abs(devinfo, inst),
1720
brw_inst_src1_hstride(devinfo, inst),
1721
brw_inst_src1_width(devinfo, inst),
1722
brw_inst_src1_vstride(devinfo, inst));
1723
}
1724
} else {
1725
if (brw_inst_src1_address_mode(devinfo, inst) == BRW_ADDRESS_DIRECT) {
1726
return src_da16(file,
1727
devinfo,
1728
brw_inst_opcode(devinfo, inst),
1729
brw_inst_src1_type(devinfo, inst),
1730
brw_inst_src1_reg_file(devinfo, inst),
1731
brw_inst_src1_vstride(devinfo, inst),
1732
brw_inst_src1_da_reg_nr(devinfo, inst),
1733
brw_inst_src1_da16_subreg_nr(devinfo, inst),
1734
brw_inst_src1_abs(devinfo, inst),
1735
brw_inst_src1_negate(devinfo, inst),
1736
brw_inst_src1_da16_swiz_x(devinfo, inst),
1737
brw_inst_src1_da16_swiz_y(devinfo, inst),
1738
brw_inst_src1_da16_swiz_z(devinfo, inst),
1739
brw_inst_src1_da16_swiz_w(devinfo, inst));
1740
} else {
1741
string(file, "Indirect align16 address mode not supported");
1742
return 1;
1743
}
1744
}
1745
}
1746
1747
static int
1748
qtr_ctrl(FILE *file, const struct intel_device_info *devinfo,
1749
const brw_inst *inst)
1750
{
1751
int qtr_ctl = brw_inst_qtr_control(devinfo, inst);
1752
int exec_size = 1 << brw_inst_exec_size(devinfo, inst);
1753
const unsigned nib_ctl = devinfo->ver < 7 ? 0 :
1754
brw_inst_nib_control(devinfo, inst);
1755
1756
if (exec_size < 8 || nib_ctl) {
1757
format(file, " %dN", qtr_ctl * 2 + nib_ctl + 1);
1758
} else if (exec_size == 8) {
1759
switch (qtr_ctl) {
1760
case 0:
1761
string(file, " 1Q");
1762
break;
1763
case 1:
1764
string(file, " 2Q");
1765
break;
1766
case 2:
1767
string(file, " 3Q");
1768
break;
1769
case 3:
1770
string(file, " 4Q");
1771
break;
1772
}
1773
} else if (exec_size == 16) {
1774
if (qtr_ctl < 2)
1775
string(file, " 1H");
1776
else
1777
string(file, " 2H");
1778
}
1779
return 0;
1780
}
1781
1782
static int
1783
swsb(FILE *file, const struct intel_device_info *devinfo, const brw_inst *inst)
1784
{
1785
const enum opcode opcode = brw_inst_opcode(devinfo, inst);
1786
const uint8_t x = brw_inst_swsb(devinfo, inst);
1787
const struct tgl_swsb swsb = tgl_swsb_decode(devinfo, opcode, x);
1788
if (swsb.regdist)
1789
format(file, " %s@%d",
1790
(swsb.pipe == TGL_PIPE_FLOAT ? "F" :
1791
swsb.pipe == TGL_PIPE_INT ? "I" :
1792
swsb.pipe == TGL_PIPE_LONG ? "L" :
1793
swsb.pipe == TGL_PIPE_ALL ? "A" : "" ),
1794
swsb.regdist);
1795
if (swsb.mode)
1796
format(file, " $%d%s", swsb.sbid,
1797
(swsb.mode & TGL_SBID_SET ? "" :
1798
swsb.mode & TGL_SBID_DST ? ".dst" : ".src"));
1799
return 0;
1800
}
1801
1802
#ifdef DEBUG
1803
static __attribute__((__unused__)) int
1804
brw_disassemble_imm(const struct intel_device_info *devinfo,
1805
uint32_t dw3, uint32_t dw2, uint32_t dw1, uint32_t dw0)
1806
{
1807
brw_inst inst;
1808
inst.data[0] = (((uint64_t) dw1) << 32) | ((uint64_t) dw0);
1809
inst.data[1] = (((uint64_t) dw3) << 32) | ((uint64_t) dw2);
1810
return brw_disassemble_inst(stderr, devinfo, &inst, false, 0, NULL);
1811
}
1812
#endif
1813
1814
static void
1815
write_label(FILE *file, const struct intel_device_info *devinfo,
1816
const struct brw_label *root_label,
1817
int offset, int jump)
1818
{
1819
if (root_label != NULL) {
1820
int to_bytes_scale = sizeof(brw_inst) / brw_jump_scale(devinfo);
1821
const struct brw_label *label =
1822
brw_find_label(root_label, offset + jump * to_bytes_scale);
1823
if (label != NULL) {
1824
format(file, " LABEL%d", label->number);
1825
}
1826
}
1827
}
1828
1829
static void
1830
lsc_disassemble_ex_desc(const struct intel_device_info *devinfo,
1831
uint32_t imm_desc,
1832
uint32_t imm_ex_desc,
1833
FILE *file)
1834
{
1835
const unsigned addr_type = lsc_msg_desc_addr_type(devinfo, imm_desc);
1836
switch (addr_type) {
1837
case LSC_ADDR_SURFTYPE_FLAT:
1838
format(file, "base_offset %u ",
1839
lsc_flat_ex_desc_base_offset(devinfo, imm_ex_desc));
1840
break;
1841
case LSC_ADDR_SURFTYPE_BSS:
1842
case LSC_ADDR_SURFTYPE_SS:
1843
format(file, "surface_state_index %u ",
1844
lsc_bss_ex_desc_index(devinfo, imm_ex_desc));
1845
break;
1846
case LSC_ADDR_SURFTYPE_BTI:
1847
format(file, "BTI %u ",
1848
lsc_bti_ex_desc_index(devinfo, imm_ex_desc));
1849
format(file, "base_offset %u ",
1850
lsc_bti_ex_desc_base_offset(devinfo, imm_ex_desc));
1851
break;
1852
default:
1853
format(file, "unsupported address surface type %d", addr_type);
1854
break;
1855
}
1856
}
1857
1858
static inline bool
1859
brw_sfid_is_lsc(unsigned sfid)
1860
{
1861
switch (sfid) {
1862
case GFX12_SFID_UGM:
1863
case GFX12_SFID_SLM:
1864
case GFX12_SFID_TGM:
1865
return true;
1866
default:
1867
break;
1868
}
1869
1870
return false;
1871
}
1872
1873
int
1874
brw_disassemble_inst(FILE *file, const struct intel_device_info *devinfo,
1875
const brw_inst *inst, bool is_compacted,
1876
int offset, const struct brw_label *root_label)
1877
{
1878
int err = 0;
1879
int space = 0;
1880
1881
const enum opcode opcode = brw_inst_opcode(devinfo, inst);
1882
const struct opcode_desc *desc = brw_opcode_desc(devinfo, opcode);
1883
1884
if (brw_inst_pred_control(devinfo, inst)) {
1885
string(file, "(");
1886
err |= control(file, "predicate inverse", pred_inv,
1887
brw_inst_pred_inv(devinfo, inst), NULL);
1888
format(file, "f%"PRIu64".%"PRIu64,
1889
devinfo->ver >= 7 ? brw_inst_flag_reg_nr(devinfo, inst) : 0,
1890
brw_inst_flag_subreg_nr(devinfo, inst));
1891
if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
1892
err |= control(file, "predicate control align1", pred_ctrl_align1,
1893
brw_inst_pred_control(devinfo, inst), NULL);
1894
} else {
1895
err |= control(file, "predicate control align16", pred_ctrl_align16,
1896
brw_inst_pred_control(devinfo, inst), NULL);
1897
}
1898
string(file, ") ");
1899
}
1900
1901
err |= print_opcode(file, devinfo, opcode);
1902
1903
if (!is_send(opcode))
1904
err |= control(file, "saturate", saturate, brw_inst_saturate(devinfo, inst),
1905
NULL);
1906
1907
err |= control(file, "debug control", debug_ctrl,
1908
brw_inst_debug_control(devinfo, inst), NULL);
1909
1910
if (opcode == BRW_OPCODE_MATH) {
1911
string(file, " ");
1912
err |= control(file, "function", math_function,
1913
brw_inst_math_function(devinfo, inst), NULL);
1914
1915
} else if (opcode == BRW_OPCODE_SYNC) {
1916
string(file, " ");
1917
err |= control(file, "function", sync_function,
1918
brw_inst_cond_modifier(devinfo, inst), NULL);
1919
1920
} else if (!is_send(opcode)) {
1921
err |= control(file, "conditional modifier", conditional_modifier,
1922
brw_inst_cond_modifier(devinfo, inst), NULL);
1923
1924
/* If we're using the conditional modifier, print which flags reg is
1925
* used for it. Note that on gfx6+, the embedded-condition SEL and
1926
* control flow doesn't update flags.
1927
*/
1928
if (brw_inst_cond_modifier(devinfo, inst) &&
1929
(devinfo->ver < 6 || (opcode != BRW_OPCODE_SEL &&
1930
opcode != BRW_OPCODE_CSEL &&
1931
opcode != BRW_OPCODE_IF &&
1932
opcode != BRW_OPCODE_WHILE))) {
1933
format(file, ".f%"PRIu64".%"PRIu64,
1934
devinfo->ver >= 7 ? brw_inst_flag_reg_nr(devinfo, inst) : 0,
1935
brw_inst_flag_subreg_nr(devinfo, inst));
1936
}
1937
}
1938
1939
if (opcode != BRW_OPCODE_NOP && opcode != BRW_OPCODE_NENOP) {
1940
string(file, "(");
1941
err |= control(file, "execution size", exec_size,
1942
brw_inst_exec_size(devinfo, inst), NULL);
1943
string(file, ")");
1944
}
1945
1946
if (opcode == BRW_OPCODE_SEND && devinfo->ver < 6)
1947
format(file, " %"PRIu64, brw_inst_base_mrf(devinfo, inst));
1948
1949
if (brw_has_uip(devinfo, opcode)) {
1950
/* Instructions that have UIP also have JIP. */
1951
pad(file, 16);
1952
string(file, "JIP: ");
1953
write_label(file, devinfo, root_label, offset, brw_inst_jip(devinfo, inst));
1954
1955
pad(file, 38);
1956
string(file, "UIP: ");
1957
write_label(file, devinfo, root_label, offset, brw_inst_uip(devinfo, inst));
1958
} else if (brw_has_jip(devinfo, opcode)) {
1959
int jip;
1960
if (devinfo->ver >= 7) {
1961
jip = brw_inst_jip(devinfo, inst);
1962
} else {
1963
jip = brw_inst_gfx6_jump_count(devinfo, inst);
1964
}
1965
1966
pad(file, 16);
1967
string(file, "JIP: ");
1968
write_label(file, devinfo, root_label, offset, jip);
1969
} else if (devinfo->ver < 6 && (opcode == BRW_OPCODE_BREAK ||
1970
opcode == BRW_OPCODE_CONTINUE ||
1971
opcode == BRW_OPCODE_ELSE)) {
1972
pad(file, 16);
1973
format(file, "Jump: %d", brw_inst_gfx4_jump_count(devinfo, inst));
1974
pad(file, 32);
1975
format(file, "Pop: %"PRIu64, brw_inst_gfx4_pop_count(devinfo, inst));
1976
} else if (devinfo->ver < 6 && (opcode == BRW_OPCODE_IF ||
1977
opcode == BRW_OPCODE_IFF ||
1978
opcode == BRW_OPCODE_HALT ||
1979
opcode == BRW_OPCODE_WHILE)) {
1980
pad(file, 16);
1981
format(file, "Jump: %d", brw_inst_gfx4_jump_count(devinfo, inst));
1982
} else if (devinfo->ver < 6 && opcode == BRW_OPCODE_ENDIF) {
1983
pad(file, 16);
1984
format(file, "Pop: %"PRIu64, brw_inst_gfx4_pop_count(devinfo, inst));
1985
} else if (opcode == BRW_OPCODE_JMPI) {
1986
pad(file, 16);
1987
err |= src1(file, devinfo, inst);
1988
} else if (desc && desc->nsrc == 3) {
1989
pad(file, 16);
1990
err |= dest_3src(file, devinfo, inst);
1991
1992
pad(file, 32);
1993
err |= src0_3src(file, devinfo, inst);
1994
1995
pad(file, 48);
1996
err |= src1_3src(file, devinfo, inst);
1997
1998
pad(file, 64);
1999
err |= src2_3src(file, devinfo, inst);
2000
} else if (desc) {
2001
if (desc->ndst > 0) {
2002
pad(file, 16);
2003
err |= dest(file, devinfo, inst);
2004
}
2005
2006
if (desc->nsrc > 0) {
2007
pad(file, 32);
2008
err |= src0(file, devinfo, inst);
2009
}
2010
2011
if (desc->nsrc > 1) {
2012
pad(file, 48);
2013
err |= src1(file, devinfo, inst);
2014
}
2015
}
2016
2017
if (is_send(opcode)) {
2018
enum brw_message_target sfid = brw_inst_sfid(devinfo, inst);
2019
2020
bool has_imm_desc = false, has_imm_ex_desc = false;
2021
uint32_t imm_desc = 0, imm_ex_desc = 0;
2022
if (is_split_send(devinfo, opcode)) {
2023
pad(file, 64);
2024
if (brw_inst_send_sel_reg32_desc(devinfo, inst)) {
2025
/* show the indirect descriptor source */
2026
err |= src_send_desc_ia(file, devinfo, 0);
2027
} else {
2028
has_imm_desc = true;
2029
imm_desc = brw_inst_send_desc(devinfo, inst);
2030
fprintf(file, "0x%08"PRIx32, imm_desc);
2031
}
2032
2033
pad(file, 80);
2034
if (brw_inst_send_sel_reg32_ex_desc(devinfo, inst)) {
2035
/* show the indirect descriptor source */
2036
err |= src_send_desc_ia(file, devinfo,
2037
brw_inst_send_ex_desc_ia_subreg_nr(devinfo, inst));
2038
} else {
2039
has_imm_ex_desc = true;
2040
imm_ex_desc = brw_inst_sends_ex_desc(devinfo, inst);
2041
fprintf(file, "0x%08"PRIx32, imm_ex_desc);
2042
}
2043
} else {
2044
if (brw_inst_src1_reg_file(devinfo, inst) != BRW_IMMEDIATE_VALUE) {
2045
/* show the indirect descriptor source */
2046
pad(file, 48);
2047
err |= src1(file, devinfo, inst);
2048
pad(file, 64);
2049
} else {
2050
has_imm_desc = true;
2051
imm_desc = brw_inst_send_desc(devinfo, inst);
2052
pad(file, 48);
2053
}
2054
2055
/* Print message descriptor as immediate source */
2056
fprintf(file, "0x%08"PRIx64, inst->data[1] >> 32);
2057
}
2058
2059
newline(file);
2060
pad(file, 16);
2061
space = 0;
2062
2063
fprintf(file, " ");
2064
err |= control(file, "SFID", devinfo->ver >= 6 ? gfx6_sfid : gfx4_sfid,
2065
sfid, &space);
2066
string(file, " MsgDesc:");
2067
2068
if (!has_imm_desc) {
2069
format(file, " indirect");
2070
} else {
2071
bool unsupported = false;
2072
switch (sfid) {
2073
case BRW_SFID_MATH:
2074
err |= control(file, "math function", math_function,
2075
brw_inst_math_msg_function(devinfo, inst), &space);
2076
err |= control(file, "math saturate", math_saturate,
2077
brw_inst_math_msg_saturate(devinfo, inst), &space);
2078
err |= control(file, "math signed", math_signed,
2079
brw_inst_math_msg_signed_int(devinfo, inst), &space);
2080
err |= control(file, "math scalar", math_scalar,
2081
brw_inst_math_msg_data_type(devinfo, inst), &space);
2082
err |= control(file, "math precision", math_precision,
2083
brw_inst_math_msg_precision(devinfo, inst), &space);
2084
break;
2085
case BRW_SFID_SAMPLER:
2086
if (devinfo->ver >= 5) {
2087
err |= control(file, "sampler message", gfx5_sampler_msg_type,
2088
brw_sampler_desc_msg_type(devinfo, imm_desc),
2089
&space);
2090
err |= control(file, "sampler simd mode", gfx5_sampler_simd_mode,
2091
brw_sampler_desc_simd_mode(devinfo, imm_desc),
2092
&space);
2093
format(file, " Surface = %u Sampler = %u",
2094
brw_sampler_desc_binding_table_index(devinfo, imm_desc),
2095
brw_sampler_desc_sampler(devinfo, imm_desc));
2096
} else {
2097
format(file, " (bti %u, sampler %u, msg_type %u, ",
2098
brw_sampler_desc_binding_table_index(devinfo, imm_desc),
2099
brw_sampler_desc_sampler(devinfo, imm_desc),
2100
brw_sampler_desc_msg_type(devinfo, imm_desc));
2101
if (!devinfo->is_g4x) {
2102
err |= control(file, "sampler target format",
2103
sampler_target_format,
2104
brw_sampler_desc_return_format(devinfo, imm_desc),
2105
NULL);
2106
}
2107
string(file, ")");
2108
}
2109
break;
2110
case GFX6_SFID_DATAPORT_SAMPLER_CACHE:
2111
case GFX6_SFID_DATAPORT_CONSTANT_CACHE:
2112
/* aka BRW_SFID_DATAPORT_READ on Gfx4-5 */
2113
if (devinfo->ver >= 6) {
2114
format(file, " (bti %u, msg_ctrl %u, msg_type %u, write_commit %u)",
2115
brw_dp_desc_binding_table_index(devinfo, imm_desc),
2116
brw_dp_desc_msg_control(devinfo, imm_desc),
2117
brw_dp_desc_msg_type(devinfo, imm_desc),
2118
devinfo->ver >= 7 ? 0u :
2119
brw_dp_write_desc_write_commit(devinfo, imm_desc));
2120
} else {
2121
bool is_965 = devinfo->ver == 4 && !devinfo->is_g4x;
2122
err |= control(file, "DP read message type",
2123
is_965 ? gfx4_dp_read_port_msg_type :
2124
g45_dp_read_port_msg_type,
2125
brw_dp_read_desc_msg_type(devinfo, imm_desc),
2126
&space);
2127
2128
format(file, " MsgCtrl = 0x%u",
2129
brw_dp_read_desc_msg_control(devinfo, imm_desc));
2130
2131
format(file, " Surface = %u",
2132
brw_dp_desc_binding_table_index(devinfo, imm_desc));
2133
}
2134
break;
2135
2136
case GFX6_SFID_DATAPORT_RENDER_CACHE: {
2137
/* aka BRW_SFID_DATAPORT_WRITE on Gfx4-5 */
2138
unsigned msg_type = brw_fb_write_desc_msg_type(devinfo, imm_desc);
2139
2140
err |= control(file, "DP rc message type",
2141
dp_rc_msg_type(devinfo), msg_type, &space);
2142
2143
bool is_rt_write = msg_type ==
2144
(devinfo->ver >= 6 ? GFX6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE
2145
: BRW_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE);
2146
2147
if (is_rt_write) {
2148
err |= control(file, "RT message type", m_rt_write_subtype,
2149
brw_inst_rt_message_type(devinfo, inst), &space);
2150
if (devinfo->ver >= 6 && brw_inst_rt_slot_group(devinfo, inst))
2151
string(file, " Hi");
2152
if (brw_fb_write_desc_last_render_target(devinfo, imm_desc))
2153
string(file, " LastRT");
2154
if (devinfo->ver >= 10 &&
2155
brw_fb_write_desc_coarse_write(devinfo, imm_desc))
2156
string(file, " CoarseWrite");
2157
if (devinfo->ver < 7 &&
2158
brw_fb_write_desc_write_commit(devinfo, imm_desc))
2159
string(file, " WriteCommit");
2160
} else {
2161
format(file, " MsgCtrl = 0x%u",
2162
brw_fb_write_desc_msg_control(devinfo, imm_desc));
2163
}
2164
2165
format(file, " Surface = %u",
2166
brw_fb_desc_binding_table_index(devinfo, imm_desc));
2167
break;
2168
}
2169
2170
case BRW_SFID_URB: {
2171
unsigned opcode = brw_inst_urb_opcode(devinfo, inst);
2172
2173
format(file, " offset %"PRIu64, brw_inst_urb_global_offset(devinfo, inst));
2174
2175
space = 1;
2176
2177
err |= control(file, "urb opcode",
2178
devinfo->ver >= 7 ? gfx7_urb_opcode
2179
: gfx5_urb_opcode,
2180
opcode, &space);
2181
2182
if (devinfo->ver >= 7 &&
2183
brw_inst_urb_per_slot_offset(devinfo, inst)) {
2184
string(file, " per-slot");
2185
}
2186
2187
if (opcode == GFX8_URB_OPCODE_SIMD8_WRITE ||
2188
opcode == GFX8_URB_OPCODE_SIMD8_READ) {
2189
if (brw_inst_urb_channel_mask_present(devinfo, inst))
2190
string(file, " masked");
2191
} else {
2192
err |= control(file, "urb swizzle", urb_swizzle,
2193
brw_inst_urb_swizzle_control(devinfo, inst),
2194
&space);
2195
}
2196
2197
if (devinfo->ver < 7) {
2198
err |= control(file, "urb allocate", urb_allocate,
2199
brw_inst_urb_allocate(devinfo, inst), &space);
2200
err |= control(file, "urb used", urb_used,
2201
brw_inst_urb_used(devinfo, inst), &space);
2202
}
2203
if (devinfo->ver < 8) {
2204
err |= control(file, "urb complete", urb_complete,
2205
brw_inst_urb_complete(devinfo, inst), &space);
2206
}
2207
break;
2208
}
2209
case BRW_SFID_THREAD_SPAWNER:
2210
break;
2211
2212
case BRW_SFID_MESSAGE_GATEWAY:
2213
format(file, " (%s)",
2214
gfx7_gateway_subfuncid[brw_inst_gateway_subfuncid(devinfo, inst)]);
2215
break;
2216
2217
case GFX12_SFID_SLM:
2218
case GFX12_SFID_TGM:
2219
case GFX12_SFID_UGM: {
2220
assert(devinfo->has_lsc);
2221
format(file, " (");
2222
const enum lsc_opcode op = lsc_msg_desc_opcode(devinfo, imm_desc);
2223
err |= control(file, "operation", lsc_operation,
2224
op, &space);
2225
format(file, ",");
2226
err |= control(file, "addr_size", lsc_addr_size,
2227
lsc_msg_desc_addr_size(devinfo, imm_desc),
2228
&space);
2229
2230
if (op == LSC_OP_FENCE) {
2231
format(file, ",");
2232
err |= control(file, "scope", lsc_fence_scope,
2233
lsc_fence_msg_desc_scope(devinfo, imm_desc),
2234
&space);
2235
format(file, ",");
2236
err |= control(file, "flush_type", lsc_flush_type,
2237
lsc_fence_msg_desc_flush_type(devinfo, imm_desc),
2238
&space);
2239
format(file, ",");
2240
err |= control(file, "backup_mode_fence_routing",
2241
lsc_backup_fence_routing,
2242
lsc_fence_msg_desc_backup_routing(devinfo, imm_desc),
2243
&space);
2244
} else {
2245
format(file, ",");
2246
err |= control(file, "data_size", lsc_data_size,
2247
lsc_msg_desc_data_size(devinfo, imm_desc),
2248
&space);
2249
format(file, ",");
2250
if (lsc_opcode_has_cmask(op)) {
2251
err |= control(file, "component_mask",
2252
lsc_cmask_str,
2253
lsc_msg_desc_cmask(devinfo, imm_desc),
2254
&space);
2255
} else {
2256
err |= control(file, "vector_size",
2257
lsc_vect_size_str,
2258
lsc_msg_desc_vect_size(devinfo, imm_desc),
2259
&space);
2260
if (lsc_msg_desc_transpose(devinfo, imm_desc))
2261
format(file, ", transpose");
2262
}
2263
switch(op) {
2264
case LSC_OP_LOAD_CMASK:
2265
case LSC_OP_LOAD:
2266
format(file, ",");
2267
err |= control(file, "cache_load",
2268
lsc_cache_load,
2269
lsc_msg_desc_cache_ctrl(devinfo, imm_desc),
2270
&space);
2271
break;
2272
default:
2273
format(file, ",");
2274
err |= control(file, "cache_store",
2275
lsc_cache_store,
2276
lsc_msg_desc_cache_ctrl(devinfo, imm_desc),
2277
&space);
2278
break;
2279
}
2280
}
2281
format(file, " dst_len = %u,", lsc_msg_desc_dest_len(devinfo, imm_desc));
2282
format(file, " src0_len = %u,", lsc_msg_desc_src0_len(devinfo, imm_desc));
2283
format(file, " src1_len = %d", brw_message_ex_desc_ex_mlen(devinfo, imm_ex_desc));
2284
err |= control(file, "address_type", lsc_addr_surface_type,
2285
lsc_msg_desc_addr_type(devinfo, imm_desc), &space);
2286
format(file, " )");
2287
break;
2288
}
2289
2290
case GFX7_SFID_DATAPORT_DATA_CACHE:
2291
if (devinfo->ver >= 7) {
2292
format(file, " (");
2293
space = 0;
2294
2295
err |= control(file, "DP DC0 message type",
2296
dp_dc0_msg_type_gfx7,
2297
brw_dp_desc_msg_type(devinfo, imm_desc), &space);
2298
2299
format(file, ", bti %u, ",
2300
brw_dp_desc_binding_table_index(devinfo, imm_desc));
2301
2302
switch (brw_inst_dp_msg_type(devinfo, inst)) {
2303
case GFX7_DATAPORT_DC_UNTYPED_ATOMIC_OP:
2304
control(file, "atomic op", aop,
2305
brw_dp_desc_msg_control(devinfo, imm_desc) & 0xf,
2306
&space);
2307
break;
2308
case GFX7_DATAPORT_DC_OWORD_BLOCK_READ:
2309
case GFX7_DATAPORT_DC_OWORD_BLOCK_WRITE: {
2310
unsigned msg_ctrl = brw_dp_desc_msg_control(devinfo, imm_desc);
2311
assert(dp_oword_block_rw[msg_ctrl & 7]);
2312
format(file, "owords = %s, aligned = %d",
2313
dp_oword_block_rw[msg_ctrl & 7], (msg_ctrl >> 3) & 3);
2314
break;
2315
}
2316
default:
2317
format(file, "%u",
2318
brw_dp_desc_msg_control(devinfo, imm_desc));
2319
}
2320
format(file, ")");
2321
} else {
2322
unsupported = true;
2323
}
2324
break;
2325
2326
case HSW_SFID_DATAPORT_DATA_CACHE_1: {
2327
if (devinfo->ver >= 7) {
2328
format(file, " (");
2329
space = 0;
2330
2331
unsigned msg_ctrl = brw_dp_desc_msg_control(devinfo, imm_desc);
2332
2333
err |= control(file, "DP DC1 message type",
2334
dp_dc1_msg_type_hsw,
2335
brw_dp_desc_msg_type(devinfo, imm_desc), &space);
2336
2337
format(file, ", Surface = %u, ",
2338
brw_dp_desc_binding_table_index(devinfo, imm_desc));
2339
2340
switch (brw_inst_dp_msg_type(devinfo, inst)) {
2341
case HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP:
2342
case HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP:
2343
case HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP:
2344
format(file, "SIMD%d,", (msg_ctrl & (1 << 4)) ? 8 : 16);
2345
FALLTHROUGH;
2346
case HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2:
2347
case HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP_SIMD4X2:
2348
case HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP_SIMD4X2:
2349
case GFX8_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_OP:
2350
case GFX12_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_HALF_INT_OP:
2351
control(file, "atomic op", aop, msg_ctrl & 0xf, &space);
2352
break;
2353
case HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_READ:
2354
case HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_WRITE:
2355
case HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_READ:
2356
case HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_WRITE:
2357
case GFX8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_WRITE:
2358
case GFX8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_READ: {
2359
static const char *simd_modes[] = { "4x2", "16", "8" };
2360
format(file, "SIMD%s, Mask = 0x%x",
2361
simd_modes[msg_ctrl >> 4], msg_ctrl & 0xf);
2362
break;
2363
}
2364
case GFX9_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_FLOAT_OP:
2365
case GFX9_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_FLOAT_OP:
2366
case GFX12_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_HALF_FLOAT_OP:
2367
format(file, "SIMD%d,", (msg_ctrl & (1 << 4)) ? 8 : 16);
2368
control(file, "atomic float op", aop_float, msg_ctrl & 0xf,
2369
&space);
2370
break;
2371
case GFX9_DATAPORT_DC_PORT1_A64_OWORD_BLOCK_WRITE:
2372
case GFX9_DATAPORT_DC_PORT1_A64_OWORD_BLOCK_READ:
2373
assert(dp_oword_block_rw[msg_ctrl & 7]);
2374
format(file, "owords = %s, aligned = %d",
2375
dp_oword_block_rw[msg_ctrl & 7], (msg_ctrl >> 3) & 3);
2376
break;
2377
default:
2378
format(file, "0x%x", msg_ctrl);
2379
}
2380
format(file, ")");
2381
} else {
2382
unsupported = true;
2383
}
2384
break;
2385
}
2386
2387
case GFX7_SFID_PIXEL_INTERPOLATOR:
2388
if (devinfo->ver >= 7) {
2389
format(file, " (%s, %s, 0x%02"PRIx64")",
2390
brw_inst_pi_nopersp(devinfo, inst) ? "linear" : "persp",
2391
pixel_interpolator_msg_types[brw_inst_pi_message_type(devinfo, inst)],
2392
brw_inst_pi_message_data(devinfo, inst));
2393
} else {
2394
unsupported = true;
2395
}
2396
break;
2397
2398
case GEN_RT_SFID_RAY_TRACE_ACCELERATOR:
2399
if (devinfo->has_ray_tracing) {
2400
format(file, " SIMD%d,",
2401
brw_rt_trace_ray_desc_exec_size(devinfo, imm_desc));
2402
} else {
2403
unsupported = true;
2404
}
2405
break;
2406
2407
default:
2408
unsupported = true;
2409
break;
2410
}
2411
2412
if (unsupported)
2413
format(file, "unsupported shared function ID %d", sfid);
2414
2415
if (space)
2416
string(file, " ");
2417
}
2418
if (brw_sfid_is_lsc(sfid)) {
2419
lsc_disassemble_ex_desc(devinfo, imm_desc, imm_ex_desc, file);
2420
} else {
2421
if (has_imm_desc)
2422
format(file, "mlen %u", brw_message_desc_mlen(devinfo, imm_desc));
2423
if (has_imm_ex_desc) {
2424
format(file, " ex_mlen %u",
2425
brw_message_ex_desc_ex_mlen(devinfo, imm_ex_desc));
2426
}
2427
if (has_imm_desc)
2428
format(file, " rlen %u", brw_message_desc_rlen(devinfo, imm_desc));
2429
}
2430
}
2431
pad(file, 64);
2432
if (opcode != BRW_OPCODE_NOP && opcode != BRW_OPCODE_NENOP) {
2433
string(file, "{");
2434
space = 1;
2435
err |= control(file, "access mode", access_mode,
2436
brw_inst_access_mode(devinfo, inst), &space);
2437
if (devinfo->ver >= 6) {
2438
err |= control(file, "write enable control", wectrl,
2439
brw_inst_mask_control(devinfo, inst), &space);
2440
} else {
2441
err |= control(file, "mask control", mask_ctrl,
2442
brw_inst_mask_control(devinfo, inst), &space);
2443
}
2444
2445
if (devinfo->ver < 12) {
2446
err |= control(file, "dependency control", dep_ctrl,
2447
((brw_inst_no_dd_check(devinfo, inst) << 1) |
2448
brw_inst_no_dd_clear(devinfo, inst)), &space);
2449
}
2450
2451
if (devinfo->ver >= 6)
2452
err |= qtr_ctrl(file, devinfo, inst);
2453
else {
2454
if (brw_inst_qtr_control(devinfo, inst) == BRW_COMPRESSION_COMPRESSED &&
2455
desc && desc->ndst > 0 &&
2456
brw_inst_dst_reg_file(devinfo, inst) == BRW_MESSAGE_REGISTER_FILE &&
2457
brw_inst_dst_da_reg_nr(devinfo, inst) & BRW_MRF_COMPR4) {
2458
format(file, " compr4");
2459
} else {
2460
err |= control(file, "compression control", compr_ctrl,
2461
brw_inst_qtr_control(devinfo, inst), &space);
2462
}
2463
}
2464
2465
if (devinfo->ver >= 12)
2466
err |= swsb(file, devinfo, inst);
2467
2468
err |= control(file, "compaction", cmpt_ctrl, is_compacted, &space);
2469
err |= control(file, "thread control", thread_ctrl,
2470
(devinfo->ver >= 12 ? brw_inst_atomic_control(devinfo, inst) :
2471
brw_inst_thread_control(devinfo, inst)),
2472
&space);
2473
if (has_branch_ctrl(devinfo, opcode)) {
2474
err |= control(file, "branch ctrl", branch_ctrl,
2475
brw_inst_branch_control(devinfo, inst), &space);
2476
} else if (devinfo->ver >= 6) {
2477
err |= control(file, "acc write control", accwr,
2478
brw_inst_acc_wr_control(devinfo, inst), &space);
2479
}
2480
if (is_send(opcode))
2481
err |= control(file, "end of thread", end_of_thread,
2482
brw_inst_eot(devinfo, inst), &space);
2483
if (space)
2484
string(file, " ");
2485
string(file, "}");
2486
}
2487
string(file, ";");
2488
newline(file);
2489
return err;
2490
}
2491
2492