Path: blob/21.2-virgl/src/intel/compiler/brw_fs_dead_code_eliminate.cpp
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/*1* Copyright © 2014 Intel Corporation2*3* Permission is hereby granted, free of charge, to any person obtaining a4* copy of this software and associated documentation files (the "Software"),5* to deal in the Software without restriction, including without limitation6* the rights to use, copy, modify, merge, publish, distribute, sublicense,7* and/or sell copies of the Software, and to permit persons to whom the8* Software is furnished to do so, subject to the following conditions:9*10* The above copyright notice and this permission notice (including the next11* paragraph) shall be included in all copies or substantial portions of the12* Software.13*14* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER18* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING19* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS20* IN THE SOFTWARE.21*/2223#include "brw_fs.h"24#include "brw_fs_live_variables.h"25#include "brw_cfg.h"2627/** @file brw_fs_dead_code_eliminate.cpp28*29* Dataflow-aware dead code elimination.30*31* Walks the instruction list from the bottom, removing instructions that32* have results that both aren't used in later blocks and haven't been read33* yet in the tail end of this block.34*/3536using namespace brw;3738/**39* Is it safe to eliminate the instruction?40*/41static bool42can_eliminate(const intel_device_info *devinfo, const fs_inst *inst,43BITSET_WORD *flag_live)44{45return !inst->is_control_flow() &&46!inst->has_side_effects() &&47!(flag_live[0] & inst->flags_written(devinfo)) &&48!inst->writes_accumulator;49}5051/**52* Is it safe to omit the write, making the destination ARF null?53*/54static bool55can_omit_write(const fs_inst *inst)56{57switch (inst->opcode) {58case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:59case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL:60case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:61return true;62default:63/* We can eliminate the destination write for ordinary instructions,64* but not most SENDs.65*/66if (inst->opcode < 128 && inst->mlen == 0)67return true;6869/* It might not be safe for other virtual opcodes. */70return false;71}72}7374bool75fs_visitor::dead_code_eliminate()76{77bool progress = false;7879const fs_live_variables &live_vars = live_analysis.require();80int num_vars = live_vars.num_vars;81BITSET_WORD *live = rzalloc_array(NULL, BITSET_WORD, BITSET_WORDS(num_vars));82BITSET_WORD *flag_live = rzalloc_array(NULL, BITSET_WORD, 1);8384foreach_block_reverse_safe(block, cfg) {85memcpy(live, live_vars.block_data[block->num].liveout,86sizeof(BITSET_WORD) * BITSET_WORDS(num_vars));87memcpy(flag_live, live_vars.block_data[block->num].flag_liveout,88sizeof(BITSET_WORD));8990foreach_inst_in_block_reverse_safe(fs_inst, inst, block) {91if (inst->dst.file == VGRF) {92const unsigned var = live_vars.var_from_reg(inst->dst);93bool result_live = false;9495for (unsigned i = 0; i < regs_written(inst); i++)96result_live |= BITSET_TEST(live, var + i);9798if (!result_live &&99(can_omit_write(inst) || can_eliminate(devinfo, inst, flag_live))) {100inst->dst = fs_reg(spread(retype(brw_null_reg(), inst->dst.type),101inst->dst.stride));102progress = true;103}104}105106if (inst->dst.is_null() && can_eliminate(devinfo, inst, flag_live)) {107inst->opcode = BRW_OPCODE_NOP;108progress = true;109}110111if (inst->dst.file == VGRF) {112if (!inst->is_partial_write()) {113const unsigned var = live_vars.var_from_reg(inst->dst);114for (unsigned i = 0; i < regs_written(inst); i++) {115BITSET_CLEAR(live, var + i);116}117}118}119120if (!inst->predicate && inst->exec_size >= 8)121flag_live[0] &= ~inst->flags_written(devinfo);122123if (inst->opcode == BRW_OPCODE_NOP) {124inst->remove(block, true);125continue;126}127128for (int i = 0; i < inst->sources; i++) {129if (inst->src[i].file == VGRF) {130int var = live_vars.var_from_reg(inst->src[i]);131132for (unsigned j = 0; j < regs_read(inst, i); j++) {133BITSET_SET(live, var + j);134}135}136}137138flag_live[0] |= inst->flags_read(devinfo);139}140}141142cfg->adjust_block_ips();143144ralloc_free(live);145ralloc_free(flag_live);146147if (progress)148invalidate_analysis(DEPENDENCY_INSTRUCTIONS);149150return progress;151}152153154