Path: blob/21.2-virgl/src/intel/compiler/brw_fs_sel_peephole.cpp
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/*1* Copyright © 2013 Intel Corporation2*3* Permission is hereby granted, free of charge, to any person obtaining a4* copy of this software and associated documentation files (the "Software"),5* to deal in the Software without restriction, including without limitation6* the rights to use, copy, modify, merge, publish, distribute, sublicense,7* and/or sell copies of the Software, and to permit persons to whom the8* Software is furnished to do so, subject to the following conditions:9*10* The above copyright notice and this permission notice (including the next11* paragraph) shall be included in all copies or substantial portions of the12* Software.13*14* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER18* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING19* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS20* IN THE SOFTWARE.21*/2223#include "brw_fs.h"24#include "brw_cfg.h"2526/** @file brw_fs_sel_peephole.cpp27*28* This file contains the opt_peephole_sel() optimization pass that replaces29* MOV instructions to the same destination in the "then" and "else" bodies of30* an if statement with SEL instructions.31*/3233/* Four MOVs seems to be pretty typical, so I picked the next power of two in34* the hopes that it would handle almost anything possible in a single35* pass.36*/37#define MAX_MOVS 8 /**< The maximum number of MOVs to attempt to match. */3839using namespace brw;4041/**42* Scans forwards from an IF counting consecutive MOV instructions in the43* "then" and "else" blocks of the if statement.44*45* A pointer to the bblock_t following the IF is passed as the <then_block>46* argument. The function stores pointers to the MOV instructions in the47* <then_mov> and <else_mov> arrays.48*49* \return the minimum number of MOVs found in the two branches or zero if50* an error occurred.51*52* E.g.:53* IF ...54* then_mov[0] = MOV g4, ...55* then_mov[1] = MOV g5, ...56* then_mov[2] = MOV g6, ...57* ELSE ...58* else_mov[0] = MOV g4, ...59* else_mov[1] = MOV g5, ...60* else_mov[2] = MOV g7, ...61* ENDIF62* returns 3.63*/64static int65count_movs_from_if(const intel_device_info *devinfo,66fs_inst *then_mov[MAX_MOVS], fs_inst *else_mov[MAX_MOVS],67bblock_t *then_block, bblock_t *else_block)68{69int then_movs = 0;70foreach_inst_in_block(fs_inst, inst, then_block) {71if (then_movs == MAX_MOVS || inst->opcode != BRW_OPCODE_MOV ||72inst->flags_written(devinfo))73break;7475then_mov[then_movs] = inst;76then_movs++;77}7879int else_movs = 0;80foreach_inst_in_block(fs_inst, inst, else_block) {81if (else_movs == MAX_MOVS || inst->opcode != BRW_OPCODE_MOV ||82inst->flags_written(devinfo))83break;8485else_mov[else_movs] = inst;86else_movs++;87}8889return MIN2(then_movs, else_movs);90}9192/**93* Try to replace IF/MOV+/ELSE/MOV+/ENDIF with SEL.94*95* Many GLSL shaders contain the following pattern:96*97* x = condition ? foo : bar98*99* or100*101* if (...) a.xyzw = foo.xyzw;102* else a.xyzw = bar.xyzw;103*104* The compiler emits an ir_if tree for this, since each subexpression might be105* a complex tree that could have side-effects or short-circuit logic.106*107* However, the common case is to simply select one of two constants or108* variable values---which is exactly what SEL is for. In this case, the109* assembly looks like:110*111* (+f0) IF112* MOV dst src0113* ...114* ELSE115* MOV dst src1116* ...117* ENDIF118*119* where each pair of MOVs to a common destination and can be easily translated120* into121*122* (+f0) SEL dst src0 src1123*124* If src0 is an immediate value, we promote it to a temporary GRF.125*/126bool127fs_visitor::opt_peephole_sel()128{129bool progress = false;130131foreach_block (block, cfg) {132/* IF instructions, by definition, can only be found at the ends of133* basic blocks.134*/135fs_inst *if_inst = (fs_inst *)block->end();136if (if_inst->opcode != BRW_OPCODE_IF)137continue;138139fs_inst *else_mov[MAX_MOVS] = { NULL };140fs_inst *then_mov[MAX_MOVS] = { NULL };141142bblock_t *then_block = block->next();143bblock_t *else_block = NULL;144foreach_list_typed(bblock_link, child, link, &block->children) {145if (child->block != then_block) {146if (child->block->prev()->end()->opcode == BRW_OPCODE_ELSE) {147else_block = child->block;148}149break;150}151}152if (else_block == NULL)153continue;154155int movs = count_movs_from_if(devinfo, then_mov, else_mov, then_block, else_block);156157if (movs == 0)158continue;159160/* Generate SEL instructions for pairs of MOVs to a common destination. */161for (int i = 0; i < movs; i++) {162if (!then_mov[i] || !else_mov[i])163break;164165/* Check that the MOVs are the right form. */166if (!then_mov[i]->dst.equals(else_mov[i]->dst) ||167then_mov[i]->exec_size != else_mov[i]->exec_size ||168then_mov[i]->group != else_mov[i]->group ||169then_mov[i]->force_writemask_all != else_mov[i]->force_writemask_all ||170then_mov[i]->is_partial_write() ||171else_mov[i]->is_partial_write() ||172then_mov[i]->conditional_mod != BRW_CONDITIONAL_NONE ||173else_mov[i]->conditional_mod != BRW_CONDITIONAL_NONE) {174movs = i;175break;176}177178/* Check that source types for mov operations match. */179if (then_mov[i]->src[0].type != else_mov[i]->src[0].type) {180movs = i;181break;182}183}184185if (movs == 0)186continue;187188for (int i = 0; i < movs; i++) {189const fs_builder ibld = fs_builder(this, then_block, then_mov[i])190.at(block, if_inst);191192if (then_mov[i]->src[0].equals(else_mov[i]->src[0])) {193ibld.MOV(then_mov[i]->dst, then_mov[i]->src[0]);194} else {195/* Only the last source register can be a constant, so if the MOV196* in the "then" clause uses a constant, we need to put it in a197* temporary.198*/199fs_reg src0(then_mov[i]->src[0]);200if (src0.file == IMM) {201src0 = ibld.vgrf(then_mov[i]->src[0].type);202ibld.MOV(src0, then_mov[i]->src[0]);203}204205/* 64-bit immediates can't be placed in src1. */206fs_reg src1(else_mov[i]->src[0]);207if (src1.file == IMM && type_sz(src1.type) == 8) {208src1 = ibld.vgrf(else_mov[i]->src[0].type);209ibld.MOV(src1, else_mov[i]->src[0]);210}211212set_predicate_inv(if_inst->predicate, if_inst->predicate_inverse,213ibld.SEL(then_mov[i]->dst, src0, src1));214}215216then_mov[i]->remove(then_block);217else_mov[i]->remove(else_block);218}219220progress = true;221}222223if (progress)224invalidate_analysis(DEPENDENCY_INSTRUCTIONS | DEPENDENCY_VARIABLES);225226return progress;227}228229230