Path: blob/21.2-virgl/src/intel/tools/intel_context.h
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/*1* Copyright © 2018 Intel Corporation2*3* Permission is hereby granted, free of charge, to any person obtaining a4* copy of this software and associated documentation files (the "Software"),5* to deal in the Software without restriction, including without limitation6* the rights to use, copy, modify, merge, publish, distribute, sublicense,7* and/or sell copies of the Software, and to permit persons to whom the8* Software is furnished to do so, subject to the following conditions:9*10* The above copyright notice and this permission notice (including the next11* paragraph) shall be included in all copies or substantial portions of the12* Software.13*14* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER18* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING19* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS20* IN THE SOFTWARE.21*/2223#ifndef INTEL_CONTEXT_H24#define INTEL_CONTEXT_H2526#include <stdint.h>2728#define RING_SIZE (1 * 4096)29#define PPHWSP_SIZE (1 * 4096)3031#define GFX11_LR_CONTEXT_RENDER_SIZE (14 * 4096)32#define GFX10_LR_CONTEXT_RENDER_SIZE (19 * 4096)33#define GFX9_LR_CONTEXT_RENDER_SIZE (22 * 4096)34#define GFX8_LR_CONTEXT_RENDER_SIZE (20 * 4096)35#define GFX8_LR_CONTEXT_OTHER_SIZE (2 * 4096)3637#define CONTEXT_RENDER_SIZE GFX9_LR_CONTEXT_RENDER_SIZE /* largest size */38#define CONTEXT_OTHER_SIZE GFX8_LR_CONTEXT_OTHER_SIZE3940#define MI_LOAD_REGISTER_IMM_n(n) ((0x22 << 23) | (2 * (n) - 1))41#define MI_LRI_FORCE_POSTED (1<<12)4243#define MI_BATCH_BUFFER_END (0xA << 23)4445#define HWS_PGA_RCSUNIT 0x0208046#define HWS_PGA_VCSUNIT0 0x1208047#define HWS_PGA_BCSUNIT 0x220804849#define GFX_MODE_RCSUNIT 0x0229c50#define GFX_MODE_VCSUNIT0 0x1229c51#define GFX_MODE_BCSUNIT 0x2229c5253#define EXECLIST_SUBMITPORT_RCSUNIT 0x0223054#define EXECLIST_SUBMITPORT_VCSUNIT0 0x1223055#define EXECLIST_SUBMITPORT_BCSUNIT 0x222305657#define EXECLIST_STATUS_RCSUNIT 0x0223458#define EXECLIST_STATUS_VCSUNIT0 0x1223459#define EXECLIST_STATUS_BCSUNIT 0x222346061#define EXECLIST_SQ_CONTENTS0_RCSUNIT 0x0251062#define EXECLIST_SQ_CONTENTS0_VCSUNIT0 0x1251063#define EXECLIST_SQ_CONTENTS0_BCSUNIT 0x225106465#define EXECLIST_CONTROL_RCSUNIT 0x0255066#define EXECLIST_CONTROL_VCSUNIT0 0x1255067#define EXECLIST_CONTROL_BCSUNIT 0x225506869#define MEMORY_MAP_SIZE (64 /* MiB */ * 1024 * 1024)7071#define PTE_SIZE 472#define GFX8_PTE_SIZE 87374#define NUM_PT_ENTRIES (ALIGN(MEMORY_MAP_SIZE, 4096) / 4096)75#define PT_SIZE ALIGN(NUM_PT_ENTRIES * GFX8_PTE_SIZE, 4096)7677#define CONTEXT_FLAGS (0x339) /* Normal Priority | L3-LLC Coherency |78* PPGTT Enabled |79* Legacy Context with 64 bit VA support |80* Valid81*/8283#define MI_LOAD_REGISTER_IMM_vals(data, flags, ...) do { \84uint32_t __regs[] = { __VA_ARGS__ }; \85assert((ARRAY_SIZE(__regs) % 2) == 0); \86*(data)++ = MI_LOAD_REGISTER_IMM_n(ARRAY_SIZE(__regs) / 2) | (flags); \87for (unsigned __e = 0; __e < ARRAY_SIZE(__regs); __e++) \88*(data)++ = __regs[__e]; \89} while (0)909192struct intel_context_parameters {93uint64_t pml4_addr;94uint64_t ring_addr;95uint32_t ring_size;96};9798typedef void (*intel_context_init_t)(const struct intel_context_parameters *, uint32_t *, uint32_t *);99100#include "gfx8_context.h"101#include "gfx10_context.h"102103#endif /* INTEL_CONTEXT_H */104105106