Path: blob/21.2-virgl/src/intel/vulkan/anv_nir.h
4547 views
/*1* Copyright © 2015 Intel Corporation2*3* Permission is hereby granted, free of charge, to any person obtaining a4* copy of this software and associated documentation files (the "Software"),5* to deal in the Software without restriction, including without limitation6* the rights to use, copy, modify, merge, publish, distribute, sublicense,7* and/or sell copies of the Software, and to permit persons to whom the8* Software is furnished to do so, subject to the following conditions:9*10* The above copyright notice and this permission notice (including the next11* paragraph) shall be included in all copies or substantial portions of the12* Software.13*14* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER18* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING19* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS20* IN THE SOFTWARE.21*/2223#ifndef ANV_NIR_H24#define ANV_NIR_H2526#include "nir/nir.h"27#include "anv_private.h"2829#ifdef __cplusplus30extern "C" {31#endif3233bool anv_check_for_primitive_replication(nir_shader **shaders,34struct anv_graphics_pipeline *pipeline);3536bool anv_nir_lower_multiview(nir_shader *shader,37struct anv_graphics_pipeline *pipeline);3839bool anv_nir_lower_ycbcr_textures(nir_shader *shader,40const struct anv_pipeline_layout *layout);4142static inline nir_address_format43anv_nir_ssbo_addr_format(const struct anv_physical_device *pdevice,44bool robust_buffer_access)45{46if (pdevice->has_a64_buffer_access) {47if (robust_buffer_access)48return nir_address_format_64bit_bounded_global;49else50return nir_address_format_64bit_global_32bit_offset;51} else {52return nir_address_format_32bit_index_offset;53}54}5556static inline nir_address_format57anv_nir_ubo_addr_format(const struct anv_physical_device *pdevice,58bool robust_buffer_access)59{60if (pdevice->has_a64_buffer_access) {61if (robust_buffer_access)62return nir_address_format_64bit_bounded_global;63else64return nir_address_format_64bit_global_32bit_offset;65} else {66return nir_address_format_32bit_index_offset;67}68}6970bool anv_nir_lower_ubo_loads(nir_shader *shader);7172void anv_nir_apply_pipeline_layout(const struct anv_physical_device *pdevice,73bool robust_buffer_access,74const struct anv_pipeline_layout *layout,75nir_shader *shader,76struct anv_pipeline_bind_map *map);7778void anv_nir_compute_push_layout(const struct anv_physical_device *pdevice,79bool robust_buffer_access,80nir_shader *nir,81struct brw_stage_prog_data *prog_data,82struct anv_pipeline_bind_map *map,83void *mem_ctx);8485void anv_nir_validate_push_layout(struct brw_stage_prog_data *prog_data,86struct anv_pipeline_bind_map *map);8788bool anv_nir_add_base_work_group_id(nir_shader *shader);8990#ifdef __cplusplus91}92#endif9394#endif /* ANV_NIR_H */959697