Path: blob/21.2-virgl/src/intel/vulkan/anv_nir_lower_ycbcr_textures.c
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/*1* Copyright © 2017 Intel Corporation2*3* Permission is hereby granted, free of charge, to any person obtaining a4* copy of this software and associated documentation files (the "Software"),5* to deal in the Software without restriction, including without limitation6* the rights to use, copy, modify, merge, publish, distribute, sublicense,7* and/or sell copies of the Software, and to permit persons to whom the8* Software is furnished to do so, subject to the following conditions:9*10* The above copyright notice and this permission notice (including the next11* paragraph) shall be included in all copies or substantial portions of the12* Software.13*14* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER18* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING19* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS20* IN THE SOFTWARE.21*/2223#include "anv_nir.h"24#include "anv_private.h"25#include "nir/nir.h"26#include "nir/nir_builder.h"27#include "nir/nir_vulkan.h"2829struct ycbcr_state {30nir_builder *builder;31nir_ssa_def *image_size;32nir_tex_instr *origin_tex;33nir_deref_instr *tex_deref;34struct anv_ycbcr_conversion *conversion;35};3637/* TODO: we should probably replace this with a push constant/uniform. */38static nir_ssa_def *39get_texture_size(struct ycbcr_state *state, nir_deref_instr *texture)40{41if (state->image_size)42return state->image_size;4344nir_builder *b = state->builder;45const struct glsl_type *type = texture->type;46nir_tex_instr *tex = nir_tex_instr_create(b->shader, 1);4748tex->op = nir_texop_txs;49tex->sampler_dim = glsl_get_sampler_dim(type);50tex->is_array = glsl_sampler_type_is_array(type);51tex->is_shadow = glsl_sampler_type_is_shadow(type);52tex->dest_type = nir_type_int32;5354tex->src[0].src_type = nir_tex_src_texture_deref;55tex->src[0].src = nir_src_for_ssa(&texture->dest.ssa);5657nir_ssa_dest_init(&tex->instr, &tex->dest,58nir_tex_instr_dest_size(tex), 32, NULL);59nir_builder_instr_insert(b, &tex->instr);6061state->image_size = nir_i2f32(b, &tex->dest.ssa);6263return state->image_size;64}6566static nir_ssa_def *67implicit_downsampled_coord(nir_builder *b,68nir_ssa_def *value,69nir_ssa_def *max_value,70int div_scale)71{72return nir_fadd(b,73value,74nir_fdiv(b,75nir_imm_float(b, 1.0f),76nir_fmul(b,77nir_imm_float(b, div_scale),78max_value)));79}8081static nir_ssa_def *82implicit_downsampled_coords(struct ycbcr_state *state,83nir_ssa_def *old_coords,84const struct anv_format_plane *plane_format)85{86nir_builder *b = state->builder;87struct anv_ycbcr_conversion *conversion = state->conversion;88nir_ssa_def *image_size = get_texture_size(state, state->tex_deref);89nir_ssa_def *comp[4] = { NULL, };90int c;9192for (c = 0; c < ARRAY_SIZE(conversion->chroma_offsets); c++) {93if (plane_format->denominator_scales[c] > 1 &&94conversion->chroma_offsets[c] == VK_CHROMA_LOCATION_COSITED_EVEN) {95comp[c] = implicit_downsampled_coord(b,96nir_channel(b, old_coords, c),97nir_channel(b, image_size, c),98plane_format->denominator_scales[c]);99} else {100comp[c] = nir_channel(b, old_coords, c);101}102}103104/* Leave other coordinates untouched */105for (; c < old_coords->num_components; c++)106comp[c] = nir_channel(b, old_coords, c);107108return nir_vec(b, comp, old_coords->num_components);109}110111static nir_ssa_def *112create_plane_tex_instr_implicit(struct ycbcr_state *state,113uint32_t plane)114{115nir_builder *b = state->builder;116struct anv_ycbcr_conversion *conversion = state->conversion;117const struct anv_format_plane *plane_format =118&conversion->format->planes[plane];119nir_tex_instr *old_tex = state->origin_tex;120nir_tex_instr *tex = nir_tex_instr_create(b->shader, old_tex->num_srcs + 1);121122for (uint32_t i = 0; i < old_tex->num_srcs; i++) {123tex->src[i].src_type = old_tex->src[i].src_type;124125switch (old_tex->src[i].src_type) {126case nir_tex_src_coord:127if (plane_format->has_chroma && conversion->chroma_reconstruction) {128assert(old_tex->src[i].src.is_ssa);129tex->src[i].src =130nir_src_for_ssa(implicit_downsampled_coords(state,131old_tex->src[i].src.ssa,132plane_format));133break;134}135FALLTHROUGH;136default:137nir_src_copy(&tex->src[i].src, &old_tex->src[i].src, tex);138break;139}140}141tex->src[tex->num_srcs - 1].src = nir_src_for_ssa(nir_imm_int(b, plane));142tex->src[tex->num_srcs - 1].src_type = nir_tex_src_plane;143144tex->sampler_dim = old_tex->sampler_dim;145tex->dest_type = old_tex->dest_type;146147tex->op = old_tex->op;148tex->coord_components = old_tex->coord_components;149tex->is_new_style_shadow = old_tex->is_new_style_shadow;150tex->component = old_tex->component;151152tex->texture_index = old_tex->texture_index;153tex->sampler_index = old_tex->sampler_index;154tex->is_array = old_tex->is_array;155156nir_ssa_dest_init(&tex->instr, &tex->dest,157old_tex->dest.ssa.num_components,158nir_dest_bit_size(old_tex->dest), NULL);159nir_builder_instr_insert(b, &tex->instr);160161return &tex->dest.ssa;162}163164static unsigned165channel_to_component(enum isl_channel_select channel)166{167switch (channel) {168case ISL_CHANNEL_SELECT_RED:169return 0;170case ISL_CHANNEL_SELECT_GREEN:171return 1;172case ISL_CHANNEL_SELECT_BLUE:173return 2;174case ISL_CHANNEL_SELECT_ALPHA:175return 3;176default:177unreachable("invalid channel");178return 0;179}180}181182static enum isl_channel_select183swizzle_channel(struct isl_swizzle swizzle, unsigned channel)184{185switch (channel) {186case 0:187return swizzle.r;188case 1:189return swizzle.g;190case 2:191return swizzle.b;192case 3:193return swizzle.a;194default:195unreachable("invalid channel");196return 0;197}198}199200static bool201try_lower_tex_ycbcr(const struct anv_pipeline_layout *layout,202nir_builder *builder,203nir_tex_instr *tex)204{205int deref_src_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_deref);206assert(deref_src_idx >= 0);207nir_deref_instr *deref = nir_src_as_deref(tex->src[deref_src_idx].src);208209nir_variable *var = nir_deref_instr_get_variable(deref);210const struct anv_descriptor_set_layout *set_layout =211layout->set[var->data.descriptor_set].layout;212const struct anv_descriptor_set_binding_layout *binding =213&set_layout->binding[var->data.binding];214215/* For the following instructions, we don't apply any change and let the216* instruction apply to the first plane.217*/218if (tex->op == nir_texop_txs ||219tex->op == nir_texop_query_levels ||220tex->op == nir_texop_lod)221return false;222223if (binding->immutable_samplers == NULL)224return false;225226assert(tex->texture_index == 0);227unsigned array_index = 0;228if (deref->deref_type != nir_deref_type_var) {229assert(deref->deref_type == nir_deref_type_array);230if (!nir_src_is_const(deref->arr.index))231return false;232array_index = nir_src_as_uint(deref->arr.index);233array_index = MIN2(array_index, binding->array_size - 1);234}235const struct anv_sampler *sampler = binding->immutable_samplers[array_index];236237if (sampler->conversion == NULL)238return false;239240struct ycbcr_state state = {241.builder = builder,242.origin_tex = tex,243.tex_deref = deref,244.conversion = sampler->conversion,245};246247builder->cursor = nir_before_instr(&tex->instr);248249const struct anv_format *format = state.conversion->format;250const struct isl_format_layout *y_isl_layout = NULL;251for (uint32_t p = 0; p < format->n_planes; p++) {252if (!format->planes[p].has_chroma)253y_isl_layout = isl_format_get_layout(format->planes[p].isl_format);254}255assert(y_isl_layout != NULL);256uint8_t y_bpc = y_isl_layout->channels_array[0].bits;257258/* |ycbcr_comp| holds components in the order : Cr-Y-Cb */259nir_ssa_def *zero = nir_imm_float(builder, 0.0f);260nir_ssa_def *one = nir_imm_float(builder, 1.0f);261/* Use extra 2 channels for following swizzle */262nir_ssa_def *ycbcr_comp[5] = { zero, zero, zero, one, zero };263264uint8_t ycbcr_bpcs[5];265memset(ycbcr_bpcs, y_bpc, sizeof(ycbcr_bpcs));266267/* Go through all the planes and gather the samples into a |ycbcr_comp|268* while applying a swizzle required by the spec:269*270* R, G, B should respectively map to Cr, Y, Cb271*/272for (uint32_t p = 0; p < format->n_planes; p++) {273const struct anv_format_plane *plane_format = &format->planes[p];274nir_ssa_def *plane_sample = create_plane_tex_instr_implicit(&state, p);275276for (uint32_t pc = 0; pc < 4; pc++) {277enum isl_channel_select ycbcr_swizzle =278swizzle_channel(plane_format->ycbcr_swizzle, pc);279if (ycbcr_swizzle == ISL_CHANNEL_SELECT_ZERO)280continue;281282unsigned ycbcr_component = channel_to_component(ycbcr_swizzle);283ycbcr_comp[ycbcr_component] = nir_channel(builder, plane_sample, pc);284285/* Also compute the number of bits for each component. */286const struct isl_format_layout *isl_layout =287isl_format_get_layout(plane_format->isl_format);288ycbcr_bpcs[ycbcr_component] = isl_layout->channels_array[pc].bits;289}290}291292/* Now remaps components to the order specified by the conversion. */293nir_ssa_def *swizzled_comp[4] = { NULL, };294uint32_t swizzled_bpcs[4] = { 0, };295296for (uint32_t i = 0; i < ARRAY_SIZE(state.conversion->mapping); i++) {297/* Maps to components in |ycbcr_comp| */298static const uint32_t swizzle_mapping[] = {299[VK_COMPONENT_SWIZZLE_ZERO] = 4,300[VK_COMPONENT_SWIZZLE_ONE] = 3,301[VK_COMPONENT_SWIZZLE_R] = 0,302[VK_COMPONENT_SWIZZLE_G] = 1,303[VK_COMPONENT_SWIZZLE_B] = 2,304[VK_COMPONENT_SWIZZLE_A] = 3,305};306const VkComponentSwizzle m = state.conversion->mapping[i];307308if (m == VK_COMPONENT_SWIZZLE_IDENTITY) {309swizzled_comp[i] = ycbcr_comp[i];310swizzled_bpcs[i] = ycbcr_bpcs[i];311} else {312swizzled_comp[i] = ycbcr_comp[swizzle_mapping[m]];313swizzled_bpcs[i] = ycbcr_bpcs[swizzle_mapping[m]];314}315}316317nir_ssa_def *result = nir_vec(builder, swizzled_comp, 4);318if (state.conversion->ycbcr_model != VK_SAMPLER_YCBCR_MODEL_CONVERSION_RGB_IDENTITY) {319result = nir_convert_ycbcr_to_rgb(builder,320state.conversion->ycbcr_model,321state.conversion->ycbcr_range,322result,323swizzled_bpcs);324}325326nir_ssa_def_rewrite_uses(&tex->dest.ssa, result);327nir_instr_remove(&tex->instr);328329return true;330}331332bool333anv_nir_lower_ycbcr_textures(nir_shader *shader,334const struct anv_pipeline_layout *layout)335{336bool progress = false;337338nir_foreach_function(function, shader) {339if (!function->impl)340continue;341342bool function_progress = false;343nir_builder builder;344nir_builder_init(&builder, function->impl);345346nir_foreach_block(block, function->impl) {347nir_foreach_instr_safe(instr, block) {348if (instr->type != nir_instr_type_tex)349continue;350351nir_tex_instr *tex = nir_instr_as_tex(instr);352function_progress |= try_lower_tex_ycbcr(layout, &builder, tex);353}354}355356if (function_progress) {357nir_metadata_preserve(function->impl,358nir_metadata_block_index |359nir_metadata_dominance);360}361362progress |= function_progress;363}364365return progress;366}367368369