Path: blob/21.2-virgl/src/intel/vulkan/genX_gpu_memcpy.c
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/*1* Copyright © 2016 Intel Corporation2*3* Permission is hereby granted, free of charge, to any person obtaining a4* copy of this software and associated documentation files (the "Software"),5* to deal in the Software without restriction, including without limitation6* the rights to use, copy, modify, merge, publish, distribute, sublicense,7* and/or sell copies of the Software, and to permit persons to whom the8* Software is furnished to do so, subject to the following conditions:9*10* The above copyright notice and this permission notice (including the next11* paragraph) shall be included in all copies or substantial portions of the12* Software.13*14* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER18* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING19* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS20* IN THE SOFTWARE.21*/2223#include "anv_private.h"2425#include "genxml/gen_macros.h"26#include "genxml/genX_pack.h"2728#include "common/intel_l3_config.h"2930/**31* This file implements some lightweight memcpy/memset operations on the GPU32* using a vertex buffer and streamout.33*/3435/**36* Returns the greatest common divisor of a and b that is a power of two.37*/38static uint64_t39gcd_pow2_u64(uint64_t a, uint64_t b)40{41assert(a > 0 || b > 0);4243unsigned a_log2 = ffsll(a) - 1;44unsigned b_log2 = ffsll(b) - 1;4546/* If either a or b is 0, then a_log2 or b_log2 will be UINT_MAX in which47* case, the MIN2() will take the other one. If both are 0 then we will48* hit the assert above.49*/50return 1 << MIN2(a_log2, b_log2);51}5253void54genX(cmd_buffer_so_memcpy)(struct anv_cmd_buffer *cmd_buffer,55struct anv_address dst, struct anv_address src,56uint32_t size)57{58if (size == 0)59return;6061/* The maximum copy block size is 4 32-bit components at a time. */62assert(size % 4 == 0);63unsigned bs = gcd_pow2_u64(16, size);6465enum isl_format format;66switch (bs) {67case 4: format = ISL_FORMAT_R32_UINT; break;68case 8: format = ISL_FORMAT_R32G32_UINT; break;69case 16: format = ISL_FORMAT_R32G32B32A32_UINT; break;70default:71unreachable("Invalid size");72}7374if (!cmd_buffer->state.current_l3_config) {75const struct intel_l3_config *cfg =76intel_get_default_l3_config(&cmd_buffer->device->info);77genX(cmd_buffer_config_l3)(cmd_buffer, cfg);78}7980genX(cmd_buffer_set_binding_for_gfx8_vb_flush)(cmd_buffer, 32, src, size);81genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);8283genX(flush_pipeline_select_3d)(cmd_buffer);8485uint32_t *dw;86dw = anv_batch_emitn(&cmd_buffer->batch, 5, GENX(3DSTATE_VERTEX_BUFFERS));87GENX(VERTEX_BUFFER_STATE_pack)(&cmd_buffer->batch, dw + 1,88&(struct GENX(VERTEX_BUFFER_STATE)) {89.VertexBufferIndex = 32, /* Reserved for this */90.AddressModifyEnable = true,91.BufferStartingAddress = src,92.BufferPitch = bs,93.MOCS = anv_mocs(cmd_buffer->device, src.bo, 0),94#if GFX_VER >= 1295.L3BypassDisable = true,96#endif97#if (GFX_VER >= 8)98.BufferSize = size,99#else100.EndAddress = anv_address_add(src, size - 1),101#endif102});103104dw = anv_batch_emitn(&cmd_buffer->batch, 3, GENX(3DSTATE_VERTEX_ELEMENTS));105GENX(VERTEX_ELEMENT_STATE_pack)(&cmd_buffer->batch, dw + 1,106&(struct GENX(VERTEX_ELEMENT_STATE)) {107.VertexBufferIndex = 32,108.Valid = true,109.SourceElementFormat = format,110.SourceElementOffset = 0,111.Component0Control = (bs >= 4) ? VFCOMP_STORE_SRC : VFCOMP_STORE_0,112.Component1Control = (bs >= 8) ? VFCOMP_STORE_SRC : VFCOMP_STORE_0,113.Component2Control = (bs >= 12) ? VFCOMP_STORE_SRC : VFCOMP_STORE_0,114.Component3Control = (bs >= 16) ? VFCOMP_STORE_SRC : VFCOMP_STORE_0,115});116117#if GFX_VER >= 8118anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_VF_INSTANCING), vfi) {119vfi.InstancingEnable = false;120vfi.VertexElementIndex = 0;121}122#endif123124#if GFX_VER >= 8125anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_VF_SGVS), sgvs);126#endif127128/* Disable all shader stages */129anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_VS), vs);130anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_HS), hs);131anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_TE), te);132anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_DS), DS);133anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_GS), gs);134anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_PS), gs);135136anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_SBE), sbe) {137sbe.VertexURBEntryReadOffset = 1;138sbe.NumberofSFOutputAttributes = 1;139sbe.VertexURBEntryReadLength = 1;140#if GFX_VER >= 8141sbe.ForceVertexURBEntryReadLength = true;142sbe.ForceVertexURBEntryReadOffset = true;143#endif144145#if GFX_VER >= 9146for (unsigned i = 0; i < 32; i++)147sbe.AttributeActiveComponentFormat[i] = ACF_XYZW;148#endif149}150151/* Emit URB setup. We tell it that the VS is active because we want it to152* allocate space for the VS. Even though one isn't run, we need VUEs to153* store the data that VF is going to pass to SOL.154*/155const unsigned entry_size[4] = { DIV_ROUND_UP(32, 64), 1, 1, 1 };156157genX(emit_urb_setup)(cmd_buffer->device, &cmd_buffer->batch,158cmd_buffer->state.current_l3_config,159VK_SHADER_STAGE_VERTEX_BIT, entry_size, NULL);160161anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_SO_BUFFER), sob) {162#if GFX_VER < 12163sob.SOBufferIndex = 0;164#else165sob._3DCommandOpcode = 0;166sob._3DCommandSubOpcode = SO_BUFFER_INDEX_0_CMD;167#endif168sob.MOCS = anv_mocs(cmd_buffer->device, dst.bo, 0),169sob.SurfaceBaseAddress = dst;170171#if GFX_VER >= 8172sob.SOBufferEnable = true;173sob.SurfaceSize = size / 4 - 1;174#else175sob.SurfacePitch = bs;176sob.SurfaceEndAddress = anv_address_add(dst, size);177#endif178179#if GFX_VER >= 8180/* As SOL writes out data, it updates the SO_WRITE_OFFSET registers with181* the end position of the stream. We need to reset this value to 0 at182* the beginning of the run or else SOL will start at the offset from183* the previous draw.184*/185sob.StreamOffsetWriteEnable = true;186sob.StreamOffset = 0;187#endif188}189190#if GFX_VER <= 7191/* The hardware can do this for us on BDW+ (see above) */192anv_batch_emit(&cmd_buffer->batch, GENX(MI_LOAD_REGISTER_IMM), load) {193load.RegisterOffset = GENX(SO_WRITE_OFFSET0_num);194load.DataDWord = 0;195}196#endif197198dw = anv_batch_emitn(&cmd_buffer->batch, 5, GENX(3DSTATE_SO_DECL_LIST),199.StreamtoBufferSelects0 = (1 << 0),200.NumEntries0 = 1);201GENX(SO_DECL_ENTRY_pack)(&cmd_buffer->batch, dw + 3,202&(struct GENX(SO_DECL_ENTRY)) {203.Stream0Decl = {204.OutputBufferSlot = 0,205.RegisterIndex = 0,206.ComponentMask = (1 << (bs / 4)) - 1,207},208});209210anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_STREAMOUT), so) {211so.SOFunctionEnable = true;212so.RenderingDisable = true;213so.Stream0VertexReadOffset = 0;214so.Stream0VertexReadLength = DIV_ROUND_UP(32, 64);215#if GFX_VER >= 8216so.Buffer0SurfacePitch = bs;217#else218so.SOBufferEnable0 = true;219#endif220}221222#if GFX_VER >= 8223anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_VF_TOPOLOGY), topo) {224topo.PrimitiveTopologyType = _3DPRIM_POINTLIST;225}226#endif227228anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_VF_STATISTICS), vf) {229vf.StatisticsEnable = false;230}231232#if GFX_VER >= 12233/* Disable Primitive Replication. */234anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_PRIMITIVE_REPLICATION), pr);235#endif236237anv_batch_emit(&cmd_buffer->batch, GENX(3DPRIMITIVE), prim) {238prim.VertexAccessType = SEQUENTIAL;239prim.PrimitiveTopologyType = _3DPRIM_POINTLIST;240prim.VertexCountPerInstance = size / bs;241prim.StartVertexLocation = 0;242prim.InstanceCount = 1;243prim.StartInstanceLocation = 0;244prim.BaseVertexLocation = 0;245}246247genX(cmd_buffer_update_dirty_vbs_for_gfx8_vb_flush)(cmd_buffer, SEQUENTIAL,2481ull << 32);249250cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_PIPELINE;251}252253254