Path: blob/21.2-virgl/src/panfrost/midgard/midgard_opt_dce.c
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/*1* Copyright (C) 2018 Alyssa Rosenzweig2* Copyright (C) 2019 Collabora, Ltd.3*4* Permission is hereby granted, free of charge, to any person obtaining a5* copy of this software and associated documentation files (the "Software"),6* to deal in the Software without restriction, including without limitation7* the rights to use, copy, modify, merge, publish, distribute, sublicense,8* and/or sell copies of the Software, and to permit persons to whom the9* Software is furnished to do so, subject to the following conditions:10*11* The above copyright notice and this permission notice (including the next12* paragraph) shall be included in all copies or substantial portions of the13* Software.14*15* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR16* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,17* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL18* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER19* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,20* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE21* SOFTWARE.22*/2324#include "compiler.h"25#include "util/u_memory.h"26#include "midgard_ops.h"2728/* SIMD-aware dead code elimination. Perform liveness analysis step-by-step,29* removing dead components. If an instruction ends up with a zero mask, the30* instruction in total is dead and should be removed. */3132static bool33can_cull_mask(compiler_context *ctx, midgard_instruction *ins)34{35if (ins->dest >= ctx->temp_count)36return false;3738if (ins->dest == ctx->blend_src1)39return false;4041if (ins->type == TAG_LOAD_STORE_4)42if (load_store_opcode_props[ins->op].props & LDST_SPECIAL_MASK)43return false;4445return true;46}4748static bool49can_dce(midgard_instruction *ins)50{51if (ins->mask)52return false;5354if (ins->compact_branch)55return false;5657if (ins->type == TAG_LOAD_STORE_4)58if (load_store_opcode_props[ins->op].props & LDST_SIDE_FX)59return false;6061if (ins->type == TAG_TEXTURE_4)62if (ins->op == midgard_tex_op_barrier)63return false;6465return true;66}6768static bool69midgard_opt_dead_code_eliminate_block(compiler_context *ctx, midgard_block *block)70{71bool progress = false;7273uint16_t *live = mem_dup(block->base.live_out, ctx->temp_count * sizeof(uint16_t));7475mir_foreach_instr_in_block_rev(block, ins) {76if (can_cull_mask(ctx, ins)) {77unsigned type_size = nir_alu_type_get_type_size(ins->dest_type);78unsigned round_size = type_size;79unsigned oldmask = ins->mask;8081/* Make sure we're packable */82if (type_size == 16 && ins->type == TAG_LOAD_STORE_4)83round_size = 32;8485unsigned rounded = mir_round_bytemask_up(live[ins->dest], round_size);86unsigned cmask = mir_from_bytemask(rounded, type_size);8788ins->mask &= cmask;89progress |= (ins->mask != oldmask);90}9192mir_liveness_ins_update(live, ins, ctx->temp_count);93}9495mir_foreach_instr_in_block_safe(block, ins) {96if (can_dce(ins)) {97mir_remove_instruction(ins);98progress = true;99}100}101102free(live);103104return progress;105}106107bool108midgard_opt_dead_code_eliminate(compiler_context *ctx)109{110/* We track liveness. In fact, it's ok if we assume more things are111* live than they actually are, that just reduces the effectiveness of112* this iterations lightly. And DCE has the effect of strictly reducing113* liveness, so we can run DCE across all blocks while only computing114* liveness at the beginning. */115116mir_invalidate_liveness(ctx);117mir_compute_liveness(ctx);118119bool progress = false;120121mir_foreach_block(ctx, block) {122progress |= midgard_opt_dead_code_eliminate_block(ctx, (midgard_block *) block);123}124125return progress;126}127128/* Removes dead moves, that is, moves with a destination overwritten before129* being read. Normally handled implicitly as part of DCE, but this has to run130* after the out-of-SSA pass */131132bool133midgard_opt_dead_move_eliminate(compiler_context *ctx, midgard_block *block)134{135bool progress = false;136137mir_foreach_instr_in_block_safe(block, ins) {138if (ins->type != TAG_ALU_4) continue;139if (ins->compact_branch) continue;140if (!OP_IS_MOVE(ins->op)) continue;141142/* Check if it's overwritten in this block before being read */143bool overwritten = false;144145mir_foreach_instr_in_block_from(block, q, mir_next_op(ins)) {146/* Check if used */147if (mir_has_arg(q, ins->dest))148break;149150/* Check if overwritten */151if (q->dest == ins->dest) {152/* Special case to vec4; component tracking is153* harder */154155overwritten = (q->mask == 0xF);156break;157}158}159160if (overwritten) {161mir_remove_instruction(ins);162progress = true;163}164}165166return progress;167}168169170