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PojavLauncherTeam
GitHub Repository: PojavLauncherTeam/mesa
Path: blob/21.2-virgl/src/virtio/virtio-gpu/virgl_hw.h
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/*
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* Copyright 2014, 2015 Red Hat.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* on the rights to use, copy, modify, merge, publish, distribute, sub
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* license, and/or sell copies of the Software, and to permit persons to whom
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* the Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef VIRGL_HW_H
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#define VIRGL_HW_H
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#include <stdint.h>
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struct virgl_box {
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uint32_t x, y, z;
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uint32_t w, h, d;
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};
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/* formats known by the HW device - based on gallium subset */
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enum virgl_formats {
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VIRGL_FORMAT_NONE = 0,
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VIRGL_FORMAT_B8G8R8A8_UNORM = 1,
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VIRGL_FORMAT_B8G8R8X8_UNORM = 2,
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VIRGL_FORMAT_A8R8G8B8_UNORM = 3,
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VIRGL_FORMAT_X8R8G8B8_UNORM = 4,
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VIRGL_FORMAT_B5G5R5A1_UNORM = 5,
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VIRGL_FORMAT_B4G4R4A4_UNORM = 6,
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VIRGL_FORMAT_B5G6R5_UNORM = 7,
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VIRGL_FORMAT_R10G10B10A2_UNORM = 8,
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VIRGL_FORMAT_L8_UNORM = 9, /**< ubyte luminance */
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VIRGL_FORMAT_A8_UNORM = 10, /**< ubyte alpha */
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VIRGL_FORMAT_I8_UNORM = 11,
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VIRGL_FORMAT_L8A8_UNORM = 12, /**< ubyte alpha, luminance */
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VIRGL_FORMAT_L16_UNORM = 13, /**< ushort luminance */
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VIRGL_FORMAT_UYVY = 14,
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VIRGL_FORMAT_YUYV = 15,
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VIRGL_FORMAT_Z16_UNORM = 16,
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VIRGL_FORMAT_Z32_UNORM = 17,
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VIRGL_FORMAT_Z32_FLOAT = 18,
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VIRGL_FORMAT_Z24_UNORM_S8_UINT = 19,
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VIRGL_FORMAT_S8_UINT_Z24_UNORM = 20,
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VIRGL_FORMAT_Z24X8_UNORM = 21,
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VIRGL_FORMAT_X8Z24_UNORM = 22,
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VIRGL_FORMAT_S8_UINT = 23, /**< ubyte stencil */
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VIRGL_FORMAT_R64_FLOAT = 24,
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VIRGL_FORMAT_R64G64_FLOAT = 25,
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VIRGL_FORMAT_R64G64B64_FLOAT = 26,
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VIRGL_FORMAT_R64G64B64A64_FLOAT = 27,
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VIRGL_FORMAT_R32_FLOAT = 28,
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VIRGL_FORMAT_R32G32_FLOAT = 29,
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VIRGL_FORMAT_R32G32B32_FLOAT = 30,
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VIRGL_FORMAT_R32G32B32A32_FLOAT = 31,
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VIRGL_FORMAT_R32_UNORM = 32,
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VIRGL_FORMAT_R32G32_UNORM = 33,
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VIRGL_FORMAT_R32G32B32_UNORM = 34,
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VIRGL_FORMAT_R32G32B32A32_UNORM = 35,
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VIRGL_FORMAT_R32_USCALED = 36,
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VIRGL_FORMAT_R32G32_USCALED = 37,
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VIRGL_FORMAT_R32G32B32_USCALED = 38,
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VIRGL_FORMAT_R32G32B32A32_USCALED = 39,
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VIRGL_FORMAT_R32_SNORM = 40,
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VIRGL_FORMAT_R32G32_SNORM = 41,
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VIRGL_FORMAT_R32G32B32_SNORM = 42,
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VIRGL_FORMAT_R32G32B32A32_SNORM = 43,
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VIRGL_FORMAT_R32_SSCALED = 44,
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VIRGL_FORMAT_R32G32_SSCALED = 45,
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VIRGL_FORMAT_R32G32B32_SSCALED = 46,
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VIRGL_FORMAT_R32G32B32A32_SSCALED = 47,
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VIRGL_FORMAT_R16_UNORM = 48,
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VIRGL_FORMAT_R16G16_UNORM = 49,
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VIRGL_FORMAT_R16G16B16_UNORM = 50,
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VIRGL_FORMAT_R16G16B16A16_UNORM = 51,
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VIRGL_FORMAT_R16_USCALED = 52,
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VIRGL_FORMAT_R16G16_USCALED = 53,
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VIRGL_FORMAT_R16G16B16_USCALED = 54,
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VIRGL_FORMAT_R16G16B16A16_USCALED = 55,
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VIRGL_FORMAT_R16_SNORM = 56,
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VIRGL_FORMAT_R16G16_SNORM = 57,
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VIRGL_FORMAT_R16G16B16_SNORM = 58,
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VIRGL_FORMAT_R16G16B16A16_SNORM = 59,
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VIRGL_FORMAT_R16_SSCALED = 60,
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VIRGL_FORMAT_R16G16_SSCALED = 61,
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VIRGL_FORMAT_R16G16B16_SSCALED = 62,
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VIRGL_FORMAT_R16G16B16A16_SSCALED = 63,
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VIRGL_FORMAT_R8_UNORM = 64,
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VIRGL_FORMAT_R8G8_UNORM = 65,
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VIRGL_FORMAT_R8G8B8_UNORM = 66,
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VIRGL_FORMAT_R8G8B8A8_UNORM = 67,
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VIRGL_FORMAT_X8B8G8R8_UNORM = 68,
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VIRGL_FORMAT_R8_USCALED = 69,
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VIRGL_FORMAT_R8G8_USCALED = 70,
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VIRGL_FORMAT_R8G8B8_USCALED = 71,
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VIRGL_FORMAT_R8G8B8A8_USCALED = 72,
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VIRGL_FORMAT_R8_SNORM = 74,
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VIRGL_FORMAT_R8G8_SNORM = 75,
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VIRGL_FORMAT_R8G8B8_SNORM = 76,
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VIRGL_FORMAT_R8G8B8A8_SNORM = 77,
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VIRGL_FORMAT_R8_SSCALED = 82,
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VIRGL_FORMAT_R8G8_SSCALED = 83,
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VIRGL_FORMAT_R8G8B8_SSCALED = 84,
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VIRGL_FORMAT_R8G8B8A8_SSCALED = 85,
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VIRGL_FORMAT_R32_FIXED = 87,
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VIRGL_FORMAT_R32G32_FIXED = 88,
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VIRGL_FORMAT_R32G32B32_FIXED = 89,
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VIRGL_FORMAT_R32G32B32A32_FIXED = 90,
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VIRGL_FORMAT_R16_FLOAT = 91,
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VIRGL_FORMAT_R16G16_FLOAT = 92,
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VIRGL_FORMAT_R16G16B16_FLOAT = 93,
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VIRGL_FORMAT_R16G16B16A16_FLOAT = 94,
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VIRGL_FORMAT_L8_SRGB = 95,
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VIRGL_FORMAT_L8A8_SRGB = 96,
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VIRGL_FORMAT_R8G8B8_SRGB = 97,
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VIRGL_FORMAT_A8B8G8R8_SRGB = 98,
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VIRGL_FORMAT_X8B8G8R8_SRGB = 99,
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VIRGL_FORMAT_B8G8R8A8_SRGB = 100,
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VIRGL_FORMAT_B8G8R8X8_SRGB = 101,
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VIRGL_FORMAT_A8R8G8B8_SRGB = 102,
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VIRGL_FORMAT_X8R8G8B8_SRGB = 103,
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VIRGL_FORMAT_R8G8B8A8_SRGB = 104,
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/* compressed formats */
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VIRGL_FORMAT_DXT1_RGB = 105,
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VIRGL_FORMAT_DXT1_RGBA = 106,
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VIRGL_FORMAT_DXT3_RGBA = 107,
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VIRGL_FORMAT_DXT5_RGBA = 108,
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/* sRGB, compressed */
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VIRGL_FORMAT_DXT1_SRGB = 109,
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VIRGL_FORMAT_DXT1_SRGBA = 110,
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VIRGL_FORMAT_DXT3_SRGBA = 111,
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VIRGL_FORMAT_DXT5_SRGBA = 112,
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/* rgtc compressed */
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VIRGL_FORMAT_RGTC1_UNORM = 113,
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VIRGL_FORMAT_RGTC1_SNORM = 114,
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VIRGL_FORMAT_RGTC2_UNORM = 115,
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VIRGL_FORMAT_RGTC2_SNORM = 116,
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VIRGL_FORMAT_R8G8_B8G8_UNORM = 117,
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VIRGL_FORMAT_G8R8_G8B8_UNORM = 118,
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VIRGL_FORMAT_R8SG8SB8UX8U_NORM = 119,
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VIRGL_FORMAT_R5SG5SB6U_NORM = 120,
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VIRGL_FORMAT_A8B8G8R8_UNORM = 121,
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VIRGL_FORMAT_B5G5R5X1_UNORM = 122,
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VIRGL_FORMAT_R10G10B10A2_USCALED = 123,
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VIRGL_FORMAT_R11G11B10_FLOAT = 124,
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VIRGL_FORMAT_R9G9B9E5_FLOAT = 125,
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VIRGL_FORMAT_Z32_FLOAT_S8X24_UINT = 126,
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VIRGL_FORMAT_R1_UNORM = 127,
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VIRGL_FORMAT_R10G10B10X2_USCALED = 128,
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VIRGL_FORMAT_R10G10B10X2_SNORM = 129,
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VIRGL_FORMAT_L4A4_UNORM = 130,
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VIRGL_FORMAT_B10G10R10A2_UNORM = 131,
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VIRGL_FORMAT_R10SG10SB10SA2U_NORM = 132,
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VIRGL_FORMAT_R8G8Bx_SNORM = 133,
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VIRGL_FORMAT_R8G8B8X8_UNORM = 134,
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VIRGL_FORMAT_B4G4R4X4_UNORM = 135,
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VIRGL_FORMAT_X24S8_UINT = 136,
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VIRGL_FORMAT_S8X24_UINT = 137,
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VIRGL_FORMAT_X32_S8X24_UINT = 138,
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VIRGL_FORMAT_B2G3R3_UNORM = 139,
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VIRGL_FORMAT_L16A16_UNORM = 140,
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VIRGL_FORMAT_A16_UNORM = 141,
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VIRGL_FORMAT_I16_UNORM = 142,
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VIRGL_FORMAT_LATC1_UNORM = 143,
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VIRGL_FORMAT_LATC1_SNORM = 144,
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VIRGL_FORMAT_LATC2_UNORM = 145,
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VIRGL_FORMAT_LATC2_SNORM = 146,
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VIRGL_FORMAT_A8_SNORM = 147,
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VIRGL_FORMAT_L8_SNORM = 148,
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VIRGL_FORMAT_L8A8_SNORM = 149,
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VIRGL_FORMAT_I8_SNORM = 150,
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VIRGL_FORMAT_A16_SNORM = 151,
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VIRGL_FORMAT_L16_SNORM = 152,
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VIRGL_FORMAT_L16A16_SNORM = 153,
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VIRGL_FORMAT_I16_SNORM = 154,
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VIRGL_FORMAT_A16_FLOAT = 155,
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VIRGL_FORMAT_L16_FLOAT = 156,
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VIRGL_FORMAT_L16A16_FLOAT = 157,
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VIRGL_FORMAT_I16_FLOAT = 158,
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VIRGL_FORMAT_A32_FLOAT = 159,
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VIRGL_FORMAT_L32_FLOAT = 160,
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VIRGL_FORMAT_L32A32_FLOAT = 161,
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VIRGL_FORMAT_I32_FLOAT = 162,
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VIRGL_FORMAT_YV12 = 163,
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VIRGL_FORMAT_YV16 = 164,
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VIRGL_FORMAT_IYUV = 165, /**< aka I420 */
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VIRGL_FORMAT_NV12 = 166,
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VIRGL_FORMAT_NV21 = 167,
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VIRGL_FORMAT_A4R4_UNORM = 168,
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VIRGL_FORMAT_R4A4_UNORM = 169,
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VIRGL_FORMAT_R8A8_UNORM = 170,
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VIRGL_FORMAT_A8R8_UNORM = 171,
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VIRGL_FORMAT_R10G10B10A2_SSCALED = 172,
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VIRGL_FORMAT_R10G10B10A2_SNORM = 173,
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VIRGL_FORMAT_B10G10R10A2_USCALED = 174,
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VIRGL_FORMAT_B10G10R10A2_SSCALED = 175,
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VIRGL_FORMAT_B10G10R10A2_SNORM = 176,
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VIRGL_FORMAT_R8_UINT = 177,
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VIRGL_FORMAT_R8G8_UINT = 178,
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VIRGL_FORMAT_R8G8B8_UINT = 179,
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VIRGL_FORMAT_R8G8B8A8_UINT = 180,
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VIRGL_FORMAT_R8_SINT = 181,
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VIRGL_FORMAT_R8G8_SINT = 182,
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VIRGL_FORMAT_R8G8B8_SINT = 183,
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VIRGL_FORMAT_R8G8B8A8_SINT = 184,
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VIRGL_FORMAT_R16_UINT = 185,
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VIRGL_FORMAT_R16G16_UINT = 186,
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VIRGL_FORMAT_R16G16B16_UINT = 187,
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VIRGL_FORMAT_R16G16B16A16_UINT = 188,
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VIRGL_FORMAT_R16_SINT = 189,
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VIRGL_FORMAT_R16G16_SINT = 190,
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VIRGL_FORMAT_R16G16B16_SINT = 191,
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VIRGL_FORMAT_R16G16B16A16_SINT = 192,
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VIRGL_FORMAT_R32_UINT = 193,
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VIRGL_FORMAT_R32G32_UINT = 194,
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VIRGL_FORMAT_R32G32B32_UINT = 195,
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VIRGL_FORMAT_R32G32B32A32_UINT = 196,
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VIRGL_FORMAT_R32_SINT = 197,
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VIRGL_FORMAT_R32G32_SINT = 198,
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VIRGL_FORMAT_R32G32B32_SINT = 199,
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VIRGL_FORMAT_R32G32B32A32_SINT = 200,
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VIRGL_FORMAT_A8_UINT = 201,
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VIRGL_FORMAT_I8_UINT = 202,
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VIRGL_FORMAT_L8_UINT = 203,
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VIRGL_FORMAT_L8A8_UINT = 204,
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VIRGL_FORMAT_A8_SINT = 205,
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VIRGL_FORMAT_I8_SINT = 206,
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VIRGL_FORMAT_L8_SINT = 207,
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VIRGL_FORMAT_L8A8_SINT = 208,
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VIRGL_FORMAT_A16_UINT = 209,
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VIRGL_FORMAT_I16_UINT = 210,
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VIRGL_FORMAT_L16_UINT = 211,
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VIRGL_FORMAT_L16A16_UINT = 212,
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VIRGL_FORMAT_A16_SINT = 213,
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VIRGL_FORMAT_I16_SINT = 214,
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VIRGL_FORMAT_L16_SINT = 215,
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VIRGL_FORMAT_L16A16_SINT = 216,
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VIRGL_FORMAT_A32_UINT = 217,
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VIRGL_FORMAT_I32_UINT = 218,
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VIRGL_FORMAT_L32_UINT = 219,
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VIRGL_FORMAT_L32A32_UINT = 220,
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VIRGL_FORMAT_A32_SINT = 221,
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VIRGL_FORMAT_I32_SINT = 222,
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VIRGL_FORMAT_L32_SINT = 223,
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VIRGL_FORMAT_L32A32_SINT = 224,
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VIRGL_FORMAT_B10G10R10A2_UINT = 225,
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VIRGL_FORMAT_ETC1_RGB8 = 226,
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VIRGL_FORMAT_R8G8_R8B8_UNORM = 227,
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VIRGL_FORMAT_G8R8_B8R8_UNORM = 228,
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VIRGL_FORMAT_R8G8B8X8_SNORM = 229,
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VIRGL_FORMAT_R8G8B8X8_SRGB = 230,
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VIRGL_FORMAT_R8G8B8X8_UINT = 231,
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VIRGL_FORMAT_R8G8B8X8_SINT = 232,
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VIRGL_FORMAT_B10G10R10X2_UNORM = 233,
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VIRGL_FORMAT_R16G16B16X16_UNORM = 234,
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VIRGL_FORMAT_R16G16B16X16_SNORM = 235,
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VIRGL_FORMAT_R16G16B16X16_FLOAT = 236,
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VIRGL_FORMAT_R16G16B16X16_UINT = 237,
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VIRGL_FORMAT_R16G16B16X16_SINT = 238,
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VIRGL_FORMAT_R32G32B32X32_FLOAT = 239,
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VIRGL_FORMAT_R32G32B32X32_UINT = 240,
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VIRGL_FORMAT_R32G32B32X32_SINT = 241,
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VIRGL_FORMAT_R8A8_SNORM = 242,
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VIRGL_FORMAT_R16A16_UNORM = 243,
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VIRGL_FORMAT_R16A16_SNORM = 244,
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VIRGL_FORMAT_R16A16_FLOAT = 245,
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VIRGL_FORMAT_R32A32_FLOAT = 246,
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VIRGL_FORMAT_R8A8_UINT = 247,
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VIRGL_FORMAT_R8A8_SINT = 248,
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VIRGL_FORMAT_R16A16_UINT = 249,
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VIRGL_FORMAT_R16A16_SINT = 250,
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VIRGL_FORMAT_R32A32_UINT = 251,
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VIRGL_FORMAT_R32A32_SINT = 252,
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VIRGL_FORMAT_R10G10B10A2_UINT = 253,
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VIRGL_FORMAT_B5G6R5_SRGB = 254,
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VIRGL_FORMAT_BPTC_RGBA_UNORM = 255,
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VIRGL_FORMAT_BPTC_SRGBA = 256,
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VIRGL_FORMAT_BPTC_RGB_FLOAT = 257,
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VIRGL_FORMAT_BPTC_RGB_UFLOAT = 258,
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VIRGL_FORMAT_A16L16_UNORM = 262,
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VIRGL_FORMAT_G8R8_UNORM = 263,
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VIRGL_FORMAT_G8R8_SNORM = 264,
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VIRGL_FORMAT_G16R16_UNORM = 265,
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VIRGL_FORMAT_G16R16_SNORM = 266,
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VIRGL_FORMAT_A8B8G8R8_SNORM = 267,
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VIRGL_FORMAT_A8L8_UNORM = 259,
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VIRGL_FORMAT_A8L8_SNORM = 260,
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VIRGL_FORMAT_A8L8_SRGB = 261,
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VIRGL_FORMAT_X8B8G8R8_SNORM = 268,
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/* etc2 compressed */
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VIRGL_FORMAT_ETC2_RGB8 = 269,
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VIRGL_FORMAT_ETC2_SRGB8 = 270,
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VIRGL_FORMAT_ETC2_RGB8A1 = 271,
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VIRGL_FORMAT_ETC2_SRGB8A1 = 272,
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VIRGL_FORMAT_ETC2_RGBA8 = 273,
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VIRGL_FORMAT_ETC2_SRGBA8 = 274,
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VIRGL_FORMAT_ETC2_R11_UNORM = 275,
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VIRGL_FORMAT_ETC2_R11_SNORM = 276,
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VIRGL_FORMAT_ETC2_RG11_UNORM = 277,
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VIRGL_FORMAT_ETC2_RG11_SNORM = 278,
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/* astc compressed */
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VIRGL_FORMAT_ASTC_4x4 = 279,
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VIRGL_FORMAT_ASTC_5x4 = 280,
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VIRGL_FORMAT_ASTC_5x5 = 281,
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VIRGL_FORMAT_ASTC_6x5 = 282,
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VIRGL_FORMAT_ASTC_6x6 = 283,
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VIRGL_FORMAT_ASTC_8x5 = 284,
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VIRGL_FORMAT_ASTC_8x6 = 285,
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VIRGL_FORMAT_ASTC_8x8 = 286,
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VIRGL_FORMAT_ASTC_10x5 = 287,
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VIRGL_FORMAT_ASTC_10x6 = 288,
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VIRGL_FORMAT_ASTC_10x8 = 289,
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VIRGL_FORMAT_ASTC_10x10 = 290,
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VIRGL_FORMAT_ASTC_12x10 = 291,
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VIRGL_FORMAT_ASTC_12x12 = 292,
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VIRGL_FORMAT_ASTC_4x4_SRGB = 293,
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VIRGL_FORMAT_ASTC_5x4_SRGB = 294,
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VIRGL_FORMAT_ASTC_5x5_SRGB = 295,
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VIRGL_FORMAT_ASTC_6x5_SRGB = 296,
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VIRGL_FORMAT_ASTC_6x6_SRGB = 297,
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VIRGL_FORMAT_ASTC_8x5_SRGB = 298,
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VIRGL_FORMAT_ASTC_8x6_SRGB = 299,
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VIRGL_FORMAT_ASTC_8x8_SRGB = 300,
384
VIRGL_FORMAT_ASTC_10x5_SRGB = 301,
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VIRGL_FORMAT_ASTC_10x6_SRGB = 302,
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VIRGL_FORMAT_ASTC_10x8_SRGB = 303,
387
VIRGL_FORMAT_ASTC_10x10_SRGB = 304,
388
VIRGL_FORMAT_ASTC_12x10_SRGB = 305,
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VIRGL_FORMAT_ASTC_12x12_SRGB = 306,
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VIRGL_FORMAT_R10G10B10X2_UNORM = 308,
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VIRGL_FORMAT_A4B4G4R4_UNORM = 311,
393
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VIRGL_FORMAT_R8_SRGB = 312,
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VIRGL_FORMAT_R8G8_SRGB = 313,
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VIRGL_FORMAT_MAX /* = PIPE_FORMAT_COUNT */,
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/* Below formats must not be used in the guest. */
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VIRGL_FORMAT_B8G8R8X8_UNORM_EMULATED,
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VIRGL_FORMAT_B8G8R8A8_UNORM_EMULATED,
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VIRGL_FORMAT_MAX_EXTENDED
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};
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/* These are used by the capability_bits field in virgl_caps_v2. */
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#define VIRGL_CAP_NONE 0
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#define VIRGL_CAP_TGSI_INVARIANT (1 << 0)
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#define VIRGL_CAP_TEXTURE_VIEW (1 << 1)
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#define VIRGL_CAP_SET_MIN_SAMPLES (1 << 2)
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#define VIRGL_CAP_COPY_IMAGE (1 << 3)
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#define VIRGL_CAP_TGSI_PRECISE (1 << 4)
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#define VIRGL_CAP_TXQS (1 << 5)
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#define VIRGL_CAP_MEMORY_BARRIER (1 << 6)
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#define VIRGL_CAP_COMPUTE_SHADER (1 << 7)
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#define VIRGL_CAP_FB_NO_ATTACH (1 << 8)
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#define VIRGL_CAP_ROBUST_BUFFER_ACCESS (1 << 9)
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#define VIRGL_CAP_TGSI_FBFETCH (1 << 10)
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#define VIRGL_CAP_SHADER_CLOCK (1 << 11)
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#define VIRGL_CAP_TEXTURE_BARRIER (1 << 12)
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#define VIRGL_CAP_TGSI_COMPONENTS (1 << 13)
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#define VIRGL_CAP_GUEST_MAY_INIT_LOG (1 << 14)
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#define VIRGL_CAP_SRGB_WRITE_CONTROL (1 << 15)
422
#define VIRGL_CAP_QBO (1 << 16)
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#define VIRGL_CAP_TRANSFER (1 << 17)
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#define VIRGL_CAP_FBO_MIXED_COLOR_FORMATS (1 << 18)
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#define VIRGL_CAP_FAKE_FP64 (1 << 19)
426
#define VIRGL_CAP_BIND_COMMAND_ARGS (1 << 20)
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#define VIRGL_CAP_MULTI_DRAW_INDIRECT (1 << 21)
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#define VIRGL_CAP_INDIRECT_PARAMS (1 << 22)
429
#define VIRGL_CAP_TRANSFORM_FEEDBACK3 (1 << 23)
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#define VIRGL_CAP_3D_ASTC (1 << 24)
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#define VIRGL_CAP_INDIRECT_INPUT_ADDR (1 << 25)
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#define VIRGL_CAP_COPY_TRANSFER (1 << 26)
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#define VIRGL_CAP_CLIP_HALFZ (1 << 27)
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#define VIRGL_CAP_APP_TWEAK_SUPPORT (1 << 28)
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#define VIRGL_CAP_BGRA_SRGB_IS_EMULATED (1 << 29)
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#define VIRGL_CAP_CLEAR_TEXTURE (1 << 30)
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#define VIRGL_CAP_ARB_BUFFER_STORAGE (1 << 31)
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/* These are used by the capability_bits_v2 field in virgl_caps_v2. */
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#define VIRGL_CAP_V2_BLEND_EQUATION (1 << 0)
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#define VIRGL_CAP_V2_UNTYPED_RESOURCE (1 << 1)
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#define VIRGL_CAP_V2_VIDEO_MEMORY (1 << 2)
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#define VIRGL_CAP_V2_MEMINFO (1 << 3)
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#define VIRGL_CAP_V2_STRING_MARKER (1 << 4)
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#define VIRGL_CAP_V2_IMPLICIT_MSAA (1 << 6)
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447
/* virgl bind flags - these are compatible with mesa 10.5 gallium.
448
* but are fixed, no other should be passed to virgl either.
449
*/
450
#define VIRGL_BIND_DEPTH_STENCIL (1 << 0)
451
#define VIRGL_BIND_RENDER_TARGET (1 << 1)
452
#define VIRGL_BIND_SAMPLER_VIEW (1 << 3)
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#define VIRGL_BIND_VERTEX_BUFFER (1 << 4)
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#define VIRGL_BIND_INDEX_BUFFER (1 << 5)
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#define VIRGL_BIND_CONSTANT_BUFFER (1 << 6)
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#define VIRGL_BIND_DISPLAY_TARGET (1 << 7)
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#define VIRGL_BIND_COMMAND_ARGS (1 << 8)
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#define VIRGL_BIND_STREAM_OUTPUT (1 << 11)
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#define VIRGL_BIND_SHADER_BUFFER (1 << 14)
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#define VIRGL_BIND_QUERY_BUFFER (1 << 15)
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#define VIRGL_BIND_CURSOR (1 << 16)
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#define VIRGL_BIND_CUSTOM (1 << 17)
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#define VIRGL_BIND_SCANOUT (1 << 18)
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/* Used for buffers that are backed by guest storage and
465
* are only read by the host.
466
*/
467
#define VIRGL_BIND_STAGING (1 << 19)
468
#define VIRGL_BIND_SHARED (1 << 20)
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470
#define VIRGL_BIND_PREFER_EMULATED_BGRA (1 << 21)
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472
#define VIRGL_BIND_LINEAR (1 << 22)
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474
#define VIRGL_BIND_SHARED_SUBFLAGS (0xff << 24)
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476
#define VIRGL_BIND_MINIGBM_CAMERA_WRITE (1 << 24)
477
#define VIRGL_BIND_MINIGBM_CAMERA_READ (1 << 25)
478
#define VIRGL_BIND_MINIGBM_HW_VIDEO_DECODER (1 << 26)
479
#define VIRGL_BIND_MINIGBM_HW_VIDEO_ENCODER (1 << 27)
480
#define VIRGL_BIND_MINIGBM_SW_READ_OFTEN (1 << 28)
481
#define VIRGL_BIND_MINIGBM_SW_READ_RARELY (1 << 29)
482
#define VIRGL_BIND_MINIGBM_SW_WRITE_OFTEN (1 << 30)
483
#define VIRGL_BIND_MINIGBM_SW_WRITE_RARELY (1 << 31)
484
#define VIRGL_BIND_MINIGBM_PROTECTED (0xf << 28) // Mutually exclusive with SW_ flags
485
486
struct virgl_caps_bool_set1 {
487
unsigned indep_blend_enable:1;
488
unsigned indep_blend_func:1;
489
unsigned cube_map_array:1;
490
unsigned shader_stencil_export:1;
491
unsigned conditional_render:1;
492
unsigned start_instance:1;
493
unsigned primitive_restart:1;
494
unsigned blend_eq_sep:1;
495
unsigned instanceid:1;
496
unsigned vertex_element_instance_divisor:1;
497
unsigned seamless_cube_map:1;
498
unsigned occlusion_query:1;
499
unsigned timer_query:1;
500
unsigned streamout_pause_resume:1;
501
unsigned texture_multisample:1;
502
unsigned fragment_coord_conventions:1;
503
unsigned depth_clip_disable:1;
504
unsigned seamless_cube_map_per_texture:1;
505
unsigned ubo:1;
506
unsigned color_clamping:1; /* not in GL 3.1 core profile */
507
unsigned poly_stipple:1; /* not in GL 3.1 core profile */
508
unsigned mirror_clamp:1;
509
unsigned texture_query_lod:1;
510
unsigned has_fp64:1;
511
unsigned has_tessellation_shaders:1;
512
unsigned has_indirect_draw:1;
513
unsigned has_sample_shading:1;
514
unsigned has_cull:1;
515
unsigned conditional_render_inverted:1;
516
unsigned derivative_control:1;
517
unsigned polygon_offset_clamp:1;
518
unsigned transform_feedback_overflow_query:1;
519
/* DO NOT ADD ANYMORE MEMBERS - need to add another 32-bit to v2 caps */
520
};
521
522
/* endless expansion capabilites - current gallium has 252 formats */
523
struct virgl_supported_format_mask {
524
uint32_t bitmask[16];
525
};
526
/* capabilities set 2 - version 1 - 32-bit and float values */
527
struct virgl_caps_v1 {
528
uint32_t max_version;
529
struct virgl_supported_format_mask sampler;
530
struct virgl_supported_format_mask render;
531
struct virgl_supported_format_mask depthstencil;
532
struct virgl_supported_format_mask vertexbuffer;
533
struct virgl_caps_bool_set1 bset;
534
uint32_t glsl_level;
535
uint32_t max_texture_array_layers;
536
uint32_t max_streamout_buffers;
537
uint32_t max_dual_source_render_targets;
538
uint32_t max_render_targets;
539
uint32_t max_samples;
540
uint32_t prim_mask;
541
uint32_t max_tbo_size;
542
uint32_t max_uniform_blocks;
543
uint32_t max_viewports;
544
uint32_t max_texture_gather_components;
545
};
546
547
/*
548
* This struct should be growable when used in capset 2,
549
* so we shouldn't have to add a v3 ever.
550
*/
551
struct virgl_caps_v2 {
552
struct virgl_caps_v1 v1;
553
float min_aliased_point_size;
554
float max_aliased_point_size;
555
float min_smooth_point_size;
556
float max_smooth_point_size;
557
float min_aliased_line_width;
558
float max_aliased_line_width;
559
float min_smooth_line_width;
560
float max_smooth_line_width;
561
float max_texture_lod_bias;
562
uint32_t max_geom_output_vertices;
563
uint32_t max_geom_total_output_components;
564
uint32_t max_vertex_outputs;
565
uint32_t max_vertex_attribs;
566
uint32_t max_shader_patch_varyings;
567
int32_t min_texel_offset;
568
int32_t max_texel_offset;
569
int32_t min_texture_gather_offset;
570
int32_t max_texture_gather_offset;
571
uint32_t texture_buffer_offset_alignment;
572
uint32_t uniform_buffer_offset_alignment;
573
uint32_t shader_buffer_offset_alignment;
574
uint32_t capability_bits;
575
uint32_t sample_locations[8];
576
uint32_t max_vertex_attrib_stride;
577
uint32_t max_shader_buffer_frag_compute;
578
uint32_t max_shader_buffer_other_stages;
579
uint32_t max_shader_image_frag_compute;
580
uint32_t max_shader_image_other_stages;
581
uint32_t max_image_samples;
582
uint32_t max_compute_work_group_invocations;
583
uint32_t max_compute_shared_memory_size;
584
uint32_t max_compute_grid_size[3];
585
uint32_t max_compute_block_size[3];
586
uint32_t max_texture_2d_size;
587
uint32_t max_texture_3d_size;
588
uint32_t max_texture_cube_size;
589
uint32_t max_combined_shader_buffers;
590
uint32_t max_atomic_counters[6];
591
uint32_t max_atomic_counter_buffers[6];
592
uint32_t max_combined_atomic_counters;
593
uint32_t max_combined_atomic_counter_buffers;
594
uint32_t host_feature_check_version;
595
struct virgl_supported_format_mask supported_readback_formats;
596
struct virgl_supported_format_mask scanout;
597
uint32_t capability_bits_v2;
598
uint32_t max_video_memory;
599
char renderer[64];
600
};
601
602
union virgl_caps {
603
uint32_t max_version;
604
struct virgl_caps_v1 v1;
605
struct virgl_caps_v2 v2;
606
};
607
608
enum virgl_errors {
609
VIRGL_ERROR_NONE,
610
VIRGL_ERROR_UNKNOWN,
611
VIRGL_ERROR_UNKNOWN_RESOURCE_FORMAT,
612
};
613
614
enum virgl_ctx_errors {
615
VIRGL_ERROR_CTX_NONE,
616
VIRGL_ERROR_CTX_UNKNOWN,
617
VIRGL_ERROR_CTX_ILLEGAL_SHADER,
618
VIRGL_ERROR_CTX_ILLEGAL_HANDLE,
619
VIRGL_ERROR_CTX_ILLEGAL_RESOURCE,
620
VIRGL_ERROR_CTX_ILLEGAL_SURFACE,
621
VIRGL_ERROR_CTX_ILLEGAL_VERTEX_FORMAT,
622
VIRGL_ERROR_CTX_ILLEGAL_CMD_BUFFER,
623
VIRGL_ERROR_CTX_GLES_HAVE_TES_BUT_MISS_TCS,
624
VIRGL_ERROR_GL_ANY_SAMPLES_PASSED,
625
VIRGL_ERROR_CTX_ILLEGAL_FORMAT,
626
VIRGL_ERROR_CTX_ILLEGAL_SAMPLER_VIEW_TARGET,
627
VIRGL_ERROR_CTX_TRANSFER_IOV_BOUNDS,
628
VIRGL_ERROR_CTX_ILLEGAL_DUAL_SRC_BLEND
629
};
630
631
/**
632
* Flags for the driver about resource behaviour:
633
*/
634
#define VIRGL_RESOURCE_Y_0_TOP (1 << 0)
635
#define VIRGL_RESOURCE_FLAG_MAP_PERSISTENT (1 << 1)
636
#define VIRGL_RESOURCE_FLAG_MAP_COHERENT (1 << 2)
637
638
#endif
639
640