Path: blob/21.2-virgl/src/virtio/virtio-gpu/virgl_hw.h
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/*1* Copyright 2014, 2015 Red Hat.2*3* Permission is hereby granted, free of charge, to any person obtaining a4* copy of this software and associated documentation files (the "Software"),5* to deal in the Software without restriction, including without limitation6* on the rights to use, copy, modify, merge, publish, distribute, sub7* license, and/or sell copies of the Software, and to permit persons to whom8* the Software is furnished to do so, subject to the following conditions:9*10* The above copyright notice and this permission notice (including the next11* paragraph) shall be included in all copies or substantial portions of the12* Software.13*14* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL17* THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,18* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR19* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE20* USE OR OTHER DEALINGS IN THE SOFTWARE.21*/22#ifndef VIRGL_HW_H23#define VIRGL_HW_H2425#include <stdint.h>2627struct virgl_box {28uint32_t x, y, z;29uint32_t w, h, d;30};3132/* formats known by the HW device - based on gallium subset */33enum virgl_formats {34VIRGL_FORMAT_NONE = 0,35VIRGL_FORMAT_B8G8R8A8_UNORM = 1,36VIRGL_FORMAT_B8G8R8X8_UNORM = 2,37VIRGL_FORMAT_A8R8G8B8_UNORM = 3,38VIRGL_FORMAT_X8R8G8B8_UNORM = 4,39VIRGL_FORMAT_B5G5R5A1_UNORM = 5,40VIRGL_FORMAT_B4G4R4A4_UNORM = 6,41VIRGL_FORMAT_B5G6R5_UNORM = 7,42VIRGL_FORMAT_R10G10B10A2_UNORM = 8,43VIRGL_FORMAT_L8_UNORM = 9, /**< ubyte luminance */44VIRGL_FORMAT_A8_UNORM = 10, /**< ubyte alpha */45VIRGL_FORMAT_I8_UNORM = 11,46VIRGL_FORMAT_L8A8_UNORM = 12, /**< ubyte alpha, luminance */47VIRGL_FORMAT_L16_UNORM = 13, /**< ushort luminance */48VIRGL_FORMAT_UYVY = 14,49VIRGL_FORMAT_YUYV = 15,50VIRGL_FORMAT_Z16_UNORM = 16,51VIRGL_FORMAT_Z32_UNORM = 17,52VIRGL_FORMAT_Z32_FLOAT = 18,53VIRGL_FORMAT_Z24_UNORM_S8_UINT = 19,54VIRGL_FORMAT_S8_UINT_Z24_UNORM = 20,55VIRGL_FORMAT_Z24X8_UNORM = 21,56VIRGL_FORMAT_X8Z24_UNORM = 22,57VIRGL_FORMAT_S8_UINT = 23, /**< ubyte stencil */58VIRGL_FORMAT_R64_FLOAT = 24,59VIRGL_FORMAT_R64G64_FLOAT = 25,60VIRGL_FORMAT_R64G64B64_FLOAT = 26,61VIRGL_FORMAT_R64G64B64A64_FLOAT = 27,62VIRGL_FORMAT_R32_FLOAT = 28,63VIRGL_FORMAT_R32G32_FLOAT = 29,64VIRGL_FORMAT_R32G32B32_FLOAT = 30,65VIRGL_FORMAT_R32G32B32A32_FLOAT = 31,6667VIRGL_FORMAT_R32_UNORM = 32,68VIRGL_FORMAT_R32G32_UNORM = 33,69VIRGL_FORMAT_R32G32B32_UNORM = 34,70VIRGL_FORMAT_R32G32B32A32_UNORM = 35,71VIRGL_FORMAT_R32_USCALED = 36,72VIRGL_FORMAT_R32G32_USCALED = 37,73VIRGL_FORMAT_R32G32B32_USCALED = 38,74VIRGL_FORMAT_R32G32B32A32_USCALED = 39,75VIRGL_FORMAT_R32_SNORM = 40,76VIRGL_FORMAT_R32G32_SNORM = 41,77VIRGL_FORMAT_R32G32B32_SNORM = 42,78VIRGL_FORMAT_R32G32B32A32_SNORM = 43,79VIRGL_FORMAT_R32_SSCALED = 44,80VIRGL_FORMAT_R32G32_SSCALED = 45,81VIRGL_FORMAT_R32G32B32_SSCALED = 46,82VIRGL_FORMAT_R32G32B32A32_SSCALED = 47,8384VIRGL_FORMAT_R16_UNORM = 48,85VIRGL_FORMAT_R16G16_UNORM = 49,86VIRGL_FORMAT_R16G16B16_UNORM = 50,87VIRGL_FORMAT_R16G16B16A16_UNORM = 51,8889VIRGL_FORMAT_R16_USCALED = 52,90VIRGL_FORMAT_R16G16_USCALED = 53,91VIRGL_FORMAT_R16G16B16_USCALED = 54,92VIRGL_FORMAT_R16G16B16A16_USCALED = 55,9394VIRGL_FORMAT_R16_SNORM = 56,95VIRGL_FORMAT_R16G16_SNORM = 57,96VIRGL_FORMAT_R16G16B16_SNORM = 58,97VIRGL_FORMAT_R16G16B16A16_SNORM = 59,9899VIRGL_FORMAT_R16_SSCALED = 60,100VIRGL_FORMAT_R16G16_SSCALED = 61,101VIRGL_FORMAT_R16G16B16_SSCALED = 62,102VIRGL_FORMAT_R16G16B16A16_SSCALED = 63,103104VIRGL_FORMAT_R8_UNORM = 64,105VIRGL_FORMAT_R8G8_UNORM = 65,106VIRGL_FORMAT_R8G8B8_UNORM = 66,107VIRGL_FORMAT_R8G8B8A8_UNORM = 67,108VIRGL_FORMAT_X8B8G8R8_UNORM = 68,109110VIRGL_FORMAT_R8_USCALED = 69,111VIRGL_FORMAT_R8G8_USCALED = 70,112VIRGL_FORMAT_R8G8B8_USCALED = 71,113VIRGL_FORMAT_R8G8B8A8_USCALED = 72,114115VIRGL_FORMAT_R8_SNORM = 74,116VIRGL_FORMAT_R8G8_SNORM = 75,117VIRGL_FORMAT_R8G8B8_SNORM = 76,118VIRGL_FORMAT_R8G8B8A8_SNORM = 77,119120VIRGL_FORMAT_R8_SSCALED = 82,121VIRGL_FORMAT_R8G8_SSCALED = 83,122VIRGL_FORMAT_R8G8B8_SSCALED = 84,123VIRGL_FORMAT_R8G8B8A8_SSCALED = 85,124125VIRGL_FORMAT_R32_FIXED = 87,126VIRGL_FORMAT_R32G32_FIXED = 88,127VIRGL_FORMAT_R32G32B32_FIXED = 89,128VIRGL_FORMAT_R32G32B32A32_FIXED = 90,129130VIRGL_FORMAT_R16_FLOAT = 91,131VIRGL_FORMAT_R16G16_FLOAT = 92,132VIRGL_FORMAT_R16G16B16_FLOAT = 93,133VIRGL_FORMAT_R16G16B16A16_FLOAT = 94,134135VIRGL_FORMAT_L8_SRGB = 95,136VIRGL_FORMAT_L8A8_SRGB = 96,137VIRGL_FORMAT_R8G8B8_SRGB = 97,138VIRGL_FORMAT_A8B8G8R8_SRGB = 98,139VIRGL_FORMAT_X8B8G8R8_SRGB = 99,140VIRGL_FORMAT_B8G8R8A8_SRGB = 100,141VIRGL_FORMAT_B8G8R8X8_SRGB = 101,142VIRGL_FORMAT_A8R8G8B8_SRGB = 102,143VIRGL_FORMAT_X8R8G8B8_SRGB = 103,144VIRGL_FORMAT_R8G8B8A8_SRGB = 104,145146/* compressed formats */147VIRGL_FORMAT_DXT1_RGB = 105,148VIRGL_FORMAT_DXT1_RGBA = 106,149VIRGL_FORMAT_DXT3_RGBA = 107,150VIRGL_FORMAT_DXT5_RGBA = 108,151152/* sRGB, compressed */153VIRGL_FORMAT_DXT1_SRGB = 109,154VIRGL_FORMAT_DXT1_SRGBA = 110,155VIRGL_FORMAT_DXT3_SRGBA = 111,156VIRGL_FORMAT_DXT5_SRGBA = 112,157158/* rgtc compressed */159VIRGL_FORMAT_RGTC1_UNORM = 113,160VIRGL_FORMAT_RGTC1_SNORM = 114,161VIRGL_FORMAT_RGTC2_UNORM = 115,162VIRGL_FORMAT_RGTC2_SNORM = 116,163164VIRGL_FORMAT_R8G8_B8G8_UNORM = 117,165VIRGL_FORMAT_G8R8_G8B8_UNORM = 118,166167VIRGL_FORMAT_R8SG8SB8UX8U_NORM = 119,168VIRGL_FORMAT_R5SG5SB6U_NORM = 120,169170VIRGL_FORMAT_A8B8G8R8_UNORM = 121,171VIRGL_FORMAT_B5G5R5X1_UNORM = 122,172VIRGL_FORMAT_R10G10B10A2_USCALED = 123,173VIRGL_FORMAT_R11G11B10_FLOAT = 124,174VIRGL_FORMAT_R9G9B9E5_FLOAT = 125,175VIRGL_FORMAT_Z32_FLOAT_S8X24_UINT = 126,176VIRGL_FORMAT_R1_UNORM = 127,177VIRGL_FORMAT_R10G10B10X2_USCALED = 128,178VIRGL_FORMAT_R10G10B10X2_SNORM = 129,179180VIRGL_FORMAT_L4A4_UNORM = 130,181VIRGL_FORMAT_B10G10R10A2_UNORM = 131,182VIRGL_FORMAT_R10SG10SB10SA2U_NORM = 132,183VIRGL_FORMAT_R8G8Bx_SNORM = 133,184VIRGL_FORMAT_R8G8B8X8_UNORM = 134,185VIRGL_FORMAT_B4G4R4X4_UNORM = 135,186VIRGL_FORMAT_X24S8_UINT = 136,187VIRGL_FORMAT_S8X24_UINT = 137,188VIRGL_FORMAT_X32_S8X24_UINT = 138,189VIRGL_FORMAT_B2G3R3_UNORM = 139,190191VIRGL_FORMAT_L16A16_UNORM = 140,192VIRGL_FORMAT_A16_UNORM = 141,193VIRGL_FORMAT_I16_UNORM = 142,194195VIRGL_FORMAT_LATC1_UNORM = 143,196VIRGL_FORMAT_LATC1_SNORM = 144,197VIRGL_FORMAT_LATC2_UNORM = 145,198VIRGL_FORMAT_LATC2_SNORM = 146,199200VIRGL_FORMAT_A8_SNORM = 147,201VIRGL_FORMAT_L8_SNORM = 148,202VIRGL_FORMAT_L8A8_SNORM = 149,203VIRGL_FORMAT_I8_SNORM = 150,204VIRGL_FORMAT_A16_SNORM = 151,205VIRGL_FORMAT_L16_SNORM = 152,206VIRGL_FORMAT_L16A16_SNORM = 153,207VIRGL_FORMAT_I16_SNORM = 154,208209VIRGL_FORMAT_A16_FLOAT = 155,210VIRGL_FORMAT_L16_FLOAT = 156,211VIRGL_FORMAT_L16A16_FLOAT = 157,212VIRGL_FORMAT_I16_FLOAT = 158,213VIRGL_FORMAT_A32_FLOAT = 159,214VIRGL_FORMAT_L32_FLOAT = 160,215VIRGL_FORMAT_L32A32_FLOAT = 161,216VIRGL_FORMAT_I32_FLOAT = 162,217218VIRGL_FORMAT_YV12 = 163,219VIRGL_FORMAT_YV16 = 164,220VIRGL_FORMAT_IYUV = 165, /**< aka I420 */221VIRGL_FORMAT_NV12 = 166,222VIRGL_FORMAT_NV21 = 167,223224VIRGL_FORMAT_A4R4_UNORM = 168,225VIRGL_FORMAT_R4A4_UNORM = 169,226VIRGL_FORMAT_R8A8_UNORM = 170,227VIRGL_FORMAT_A8R8_UNORM = 171,228229VIRGL_FORMAT_R10G10B10A2_SSCALED = 172,230VIRGL_FORMAT_R10G10B10A2_SNORM = 173,231VIRGL_FORMAT_B10G10R10A2_USCALED = 174,232VIRGL_FORMAT_B10G10R10A2_SSCALED = 175,233VIRGL_FORMAT_B10G10R10A2_SNORM = 176,234235VIRGL_FORMAT_R8_UINT = 177,236VIRGL_FORMAT_R8G8_UINT = 178,237VIRGL_FORMAT_R8G8B8_UINT = 179,238VIRGL_FORMAT_R8G8B8A8_UINT = 180,239240VIRGL_FORMAT_R8_SINT = 181,241VIRGL_FORMAT_R8G8_SINT = 182,242VIRGL_FORMAT_R8G8B8_SINT = 183,243VIRGL_FORMAT_R8G8B8A8_SINT = 184,244245VIRGL_FORMAT_R16_UINT = 185,246VIRGL_FORMAT_R16G16_UINT = 186,247VIRGL_FORMAT_R16G16B16_UINT = 187,248VIRGL_FORMAT_R16G16B16A16_UINT = 188,249250VIRGL_FORMAT_R16_SINT = 189,251VIRGL_FORMAT_R16G16_SINT = 190,252VIRGL_FORMAT_R16G16B16_SINT = 191,253VIRGL_FORMAT_R16G16B16A16_SINT = 192,254VIRGL_FORMAT_R32_UINT = 193,255VIRGL_FORMAT_R32G32_UINT = 194,256VIRGL_FORMAT_R32G32B32_UINT = 195,257VIRGL_FORMAT_R32G32B32A32_UINT = 196,258259VIRGL_FORMAT_R32_SINT = 197,260VIRGL_FORMAT_R32G32_SINT = 198,261VIRGL_FORMAT_R32G32B32_SINT = 199,262VIRGL_FORMAT_R32G32B32A32_SINT = 200,263264VIRGL_FORMAT_A8_UINT = 201,265VIRGL_FORMAT_I8_UINT = 202,266VIRGL_FORMAT_L8_UINT = 203,267VIRGL_FORMAT_L8A8_UINT = 204,268269VIRGL_FORMAT_A8_SINT = 205,270VIRGL_FORMAT_I8_SINT = 206,271VIRGL_FORMAT_L8_SINT = 207,272VIRGL_FORMAT_L8A8_SINT = 208,273274VIRGL_FORMAT_A16_UINT = 209,275VIRGL_FORMAT_I16_UINT = 210,276VIRGL_FORMAT_L16_UINT = 211,277VIRGL_FORMAT_L16A16_UINT = 212,278279VIRGL_FORMAT_A16_SINT = 213,280VIRGL_FORMAT_I16_SINT = 214,281VIRGL_FORMAT_L16_SINT = 215,282VIRGL_FORMAT_L16A16_SINT = 216,283284VIRGL_FORMAT_A32_UINT = 217,285VIRGL_FORMAT_I32_UINT = 218,286VIRGL_FORMAT_L32_UINT = 219,287VIRGL_FORMAT_L32A32_UINT = 220,288289VIRGL_FORMAT_A32_SINT = 221,290VIRGL_FORMAT_I32_SINT = 222,291VIRGL_FORMAT_L32_SINT = 223,292VIRGL_FORMAT_L32A32_SINT = 224,293294VIRGL_FORMAT_B10G10R10A2_UINT = 225,295VIRGL_FORMAT_ETC1_RGB8 = 226,296VIRGL_FORMAT_R8G8_R8B8_UNORM = 227,297VIRGL_FORMAT_G8R8_B8R8_UNORM = 228,298VIRGL_FORMAT_R8G8B8X8_SNORM = 229,299300VIRGL_FORMAT_R8G8B8X8_SRGB = 230,301302VIRGL_FORMAT_R8G8B8X8_UINT = 231,303VIRGL_FORMAT_R8G8B8X8_SINT = 232,304VIRGL_FORMAT_B10G10R10X2_UNORM = 233,305VIRGL_FORMAT_R16G16B16X16_UNORM = 234,306VIRGL_FORMAT_R16G16B16X16_SNORM = 235,307VIRGL_FORMAT_R16G16B16X16_FLOAT = 236,308VIRGL_FORMAT_R16G16B16X16_UINT = 237,309VIRGL_FORMAT_R16G16B16X16_SINT = 238,310VIRGL_FORMAT_R32G32B32X32_FLOAT = 239,311VIRGL_FORMAT_R32G32B32X32_UINT = 240,312VIRGL_FORMAT_R32G32B32X32_SINT = 241,313VIRGL_FORMAT_R8A8_SNORM = 242,314VIRGL_FORMAT_R16A16_UNORM = 243,315VIRGL_FORMAT_R16A16_SNORM = 244,316VIRGL_FORMAT_R16A16_FLOAT = 245,317VIRGL_FORMAT_R32A32_FLOAT = 246,318VIRGL_FORMAT_R8A8_UINT = 247,319VIRGL_FORMAT_R8A8_SINT = 248,320VIRGL_FORMAT_R16A16_UINT = 249,321VIRGL_FORMAT_R16A16_SINT = 250,322VIRGL_FORMAT_R32A32_UINT = 251,323VIRGL_FORMAT_R32A32_SINT = 252,324325VIRGL_FORMAT_R10G10B10A2_UINT = 253,326VIRGL_FORMAT_B5G6R5_SRGB = 254,327328VIRGL_FORMAT_BPTC_RGBA_UNORM = 255,329VIRGL_FORMAT_BPTC_SRGBA = 256,330VIRGL_FORMAT_BPTC_RGB_FLOAT = 257,331VIRGL_FORMAT_BPTC_RGB_UFLOAT = 258,332333VIRGL_FORMAT_A16L16_UNORM = 262,334335VIRGL_FORMAT_G8R8_UNORM = 263,336VIRGL_FORMAT_G8R8_SNORM = 264,337VIRGL_FORMAT_G16R16_UNORM = 265,338VIRGL_FORMAT_G16R16_SNORM = 266,339VIRGL_FORMAT_A8B8G8R8_SNORM = 267,340341VIRGL_FORMAT_A8L8_UNORM = 259,342VIRGL_FORMAT_A8L8_SNORM = 260,343VIRGL_FORMAT_A8L8_SRGB = 261,344345VIRGL_FORMAT_X8B8G8R8_SNORM = 268,346347348/* etc2 compressed */349VIRGL_FORMAT_ETC2_RGB8 = 269,350VIRGL_FORMAT_ETC2_SRGB8 = 270,351VIRGL_FORMAT_ETC2_RGB8A1 = 271,352VIRGL_FORMAT_ETC2_SRGB8A1 = 272,353VIRGL_FORMAT_ETC2_RGBA8 = 273,354VIRGL_FORMAT_ETC2_SRGBA8 = 274,355VIRGL_FORMAT_ETC2_R11_UNORM = 275,356VIRGL_FORMAT_ETC2_R11_SNORM = 276,357VIRGL_FORMAT_ETC2_RG11_UNORM = 277,358VIRGL_FORMAT_ETC2_RG11_SNORM = 278,359360/* astc compressed */361VIRGL_FORMAT_ASTC_4x4 = 279,362VIRGL_FORMAT_ASTC_5x4 = 280,363VIRGL_FORMAT_ASTC_5x5 = 281,364VIRGL_FORMAT_ASTC_6x5 = 282,365VIRGL_FORMAT_ASTC_6x6 = 283,366VIRGL_FORMAT_ASTC_8x5 = 284,367VIRGL_FORMAT_ASTC_8x6 = 285,368VIRGL_FORMAT_ASTC_8x8 = 286,369VIRGL_FORMAT_ASTC_10x5 = 287,370VIRGL_FORMAT_ASTC_10x6 = 288,371VIRGL_FORMAT_ASTC_10x8 = 289,372VIRGL_FORMAT_ASTC_10x10 = 290,373VIRGL_FORMAT_ASTC_12x10 = 291,374VIRGL_FORMAT_ASTC_12x12 = 292,375VIRGL_FORMAT_ASTC_4x4_SRGB = 293,376VIRGL_FORMAT_ASTC_5x4_SRGB = 294,377VIRGL_FORMAT_ASTC_5x5_SRGB = 295,378VIRGL_FORMAT_ASTC_6x5_SRGB = 296,379VIRGL_FORMAT_ASTC_6x6_SRGB = 297,380VIRGL_FORMAT_ASTC_8x5_SRGB = 298,381VIRGL_FORMAT_ASTC_8x6_SRGB = 299,382VIRGL_FORMAT_ASTC_8x8_SRGB = 300,383VIRGL_FORMAT_ASTC_10x5_SRGB = 301,384VIRGL_FORMAT_ASTC_10x6_SRGB = 302,385VIRGL_FORMAT_ASTC_10x8_SRGB = 303,386VIRGL_FORMAT_ASTC_10x10_SRGB = 304,387VIRGL_FORMAT_ASTC_12x10_SRGB = 305,388VIRGL_FORMAT_ASTC_12x12_SRGB = 306,389390VIRGL_FORMAT_R10G10B10X2_UNORM = 308,391VIRGL_FORMAT_A4B4G4R4_UNORM = 311,392393VIRGL_FORMAT_R8_SRGB = 312,394VIRGL_FORMAT_R8G8_SRGB = 313,395VIRGL_FORMAT_MAX /* = PIPE_FORMAT_COUNT */,396397/* Below formats must not be used in the guest. */398VIRGL_FORMAT_B8G8R8X8_UNORM_EMULATED,399VIRGL_FORMAT_B8G8R8A8_UNORM_EMULATED,400VIRGL_FORMAT_MAX_EXTENDED401};402403/* These are used by the capability_bits field in virgl_caps_v2. */404#define VIRGL_CAP_NONE 0405#define VIRGL_CAP_TGSI_INVARIANT (1 << 0)406#define VIRGL_CAP_TEXTURE_VIEW (1 << 1)407#define VIRGL_CAP_SET_MIN_SAMPLES (1 << 2)408#define VIRGL_CAP_COPY_IMAGE (1 << 3)409#define VIRGL_CAP_TGSI_PRECISE (1 << 4)410#define VIRGL_CAP_TXQS (1 << 5)411#define VIRGL_CAP_MEMORY_BARRIER (1 << 6)412#define VIRGL_CAP_COMPUTE_SHADER (1 << 7)413#define VIRGL_CAP_FB_NO_ATTACH (1 << 8)414#define VIRGL_CAP_ROBUST_BUFFER_ACCESS (1 << 9)415#define VIRGL_CAP_TGSI_FBFETCH (1 << 10)416#define VIRGL_CAP_SHADER_CLOCK (1 << 11)417#define VIRGL_CAP_TEXTURE_BARRIER (1 << 12)418#define VIRGL_CAP_TGSI_COMPONENTS (1 << 13)419#define VIRGL_CAP_GUEST_MAY_INIT_LOG (1 << 14)420#define VIRGL_CAP_SRGB_WRITE_CONTROL (1 << 15)421#define VIRGL_CAP_QBO (1 << 16)422#define VIRGL_CAP_TRANSFER (1 << 17)423#define VIRGL_CAP_FBO_MIXED_COLOR_FORMATS (1 << 18)424#define VIRGL_CAP_FAKE_FP64 (1 << 19)425#define VIRGL_CAP_BIND_COMMAND_ARGS (1 << 20)426#define VIRGL_CAP_MULTI_DRAW_INDIRECT (1 << 21)427#define VIRGL_CAP_INDIRECT_PARAMS (1 << 22)428#define VIRGL_CAP_TRANSFORM_FEEDBACK3 (1 << 23)429#define VIRGL_CAP_3D_ASTC (1 << 24)430#define VIRGL_CAP_INDIRECT_INPUT_ADDR (1 << 25)431#define VIRGL_CAP_COPY_TRANSFER (1 << 26)432#define VIRGL_CAP_CLIP_HALFZ (1 << 27)433#define VIRGL_CAP_APP_TWEAK_SUPPORT (1 << 28)434#define VIRGL_CAP_BGRA_SRGB_IS_EMULATED (1 << 29)435#define VIRGL_CAP_CLEAR_TEXTURE (1 << 30)436#define VIRGL_CAP_ARB_BUFFER_STORAGE (1 << 31)437438/* These are used by the capability_bits_v2 field in virgl_caps_v2. */439#define VIRGL_CAP_V2_BLEND_EQUATION (1 << 0)440#define VIRGL_CAP_V2_UNTYPED_RESOURCE (1 << 1)441#define VIRGL_CAP_V2_VIDEO_MEMORY (1 << 2)442#define VIRGL_CAP_V2_MEMINFO (1 << 3)443#define VIRGL_CAP_V2_STRING_MARKER (1 << 4)444#define VIRGL_CAP_V2_IMPLICIT_MSAA (1 << 6)445446/* virgl bind flags - these are compatible with mesa 10.5 gallium.447* but are fixed, no other should be passed to virgl either.448*/449#define VIRGL_BIND_DEPTH_STENCIL (1 << 0)450#define VIRGL_BIND_RENDER_TARGET (1 << 1)451#define VIRGL_BIND_SAMPLER_VIEW (1 << 3)452#define VIRGL_BIND_VERTEX_BUFFER (1 << 4)453#define VIRGL_BIND_INDEX_BUFFER (1 << 5)454#define VIRGL_BIND_CONSTANT_BUFFER (1 << 6)455#define VIRGL_BIND_DISPLAY_TARGET (1 << 7)456#define VIRGL_BIND_COMMAND_ARGS (1 << 8)457#define VIRGL_BIND_STREAM_OUTPUT (1 << 11)458#define VIRGL_BIND_SHADER_BUFFER (1 << 14)459#define VIRGL_BIND_QUERY_BUFFER (1 << 15)460#define VIRGL_BIND_CURSOR (1 << 16)461#define VIRGL_BIND_CUSTOM (1 << 17)462#define VIRGL_BIND_SCANOUT (1 << 18)463/* Used for buffers that are backed by guest storage and464* are only read by the host.465*/466#define VIRGL_BIND_STAGING (1 << 19)467#define VIRGL_BIND_SHARED (1 << 20)468469#define VIRGL_BIND_PREFER_EMULATED_BGRA (1 << 21)470471#define VIRGL_BIND_LINEAR (1 << 22)472473#define VIRGL_BIND_SHARED_SUBFLAGS (0xff << 24)474475#define VIRGL_BIND_MINIGBM_CAMERA_WRITE (1 << 24)476#define VIRGL_BIND_MINIGBM_CAMERA_READ (1 << 25)477#define VIRGL_BIND_MINIGBM_HW_VIDEO_DECODER (1 << 26)478#define VIRGL_BIND_MINIGBM_HW_VIDEO_ENCODER (1 << 27)479#define VIRGL_BIND_MINIGBM_SW_READ_OFTEN (1 << 28)480#define VIRGL_BIND_MINIGBM_SW_READ_RARELY (1 << 29)481#define VIRGL_BIND_MINIGBM_SW_WRITE_OFTEN (1 << 30)482#define VIRGL_BIND_MINIGBM_SW_WRITE_RARELY (1 << 31)483#define VIRGL_BIND_MINIGBM_PROTECTED (0xf << 28) // Mutually exclusive with SW_ flags484485struct virgl_caps_bool_set1 {486unsigned indep_blend_enable:1;487unsigned indep_blend_func:1;488unsigned cube_map_array:1;489unsigned shader_stencil_export:1;490unsigned conditional_render:1;491unsigned start_instance:1;492unsigned primitive_restart:1;493unsigned blend_eq_sep:1;494unsigned instanceid:1;495unsigned vertex_element_instance_divisor:1;496unsigned seamless_cube_map:1;497unsigned occlusion_query:1;498unsigned timer_query:1;499unsigned streamout_pause_resume:1;500unsigned texture_multisample:1;501unsigned fragment_coord_conventions:1;502unsigned depth_clip_disable:1;503unsigned seamless_cube_map_per_texture:1;504unsigned ubo:1;505unsigned color_clamping:1; /* not in GL 3.1 core profile */506unsigned poly_stipple:1; /* not in GL 3.1 core profile */507unsigned mirror_clamp:1;508unsigned texture_query_lod:1;509unsigned has_fp64:1;510unsigned has_tessellation_shaders:1;511unsigned has_indirect_draw:1;512unsigned has_sample_shading:1;513unsigned has_cull:1;514unsigned conditional_render_inverted:1;515unsigned derivative_control:1;516unsigned polygon_offset_clamp:1;517unsigned transform_feedback_overflow_query:1;518/* DO NOT ADD ANYMORE MEMBERS - need to add another 32-bit to v2 caps */519};520521/* endless expansion capabilites - current gallium has 252 formats */522struct virgl_supported_format_mask {523uint32_t bitmask[16];524};525/* capabilities set 2 - version 1 - 32-bit and float values */526struct virgl_caps_v1 {527uint32_t max_version;528struct virgl_supported_format_mask sampler;529struct virgl_supported_format_mask render;530struct virgl_supported_format_mask depthstencil;531struct virgl_supported_format_mask vertexbuffer;532struct virgl_caps_bool_set1 bset;533uint32_t glsl_level;534uint32_t max_texture_array_layers;535uint32_t max_streamout_buffers;536uint32_t max_dual_source_render_targets;537uint32_t max_render_targets;538uint32_t max_samples;539uint32_t prim_mask;540uint32_t max_tbo_size;541uint32_t max_uniform_blocks;542uint32_t max_viewports;543uint32_t max_texture_gather_components;544};545546/*547* This struct should be growable when used in capset 2,548* so we shouldn't have to add a v3 ever.549*/550struct virgl_caps_v2 {551struct virgl_caps_v1 v1;552float min_aliased_point_size;553float max_aliased_point_size;554float min_smooth_point_size;555float max_smooth_point_size;556float min_aliased_line_width;557float max_aliased_line_width;558float min_smooth_line_width;559float max_smooth_line_width;560float max_texture_lod_bias;561uint32_t max_geom_output_vertices;562uint32_t max_geom_total_output_components;563uint32_t max_vertex_outputs;564uint32_t max_vertex_attribs;565uint32_t max_shader_patch_varyings;566int32_t min_texel_offset;567int32_t max_texel_offset;568int32_t min_texture_gather_offset;569int32_t max_texture_gather_offset;570uint32_t texture_buffer_offset_alignment;571uint32_t uniform_buffer_offset_alignment;572uint32_t shader_buffer_offset_alignment;573uint32_t capability_bits;574uint32_t sample_locations[8];575uint32_t max_vertex_attrib_stride;576uint32_t max_shader_buffer_frag_compute;577uint32_t max_shader_buffer_other_stages;578uint32_t max_shader_image_frag_compute;579uint32_t max_shader_image_other_stages;580uint32_t max_image_samples;581uint32_t max_compute_work_group_invocations;582uint32_t max_compute_shared_memory_size;583uint32_t max_compute_grid_size[3];584uint32_t max_compute_block_size[3];585uint32_t max_texture_2d_size;586uint32_t max_texture_3d_size;587uint32_t max_texture_cube_size;588uint32_t max_combined_shader_buffers;589uint32_t max_atomic_counters[6];590uint32_t max_atomic_counter_buffers[6];591uint32_t max_combined_atomic_counters;592uint32_t max_combined_atomic_counter_buffers;593uint32_t host_feature_check_version;594struct virgl_supported_format_mask supported_readback_formats;595struct virgl_supported_format_mask scanout;596uint32_t capability_bits_v2;597uint32_t max_video_memory;598char renderer[64];599};600601union virgl_caps {602uint32_t max_version;603struct virgl_caps_v1 v1;604struct virgl_caps_v2 v2;605};606607enum virgl_errors {608VIRGL_ERROR_NONE,609VIRGL_ERROR_UNKNOWN,610VIRGL_ERROR_UNKNOWN_RESOURCE_FORMAT,611};612613enum virgl_ctx_errors {614VIRGL_ERROR_CTX_NONE,615VIRGL_ERROR_CTX_UNKNOWN,616VIRGL_ERROR_CTX_ILLEGAL_SHADER,617VIRGL_ERROR_CTX_ILLEGAL_HANDLE,618VIRGL_ERROR_CTX_ILLEGAL_RESOURCE,619VIRGL_ERROR_CTX_ILLEGAL_SURFACE,620VIRGL_ERROR_CTX_ILLEGAL_VERTEX_FORMAT,621VIRGL_ERROR_CTX_ILLEGAL_CMD_BUFFER,622VIRGL_ERROR_CTX_GLES_HAVE_TES_BUT_MISS_TCS,623VIRGL_ERROR_GL_ANY_SAMPLES_PASSED,624VIRGL_ERROR_CTX_ILLEGAL_FORMAT,625VIRGL_ERROR_CTX_ILLEGAL_SAMPLER_VIEW_TARGET,626VIRGL_ERROR_CTX_TRANSFER_IOV_BOUNDS,627VIRGL_ERROR_CTX_ILLEGAL_DUAL_SRC_BLEND628};629630/**631* Flags for the driver about resource behaviour:632*/633#define VIRGL_RESOURCE_Y_0_TOP (1 << 0)634#define VIRGL_RESOURCE_FLAG_MAP_PERSISTENT (1 << 1)635#define VIRGL_RESOURCE_FLAG_MAP_COHERENT (1 << 2)636637#endif638639640