Path: blob/21.2-virgl/src/virtio/virtio-gpu/virgl_protocol.h
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/*1* Copyright 2014, 2015 Red Hat.2*3* Permission is hereby granted, free of charge, to any person obtaining a4* copy of this software and associated documentation files (the "Software"),5* to deal in the Software without restriction, including without limitation6* on the rights to use, copy, modify, merge, publish, distribute, sub7* license, and/or sell copies of the Software, and to permit persons to whom8* the Software is furnished to do so, subject to the following conditions:9*10* The above copyright notice and this permission notice (including the next11* paragraph) shall be included in all copies or substantial portions of the12* Software.13*14* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL17* THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,18* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR19* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE20* USE OR OTHER DEALINGS IN THE SOFTWARE.21*/22#ifndef VIRGL_PROTOCOL_H23#define VIRGL_PROTOCOL_H2425#include <stdint.h>2627#define VIRGL_QUERY_STATE_NEW 028#define VIRGL_QUERY_STATE_DONE 129#define VIRGL_QUERY_STATE_WAIT_HOST 23031struct virgl_host_query_state {32uint32_t query_state;33uint32_t result_size;34uint64_t result;35};3637struct virgl_memory_info38{39uint32_t total_device_memory; /**< size of device memory, e.g. VRAM */40uint32_t avail_device_memory; /**< free device memory at the moment */41uint32_t total_staging_memory; /**< size of staging memory, e.g. GART */42uint32_t avail_staging_memory; /**< free staging memory at the moment */43uint32_t device_memory_evicted; /**< size of memory evicted (monotonic counter) */44uint32_t nr_device_memory_evictions; /**< # of evictions (monotonic counter) */45};4647enum virgl_object_type {48VIRGL_OBJECT_NULL,49VIRGL_OBJECT_BLEND,50VIRGL_OBJECT_RASTERIZER,51VIRGL_OBJECT_DSA,52VIRGL_OBJECT_SHADER,53VIRGL_OBJECT_VERTEX_ELEMENTS,54VIRGL_OBJECT_SAMPLER_VIEW,55VIRGL_OBJECT_SAMPLER_STATE,56VIRGL_OBJECT_SURFACE,57VIRGL_OBJECT_QUERY,58VIRGL_OBJECT_STREAMOUT_TARGET,59VIRGL_OBJECT_MSAA_SURFACE,60VIRGL_MAX_OBJECTS,61};6263/* context cmds to be encoded in the command stream */64enum virgl_context_cmd {65VIRGL_CCMD_NOP = 0,66VIRGL_CCMD_CREATE_OBJECT = 1,67VIRGL_CCMD_BIND_OBJECT,68VIRGL_CCMD_DESTROY_OBJECT,69VIRGL_CCMD_SET_VIEWPORT_STATE,70VIRGL_CCMD_SET_FRAMEBUFFER_STATE,71VIRGL_CCMD_SET_VERTEX_BUFFERS,72VIRGL_CCMD_CLEAR,73VIRGL_CCMD_DRAW_VBO,74VIRGL_CCMD_RESOURCE_INLINE_WRITE,75VIRGL_CCMD_SET_SAMPLER_VIEWS,76VIRGL_CCMD_SET_INDEX_BUFFER,77VIRGL_CCMD_SET_CONSTANT_BUFFER,78VIRGL_CCMD_SET_STENCIL_REF,79VIRGL_CCMD_SET_BLEND_COLOR,80VIRGL_CCMD_SET_SCISSOR_STATE,81VIRGL_CCMD_BLIT,82VIRGL_CCMD_RESOURCE_COPY_REGION,83VIRGL_CCMD_BIND_SAMPLER_STATES,84VIRGL_CCMD_BEGIN_QUERY,85VIRGL_CCMD_END_QUERY,86VIRGL_CCMD_GET_QUERY_RESULT,87VIRGL_CCMD_SET_POLYGON_STIPPLE,88VIRGL_CCMD_SET_CLIP_STATE,89VIRGL_CCMD_SET_SAMPLE_MASK,90VIRGL_CCMD_SET_STREAMOUT_TARGETS,91VIRGL_CCMD_SET_RENDER_CONDITION,92VIRGL_CCMD_SET_UNIFORM_BUFFER,9394VIRGL_CCMD_SET_SUB_CTX,95VIRGL_CCMD_CREATE_SUB_CTX,96VIRGL_CCMD_DESTROY_SUB_CTX,97VIRGL_CCMD_BIND_SHADER,98VIRGL_CCMD_SET_TESS_STATE,99VIRGL_CCMD_SET_MIN_SAMPLES,100VIRGL_CCMD_SET_SHADER_BUFFERS,101VIRGL_CCMD_SET_SHADER_IMAGES,102VIRGL_CCMD_MEMORY_BARRIER,103VIRGL_CCMD_LAUNCH_GRID,104VIRGL_CCMD_SET_FRAMEBUFFER_STATE_NO_ATTACH,105VIRGL_CCMD_TEXTURE_BARRIER,106VIRGL_CCMD_SET_ATOMIC_BUFFERS,107VIRGL_CCMD_SET_DEBUG_FLAGS,108VIRGL_CCMD_GET_QUERY_RESULT_QBO,109VIRGL_CCMD_TRANSFER3D,110VIRGL_CCMD_END_TRANSFERS,111VIRGL_CCMD_COPY_TRANSFER3D,112VIRGL_CCMD_SET_TWEAKS,113VIRGL_CCMD_CLEAR_TEXTURE,114VIRGL_CCMD_PIPE_RESOURCE_CREATE,115VIRGL_CCMD_PIPE_RESOURCE_SET_TYPE,116VIRGL_CCMD_GET_MEMORY_INFO,117VIRGL_CCMD_EMIT_STRING_MARKER,118VIRGL_MAX_COMMANDS119};120121/*1228-bit cmd headers1238-bit object type12416-bit length125*/126127#define VIRGL_CMD0(cmd, obj, len) ((cmd) | ((obj) << 8) | ((len) << 16))128#define VIRGL_CMD0_MAX_DWORDS (((1ULL << 16) - 1) / 4) * 4129130/* hw specification */131#define VIRGL_MAX_COLOR_BUFS 8132#define VIRGL_MAX_CLIP_PLANES 8133134#define VIRGL_OBJ_CREATE_HEADER 0135#define VIRGL_OBJ_CREATE_HANDLE 1136137#define VIRGL_OBJ_BIND_HEADER 0138#define VIRGL_OBJ_BIND_HANDLE 1139140#define VIRGL_OBJ_DESTROY_HANDLE 1141142/* some of these defines are a specification - not used in the code */143/* bit offsets for blend state object */144#define VIRGL_OBJ_BLEND_SIZE (VIRGL_MAX_COLOR_BUFS + 3)145#define VIRGL_OBJ_BLEND_HANDLE 1146#define VIRGL_OBJ_BLEND_S0 2147#define VIRGL_OBJ_BLEND_S0_INDEPENDENT_BLEND_ENABLE(x) ((x) & 0x1 << 0)148#define VIRGL_OBJ_BLEND_S0_LOGICOP_ENABLE(x) (((x) & 0x1) << 1)149#define VIRGL_OBJ_BLEND_S0_DITHER(x) (((x) & 0x1) << 2)150#define VIRGL_OBJ_BLEND_S0_ALPHA_TO_COVERAGE(x) (((x) & 0x1) << 3)151#define VIRGL_OBJ_BLEND_S0_ALPHA_TO_ONE(x) (((x) & 0x1) << 4)152#define VIRGL_OBJ_BLEND_S1 3153#define VIRGL_OBJ_BLEND_S1_LOGICOP_FUNC(x) (((x) & 0xf) << 0)154/* repeated once per number of cbufs */155156#define VIRGL_OBJ_BLEND_S2(cbuf) (4 + (cbuf))157#define VIRGL_OBJ_BLEND_S2_RT_BLEND_ENABLE(x) (((x) & 0x1) << 0)158#define VIRGL_OBJ_BLEND_S2_RT_RGB_FUNC(x) (((x) & 0x7) << 1)159#define VIRGL_OBJ_BLEND_S2_RT_RGB_SRC_FACTOR(x) (((x) & 0x1f) << 4)160#define VIRGL_OBJ_BLEND_S2_RT_RGB_DST_FACTOR(x) (((x) & 0x1f) << 9)161#define VIRGL_OBJ_BLEND_S2_RT_ALPHA_FUNC(x) (((x) & 0x7) << 14)162#define VIRGL_OBJ_BLEND_S2_RT_ALPHA_SRC_FACTOR(x) (((x) & 0x1f) << 17)163#define VIRGL_OBJ_BLEND_S2_RT_ALPHA_DST_FACTOR(x) (((x) & 0x1f) << 22)164#define VIRGL_OBJ_BLEND_S2_RT_COLORMASK(x) (((x) & 0xf) << 27)165166/* bit offsets for DSA state */167#define VIRGL_OBJ_DSA_SIZE 5168#define VIRGL_OBJ_DSA_HANDLE 1169#define VIRGL_OBJ_DSA_S0 2170#define VIRGL_OBJ_DSA_S0_DEPTH_ENABLE(x) (((x) & 0x1) << 0)171#define VIRGL_OBJ_DSA_S0_DEPTH_WRITEMASK(x) (((x) & 0x1) << 1)172#define VIRGL_OBJ_DSA_S0_DEPTH_FUNC(x) (((x) & 0x7) << 2)173#define VIRGL_OBJ_DSA_S0_ALPHA_ENABLED(x) (((x) & 0x1) << 8)174#define VIRGL_OBJ_DSA_S0_ALPHA_FUNC(x) (((x) & 0x7) << 9)175#define VIRGL_OBJ_DSA_S1 3176#define VIRGL_OBJ_DSA_S2 4177#define VIRGL_OBJ_DSA_S1_STENCIL_ENABLED(x) (((x) & 0x1) << 0)178#define VIRGL_OBJ_DSA_S1_STENCIL_FUNC(x) (((x) & 0x7) << 1)179#define VIRGL_OBJ_DSA_S1_STENCIL_FAIL_OP(x) (((x) & 0x7) << 4)180#define VIRGL_OBJ_DSA_S1_STENCIL_ZPASS_OP(x) (((x) & 0x7) << 7)181#define VIRGL_OBJ_DSA_S1_STENCIL_ZFAIL_OP(x) (((x) & 0x7) << 10)182#define VIRGL_OBJ_DSA_S1_STENCIL_VALUEMASK(x) (((x) & 0xff) << 13)183#define VIRGL_OBJ_DSA_S1_STENCIL_WRITEMASK(x) (((x) & 0xff) << 21)184#define VIRGL_OBJ_DSA_ALPHA_REF 5185186/* offsets for rasterizer state */187#define VIRGL_OBJ_RS_SIZE 9188#define VIRGL_OBJ_RS_HANDLE 1189#define VIRGL_OBJ_RS_S0 2190#define VIRGL_OBJ_RS_S0_FLATSHADE(x) (((x) & 0x1) << 0)191#define VIRGL_OBJ_RS_S0_DEPTH_CLIP(x) (((x) & 0x1) << 1)192#define VIRGL_OBJ_RS_S0_CLIP_HALFZ(x) (((x) & 0x1) << 2)193#define VIRGL_OBJ_RS_S0_RASTERIZER_DISCARD(x) (((x) & 0x1) << 3)194#define VIRGL_OBJ_RS_S0_FLATSHADE_FIRST(x) (((x) & 0x1) << 4)195#define VIRGL_OBJ_RS_S0_LIGHT_TWOSIZE(x) (((x) & 0x1) << 5)196#define VIRGL_OBJ_RS_S0_SPRITE_COORD_MODE(x) (((x) & 0x1) << 6)197#define VIRGL_OBJ_RS_S0_POINT_QUAD_RASTERIZATION(x) (((x) & 0x1) << 7)198#define VIRGL_OBJ_RS_S0_CULL_FACE(x) (((x) & 0x3) << 8)199#define VIRGL_OBJ_RS_S0_FILL_FRONT(x) (((x) & 0x3) << 10)200#define VIRGL_OBJ_RS_S0_FILL_BACK(x) (((x) & 0x3) << 12)201#define VIRGL_OBJ_RS_S0_SCISSOR(x) (((x) & 0x1) << 14)202#define VIRGL_OBJ_RS_S0_FRONT_CCW(x) (((x) & 0x1) << 15)203#define VIRGL_OBJ_RS_S0_CLAMP_VERTEX_COLOR(x) (((x) & 0x1) << 16)204#define VIRGL_OBJ_RS_S0_CLAMP_FRAGMENT_COLOR(x) (((x) & 0x1) << 17)205#define VIRGL_OBJ_RS_S0_OFFSET_LINE(x) (((x) & 0x1) << 18)206#define VIRGL_OBJ_RS_S0_OFFSET_POINT(x) (((x) & 0x1) << 19)207#define VIRGL_OBJ_RS_S0_OFFSET_TRI(x) (((x) & 0x1) << 20)208#define VIRGL_OBJ_RS_S0_POLY_SMOOTH(x) (((x) & 0x1) << 21)209#define VIRGL_OBJ_RS_S0_POLY_STIPPLE_ENABLE(x) (((x) & 0x1) << 22)210#define VIRGL_OBJ_RS_S0_POINT_SMOOTH(x) (((x) & 0x1) << 23)211#define VIRGL_OBJ_RS_S0_POINT_SIZE_PER_VERTEX(x) (((x) & 0x1) << 24)212#define VIRGL_OBJ_RS_S0_MULTISAMPLE(x) (((x) & 0x1) << 25)213#define VIRGL_OBJ_RS_S0_LINE_SMOOTH(x) (((x) & 0x1) << 26)214#define VIRGL_OBJ_RS_S0_LINE_STIPPLE_ENABLE(x) (((x) & 0x1) << 27)215#define VIRGL_OBJ_RS_S0_LINE_LAST_PIXEL(x) (((x) & 0x1) << 28)216#define VIRGL_OBJ_RS_S0_HALF_PIXEL_CENTER(x) (((x) & 0x1) << 29)217#define VIRGL_OBJ_RS_S0_BOTTOM_EDGE_RULE(x) (((x) & 0x1) << 30)218#define VIRGL_OBJ_RS_S0_FORCE_PERSAMPLE_INTERP(x) (((x) & 0x1) << 31)219220#define VIRGL_OBJ_RS_POINT_SIZE 3221#define VIRGL_OBJ_RS_SPRITE_COORD_ENABLE 4222#define VIRGL_OBJ_RS_S3 5223224#define VIRGL_OBJ_RS_S3_LINE_STIPPLE_PATTERN(x) (((x) & 0xffff) << 0)225#define VIRGL_OBJ_RS_S3_LINE_STIPPLE_FACTOR(x) (((x) & 0xff) << 16)226#define VIRGL_OBJ_RS_S3_CLIP_PLANE_ENABLE(x) (((x) & 0xff) << 24)227#define VIRGL_OBJ_RS_LINE_WIDTH 6228#define VIRGL_OBJ_RS_OFFSET_UNITS 7229#define VIRGL_OBJ_RS_OFFSET_SCALE 8230#define VIRGL_OBJ_RS_OFFSET_CLAMP 9231232#define VIRGL_OBJ_CLEAR_SIZE 8233#define VIRGL_OBJ_CLEAR_BUFFERS 1234#define VIRGL_OBJ_CLEAR_COLOR_0 2 /* color is 4 * u32/f32/i32 */235#define VIRGL_OBJ_CLEAR_COLOR_1 3236#define VIRGL_OBJ_CLEAR_COLOR_2 4237#define VIRGL_OBJ_CLEAR_COLOR_3 5238#define VIRGL_OBJ_CLEAR_DEPTH_0 6 /* depth is a double precision float */239#define VIRGL_OBJ_CLEAR_DEPTH_1 7240#define VIRGL_OBJ_CLEAR_STENCIL 8241242/* shader object */243#define VIRGL_OBJ_SHADER_HDR_SIZE(nso) (5 + ((nso) ? (2 * nso) + 4 : 0))244#define VIRGL_OBJ_SHADER_HANDLE 1245#define VIRGL_OBJ_SHADER_TYPE 2246#define VIRGL_OBJ_SHADER_OFFSET 3247#define VIRGL_OBJ_SHADER_OFFSET_VAL(x) (((x) & 0x7fffffff) << 0)248/* start contains full length in VAL - also implies continuations */249/* continuation contains offset in VAL */250#define VIRGL_OBJ_SHADER_OFFSET_CONT (0x1u << 31)251#define VIRGL_OBJ_SHADER_NUM_TOKENS 4252#define VIRGL_OBJ_SHADER_SO_NUM_OUTPUTS 5253#define VIRGL_OBJ_SHADER_SO_STRIDE(x) (6 + (x))254#define VIRGL_OBJ_SHADER_SO_OUTPUT0(x) (10 + (x * 2))255#define VIRGL_OBJ_SHADER_SO_OUTPUT_REGISTER_INDEX(x) (((x) & 0xff) << 0)256#define VIRGL_OBJ_SHADER_SO_OUTPUT_START_COMPONENT(x) (((x) & 0x3) << 8)257#define VIRGL_OBJ_SHADER_SO_OUTPUT_NUM_COMPONENTS(x) (((x) & 0x7) << 10)258#define VIRGL_OBJ_SHADER_SO_OUTPUT_BUFFER(x) (((x) & 0x7) << 13)259#define VIRGL_OBJ_SHADER_SO_OUTPUT_DST_OFFSET(x) (((x) & 0xffff) << 16)260#define VIRGL_OBJ_SHADER_SO_OUTPUT0_SO(x) (11 + (x * 2))261#define VIRGL_OBJ_SHADER_SO_OUTPUT_STREAM(x) (((x) & 0x03) << 0)262263/* viewport state */264#define VIRGL_SET_VIEWPORT_STATE_SIZE(num_viewports) ((6 * num_viewports) + 1)265#define VIRGL_SET_VIEWPORT_START_SLOT 1266#define VIRGL_SET_VIEWPORT_STATE_SCALE_0(x) (2 + (x * 6))267#define VIRGL_SET_VIEWPORT_STATE_SCALE_1(x) (3 + (x * 6))268#define VIRGL_SET_VIEWPORT_STATE_SCALE_2(x) (4 + (x * 6))269#define VIRGL_SET_VIEWPORT_STATE_TRANSLATE_0(x) (5 + (x * 6))270#define VIRGL_SET_VIEWPORT_STATE_TRANSLATE_1(x) (6 + (x * 6))271#define VIRGL_SET_VIEWPORT_STATE_TRANSLATE_2(x) (7 + (x * 6))272273/* framebuffer state */274#define VIRGL_SET_FRAMEBUFFER_STATE_SIZE(nr_cbufs) (nr_cbufs + 2)275#define VIRGL_SET_FRAMEBUFFER_STATE_NR_CBUFS 1276#define VIRGL_SET_FRAMEBUFFER_STATE_NR_ZSURF_HANDLE 2277#define VIRGL_SET_FRAMEBUFFER_STATE_CBUF_HANDLE(x) ((x) + 3)278279/* vertex elements object */280#define VIRGL_OBJ_VERTEX_ELEMENTS_SIZE(num_elements) (((num_elements) * 4) + 1)281#define VIRGL_OBJ_VERTEX_ELEMENTS_HANDLE 1282#define VIRGL_OBJ_VERTEX_ELEMENTS_V0_SRC_OFFSET(x) (((x) * 4) + 2) /* repeated per VE */283#define VIRGL_OBJ_VERTEX_ELEMENTS_V0_INSTANCE_DIVISOR(x) (((x) * 4) + 3)284#define VIRGL_OBJ_VERTEX_ELEMENTS_V0_VERTEX_BUFFER_INDEX(x) (((x) * 4) + 4)285#define VIRGL_OBJ_VERTEX_ELEMENTS_V0_SRC_FORMAT(x) (((x) * 4) + 5)286287/* vertex buffers */288#define VIRGL_SET_VERTEX_BUFFERS_SIZE(num_buffers) ((num_buffers) * 3)289#define VIRGL_SET_VERTEX_BUFFER_STRIDE(x) (((x) * 3) + 1)290#define VIRGL_SET_VERTEX_BUFFER_OFFSET(x) (((x) * 3) + 2)291#define VIRGL_SET_VERTEX_BUFFER_HANDLE(x) (((x) * 3) + 3)292293/* index buffer */294#define VIRGL_SET_INDEX_BUFFER_SIZE(ib) (((ib) ? 2 : 0) + 1)295#define VIRGL_SET_INDEX_BUFFER_HANDLE 1296#define VIRGL_SET_INDEX_BUFFER_INDEX_SIZE 2 /* only if sending an IB handle */297#define VIRGL_SET_INDEX_BUFFER_OFFSET 3 /* only if sending an IB handle */298299/* constant buffer */300#define VIRGL_SET_CONSTANT_BUFFER_SHADER_TYPE 1301#define VIRGL_SET_CONSTANT_BUFFER_INDEX 2302#define VIRGL_SET_CONSTANT_BUFFER_DATA_START 3303304#define VIRGL_SET_UNIFORM_BUFFER_SIZE 5305#define VIRGL_SET_UNIFORM_BUFFER_SHADER_TYPE 1306#define VIRGL_SET_UNIFORM_BUFFER_INDEX 2307#define VIRGL_SET_UNIFORM_BUFFER_OFFSET 3308#define VIRGL_SET_UNIFORM_BUFFER_LENGTH 4309#define VIRGL_SET_UNIFORM_BUFFER_RES_HANDLE 5310311/* draw VBO */312#define VIRGL_DRAW_VBO_SIZE 12313#define VIRGL_DRAW_VBO_SIZE_TESS 14314#define VIRGL_DRAW_VBO_SIZE_INDIRECT 20315#define VIRGL_DRAW_VBO_START 1316#define VIRGL_DRAW_VBO_COUNT 2317#define VIRGL_DRAW_VBO_MODE 3318#define VIRGL_DRAW_VBO_INDEXED 4319#define VIRGL_DRAW_VBO_INSTANCE_COUNT 5320#define VIRGL_DRAW_VBO_INDEX_BIAS 6321#define VIRGL_DRAW_VBO_START_INSTANCE 7322#define VIRGL_DRAW_VBO_PRIMITIVE_RESTART 8323#define VIRGL_DRAW_VBO_RESTART_INDEX 9324#define VIRGL_DRAW_VBO_MIN_INDEX 10325#define VIRGL_DRAW_VBO_MAX_INDEX 11326#define VIRGL_DRAW_VBO_COUNT_FROM_SO 12327/* tess packet */328#define VIRGL_DRAW_VBO_VERTICES_PER_PATCH 13329#define VIRGL_DRAW_VBO_DRAWID 14330/* indirect packet */331#define VIRGL_DRAW_VBO_INDIRECT_HANDLE 15332#define VIRGL_DRAW_VBO_INDIRECT_OFFSET 16333#define VIRGL_DRAW_VBO_INDIRECT_STRIDE 17334#define VIRGL_DRAW_VBO_INDIRECT_DRAW_COUNT 18335#define VIRGL_DRAW_VBO_INDIRECT_DRAW_COUNT_OFFSET 19336#define VIRGL_DRAW_VBO_INDIRECT_DRAW_COUNT_HANDLE 20337338/* create surface */339#define VIRGL_OBJ_SURFACE_SIZE 5340#define VIRGL_OBJ_SURFACE_HANDLE 1341#define VIRGL_OBJ_SURFACE_RES_HANDLE 2342#define VIRGL_OBJ_SURFACE_FORMAT 3343#define VIRGL_OBJ_SURFACE_BUFFER_FIRST_ELEMENT 4344#define VIRGL_OBJ_SURFACE_BUFFER_LAST_ELEMENT 5345#define VIRGL_OBJ_SURFACE_TEXTURE_LEVEL 4346#define VIRGL_OBJ_SURFACE_TEXTURE_LAYERS 5347348/* create surface with implicit MSAA support (for EXT_multisample_render_to_texture) */349#define VIRGL_OBJ_MSAA_SURFACE_SIZE (VIRGL_OBJ_SURFACE_SIZE + 1)350#define VIRGL_OBJ_SURFACE_SAMPLE_COUNT 6351352/* create streamout target */353#define VIRGL_OBJ_STREAMOUT_SIZE 4354#define VIRGL_OBJ_STREAMOUT_HANDLE 1355#define VIRGL_OBJ_STREAMOUT_RES_HANDLE 2356#define VIRGL_OBJ_STREAMOUT_BUFFER_OFFSET 3357#define VIRGL_OBJ_STREAMOUT_BUFFER_SIZE 4358359/* sampler state */360#define VIRGL_OBJ_SAMPLER_STATE_SIZE 9361#define VIRGL_OBJ_SAMPLER_STATE_HANDLE 1362#define VIRGL_OBJ_SAMPLER_STATE_S0 2363#define VIRGL_OBJ_SAMPLE_STATE_S0_WRAP_S(x) (((x) & 0x7) << 0)364#define VIRGL_OBJ_SAMPLE_STATE_S0_WRAP_T(x) (((x) & 0x7) << 3)365#define VIRGL_OBJ_SAMPLE_STATE_S0_WRAP_R(x) (((x) & 0x7) << 6)366#define VIRGL_OBJ_SAMPLE_STATE_S0_MIN_IMG_FILTER(x) (((x) & 0x3) << 9)367#define VIRGL_OBJ_SAMPLE_STATE_S0_MIN_MIP_FILTER(x) (((x) & 0x3) << 11)368#define VIRGL_OBJ_SAMPLE_STATE_S0_MAG_IMG_FILTER(x) (((x) & 0x3) << 13)369#define VIRGL_OBJ_SAMPLE_STATE_S0_COMPARE_MODE(x) (((x) & 0x1) << 15)370#define VIRGL_OBJ_SAMPLE_STATE_S0_COMPARE_FUNC(x) (((x) & 0x7) << 16)371#define VIRGL_OBJ_SAMPLE_STATE_S0_SEAMLESS_CUBE_MAP(x) (((x) & 0x1) << 19)372373#define VIRGL_OBJ_SAMPLER_STATE_LOD_BIAS 3374#define VIRGL_OBJ_SAMPLER_STATE_MIN_LOD 4375#define VIRGL_OBJ_SAMPLER_STATE_MAX_LOD 5376#define VIRGL_OBJ_SAMPLER_STATE_BORDER_COLOR(x) ((x) + 6) /* 6 - 9 */377378379/* sampler view */380#define VIRGL_OBJ_SAMPLER_VIEW_SIZE 6381#define VIRGL_OBJ_SAMPLER_VIEW_HANDLE 1382#define VIRGL_OBJ_SAMPLER_VIEW_RES_HANDLE 2383#define VIRGL_OBJ_SAMPLER_VIEW_FORMAT 3384#define VIRGL_OBJ_SAMPLER_VIEW_BUFFER_FIRST_ELEMENT 4385#define VIRGL_OBJ_SAMPLER_VIEW_BUFFER_LAST_ELEMENT 5386#define VIRGL_OBJ_SAMPLER_VIEW_TEXTURE_LAYER 4387#define VIRGL_OBJ_SAMPLER_VIEW_TEXTURE_LEVEL 5388#define VIRGL_OBJ_SAMPLER_VIEW_SWIZZLE 6389#define VIRGL_OBJ_SAMPLER_VIEW_SWIZZLE_R(x) (((x) & 0x7) << 0)390#define VIRGL_OBJ_SAMPLER_VIEW_SWIZZLE_G(x) (((x) & 0x7) << 3)391#define VIRGL_OBJ_SAMPLER_VIEW_SWIZZLE_B(x) (((x) & 0x7) << 6)392#define VIRGL_OBJ_SAMPLER_VIEW_SWIZZLE_A(x) (((x) & 0x7) << 9)393394/* set sampler views */395#define VIRGL_SET_SAMPLER_VIEWS_SIZE(num_views) ((num_views) + 2)396#define VIRGL_SET_SAMPLER_VIEWS_SHADER_TYPE 1397#define VIRGL_SET_SAMPLER_VIEWS_START_SLOT 2398#define VIRGL_SET_SAMPLER_VIEWS_V0_HANDLE 3399400/* bind sampler states */401#define VIRGL_BIND_SAMPLER_STATES(num_states) ((num_states) + 2)402#define VIRGL_BIND_SAMPLER_STATES_SHADER_TYPE 1403#define VIRGL_BIND_SAMPLER_STATES_START_SLOT 2404#define VIRGL_BIND_SAMPLER_STATES_S0_HANDLE 3405406/* set stencil reference */407#define VIRGL_SET_STENCIL_REF_SIZE 1408#define VIRGL_SET_STENCIL_REF 1409#define VIRGL_STENCIL_REF_VAL(f, s) ((f & 0xff) | (((s & 0xff) << 8)))410411/* set blend color */412#define VIRGL_SET_BLEND_COLOR_SIZE 4413#define VIRGL_SET_BLEND_COLOR(x) ((x) + 1)414415/* set scissor state */416#define VIRGL_SET_SCISSOR_STATE_SIZE(x) (1 + 2 * x)417#define VIRGL_SET_SCISSOR_START_SLOT 1418#define VIRGL_SET_SCISSOR_MINX_MINY(x) (2 + (x * 2))419#define VIRGL_SET_SCISSOR_MAXX_MAXY(x) (3 + (x * 2))420421/* resource copy region */422#define VIRGL_CMD_RESOURCE_COPY_REGION_SIZE 13423#define VIRGL_CMD_RCR_DST_RES_HANDLE 1424#define VIRGL_CMD_RCR_DST_LEVEL 2425#define VIRGL_CMD_RCR_DST_X 3426#define VIRGL_CMD_RCR_DST_Y 4427#define VIRGL_CMD_RCR_DST_Z 5428#define VIRGL_CMD_RCR_SRC_RES_HANDLE 6429#define VIRGL_CMD_RCR_SRC_LEVEL 7430#define VIRGL_CMD_RCR_SRC_X 8431#define VIRGL_CMD_RCR_SRC_Y 9432#define VIRGL_CMD_RCR_SRC_Z 10433#define VIRGL_CMD_RCR_SRC_W 11434#define VIRGL_CMD_RCR_SRC_H 12435#define VIRGL_CMD_RCR_SRC_D 13436437/* blit */438#define VIRGL_CMD_BLIT_SIZE 21439#define VIRGL_CMD_BLIT_S0 1440#define VIRGL_CMD_BLIT_S0_MASK(x) (((x) & 0xff) << 0)441#define VIRGL_CMD_BLIT_S0_FILTER(x) (((x) & 0x3) << 8)442#define VIRGL_CMD_BLIT_S0_SCISSOR_ENABLE(x) (((x) & 0x1) << 10)443#define VIRGL_CMD_BLIT_S0_RENDER_CONDITION_ENABLE(x) (((x) & 0x1) << 11)444#define VIRGL_CMD_BLIT_S0_ALPHA_BLEND(x) (((x) & 0x1) << 12)445#define VIRGL_CMD_BLIT_SCISSOR_MINX_MINY 2446#define VIRGL_CMD_BLIT_SCISSOR_MAXX_MAXY 3447#define VIRGL_CMD_BLIT_DST_RES_HANDLE 4448#define VIRGL_CMD_BLIT_DST_LEVEL 5449#define VIRGL_CMD_BLIT_DST_FORMAT 6450#define VIRGL_CMD_BLIT_DST_X 7451#define VIRGL_CMD_BLIT_DST_Y 8452#define VIRGL_CMD_BLIT_DST_Z 9453#define VIRGL_CMD_BLIT_DST_W 10454#define VIRGL_CMD_BLIT_DST_H 11455#define VIRGL_CMD_BLIT_DST_D 12456#define VIRGL_CMD_BLIT_SRC_RES_HANDLE 13457#define VIRGL_CMD_BLIT_SRC_LEVEL 14458#define VIRGL_CMD_BLIT_SRC_FORMAT 15459#define VIRGL_CMD_BLIT_SRC_X 16460#define VIRGL_CMD_BLIT_SRC_Y 17461#define VIRGL_CMD_BLIT_SRC_Z 18462#define VIRGL_CMD_BLIT_SRC_W 19463#define VIRGL_CMD_BLIT_SRC_H 20464#define VIRGL_CMD_BLIT_SRC_D 21465466/* query object */467#define VIRGL_OBJ_QUERY_SIZE 4468#define VIRGL_OBJ_QUERY_HANDLE 1469#define VIRGL_OBJ_QUERY_TYPE_INDEX 2470#define VIRGL_OBJ_QUERY_TYPE(x) (x & 0xffff)471#define VIRGL_OBJ_QUERY_INDEX(x) ((x & 0xffff) << 16)472#define VIRGL_OBJ_QUERY_OFFSET 3473#define VIRGL_OBJ_QUERY_RES_HANDLE 4474475#define VIRGL_QUERY_BEGIN_HANDLE 1476477#define VIRGL_QUERY_END_HANDLE 1478479#define VIRGL_QUERY_RESULT_SIZE 2480#define VIRGL_QUERY_RESULT_HANDLE 1481#define VIRGL_QUERY_RESULT_WAIT 2482483/* render condition */484#define VIRGL_RENDER_CONDITION_SIZE 3485#define VIRGL_RENDER_CONDITION_HANDLE 1486#define VIRGL_RENDER_CONDITION_CONDITION 2487#define VIRGL_RENDER_CONDITION_MODE 3488489/* resource inline write */490#define VIRGL_RESOURCE_IW_RES_HANDLE 1491#define VIRGL_RESOURCE_IW_LEVEL 2492#define VIRGL_RESOURCE_IW_USAGE 3493#define VIRGL_RESOURCE_IW_STRIDE 4494#define VIRGL_RESOURCE_IW_LAYER_STRIDE 5495#define VIRGL_RESOURCE_IW_X 6496#define VIRGL_RESOURCE_IW_Y 7497#define VIRGL_RESOURCE_IW_Z 8498#define VIRGL_RESOURCE_IW_W 9499#define VIRGL_RESOURCE_IW_H 10500#define VIRGL_RESOURCE_IW_D 11501#define VIRGL_RESOURCE_IW_DATA_START 12502503/* set streamout targets */504#define VIRGL_SET_STREAMOUT_TARGETS_APPEND_BITMASK 1505#define VIRGL_SET_STREAMOUT_TARGETS_H0 2506507/* set sample mask */508#define VIRGL_SET_SAMPLE_MASK_SIZE 1509#define VIRGL_SET_SAMPLE_MASK_MASK 1510511/* set clip state */512#define VIRGL_SET_CLIP_STATE_SIZE 32513#define VIRGL_SET_CLIP_STATE_C0 1514515/* polygon stipple */516#define VIRGL_POLYGON_STIPPLE_SIZE 32517#define VIRGL_POLYGON_STIPPLE_P0 1518519#define VIRGL_BIND_SHADER_SIZE 2520#define VIRGL_BIND_SHADER_HANDLE 1521#define VIRGL_BIND_SHADER_TYPE 2522523/* tess state */524#define VIRGL_TESS_STATE_SIZE 6525526/* set min samples */527#define VIRGL_SET_MIN_SAMPLES_SIZE 1528#define VIRGL_SET_MIN_SAMPLES_MASK 1529530/* set shader buffers */531#define VIRGL_SET_SHADER_BUFFER_ELEMENT_SIZE 3532#define VIRGL_SET_SHADER_BUFFER_SIZE(x) (VIRGL_SET_SHADER_BUFFER_ELEMENT_SIZE * (x)) + 2533#define VIRGL_SET_SHADER_BUFFER_SHADER_TYPE 1534#define VIRGL_SET_SHADER_BUFFER_START_SLOT 2535#define VIRGL_SET_SHADER_BUFFER_OFFSET(x) ((x) * VIRGL_SET_SHADER_BUFFER_ELEMENT_SIZE + 3)536#define VIRGL_SET_SHADER_BUFFER_LENGTH(x) ((x) * VIRGL_SET_SHADER_BUFFER_ELEMENT_SIZE + 4)537#define VIRGL_SET_SHADER_BUFFER_RES_HANDLE(x) ((x) * VIRGL_SET_SHADER_BUFFER_ELEMENT_SIZE + 5)538539/* set shader images */540#define VIRGL_SET_SHADER_IMAGE_ELEMENT_SIZE 5541#define VIRGL_SET_SHADER_IMAGE_SIZE(x) (VIRGL_SET_SHADER_IMAGE_ELEMENT_SIZE * (x)) + 2542#define VIRGL_SET_SHADER_IMAGE_SHADER_TYPE 1543#define VIRGL_SET_SHADER_IMAGE_START_SLOT 2544#define VIRGL_SET_SHADER_IMAGE_FORMAT(x) ((x) * VIRGL_SET_SHADER_IMAGE_ELEMENT_SIZE + 3)545#define VIRGL_SET_SHADER_IMAGE_ACCESS(x) ((x) * VIRGL_SET_SHADER_IMAGE_ELEMENT_SIZE + 4)546#define VIRGL_SET_SHADER_IMAGE_LAYER_OFFSET(x) ((x) * VIRGL_SET_SHADER_IMAGE_ELEMENT_SIZE + 5)547#define VIRGL_SET_SHADER_IMAGE_LEVEL_SIZE(x) ((x) * VIRGL_SET_SHADER_IMAGE_ELEMENT_SIZE + 6)548#define VIRGL_SET_SHADER_IMAGE_RES_HANDLE(x) ((x) * VIRGL_SET_SHADER_IMAGE_ELEMENT_SIZE + 7)549550/* memory barrier */551#define VIRGL_MEMORY_BARRIER_SIZE 1552#define VIRGL_MEMORY_BARRIER_FLAGS 1553554/* launch grid */555#define VIRGL_LAUNCH_GRID_SIZE 8556#define VIRGL_LAUNCH_BLOCK_X 1557#define VIRGL_LAUNCH_BLOCK_Y 2558#define VIRGL_LAUNCH_BLOCK_Z 3559#define VIRGL_LAUNCH_GRID_X 4560#define VIRGL_LAUNCH_GRID_Y 5561#define VIRGL_LAUNCH_GRID_Z 6562#define VIRGL_LAUNCH_INDIRECT_HANDLE 7563#define VIRGL_LAUNCH_INDIRECT_OFFSET 8564565/* framebuffer state no attachment */566#define VIRGL_SET_FRAMEBUFFER_STATE_NO_ATTACH_SIZE 2567#define VIRGL_SET_FRAMEBUFFER_STATE_NO_ATTACH_WIDTH_HEIGHT 1568#define VIRGL_SET_FRAMEBUFFER_STATE_NO_ATTACH_WIDTH(x) (x & 0xffff)569#define VIRGL_SET_FRAMEBUFFER_STATE_NO_ATTACH_HEIGHT(x) ((x >> 16) & 0xffff)570#define VIRGL_SET_FRAMEBUFFER_STATE_NO_ATTACH_LAYERS_SAMPLES 2571#define VIRGL_SET_FRAMEBUFFER_STATE_NO_ATTACH_LAYERS(x) (x & 0xffff)572#define VIRGL_SET_FRAMEBUFFER_STATE_NO_ATTACH_SAMPLES(x) ((x >> 16) & 0xff)573574/* texture barrier */575#define VIRGL_TEXTURE_BARRIER_SIZE 1576#define VIRGL_TEXTURE_BARRIER_FLAGS 1577578/* hw atomics */579#define VIRGL_SET_ATOMIC_BUFFER_ELEMENT_SIZE 3580#define VIRGL_SET_ATOMIC_BUFFER_SIZE(x) (VIRGL_SET_ATOMIC_BUFFER_ELEMENT_SIZE * (x)) + 1581#define VIRGL_SET_ATOMIC_BUFFER_START_SLOT 1582#define VIRGL_SET_ATOMIC_BUFFER_OFFSET(x) ((x) * VIRGL_SET_ATOMIC_BUFFER_ELEMENT_SIZE + 2)583#define VIRGL_SET_ATOMIC_BUFFER_LENGTH(x) ((x) * VIRGL_SET_ATOMIC_BUFFER_ELEMENT_SIZE + 3)584#define VIRGL_SET_ATOMIC_BUFFER_RES_HANDLE(x) ((x) * VIRGL_SET_ATOMIC_BUFFER_ELEMENT_SIZE + 4)585586/* set debug flags */587#define VIRGL_SET_DEBUG_FLAGS_MIN_SIZE 2588#define VIRGL_SET_DEBUG_FLAGSTRING_OFFSET 1589590/* query buffer object */591#define VIRGL_QUERY_RESULT_QBO_SIZE 6592#define VIRGL_QUERY_RESULT_QBO_HANDLE 1593#define VIRGL_QUERY_RESULT_QBO_QBO_HANDLE 2594#define VIRGL_QUERY_RESULT_QBO_WAIT 3595#define VIRGL_QUERY_RESULT_QBO_RESULT_TYPE 4596#define VIRGL_QUERY_RESULT_QBO_OFFSET 5597#define VIRGL_QUERY_RESULT_QBO_INDEX 6598599#define VIRGL_TRANSFER_TO_HOST 1600#define VIRGL_TRANSFER_FROM_HOST 2601602/* Transfer */603#define VIRGL_TRANSFER3D_SIZE 13604/* The first 11 dwords are the same as VIRGL_RESOURCE_IW_* */605#define VIRGL_TRANSFER3D_DATA_OFFSET 12606#define VIRGL_TRANSFER3D_DIRECTION 13607608/* Copy transfer */609#define VIRGL_COPY_TRANSFER3D_SIZE 14610/* The first 11 dwords are the same as VIRGL_RESOURCE_IW_* */611#define VIRGL_COPY_TRANSFER3D_SRC_RES_HANDLE 12612#define VIRGL_COPY_TRANSFER3D_SRC_RES_OFFSET 13613#define VIRGL_COPY_TRANSFER3D_SYNCHRONIZED 14614615/* set tweak flags */616#define VIRGL_SET_TWEAKS_SIZE 2617#define VIRGL_SET_TWEAKS_ID 1618#define VIRGL_SET_TWEAKS_VALUE 2619620enum vrend_tweak_type {621virgl_tweak_gles_brga_emulate,622virgl_tweak_gles_brga_apply_dest_swizzle,623virgl_tweak_gles_tf3_samples_passes_multiplier,624virgl_tweak_undefined625};626627/* Clear texture */628#define VIRGL_CLEAR_TEXTURE_SIZE 12629#define VIRGL_TEXTURE_HANDLE 1630#define VIRGL_TEXTURE_LEVEL 2631#define VIRGL_TEXTURE_SRC_X 3632#define VIRGL_TEXTURE_SRC_Y 4633#define VIRGL_TEXTURE_SRC_Z 5634#define VIRGL_TEXTURE_SRC_W 6635#define VIRGL_TEXTURE_SRC_H 7636#define VIRGL_TEXTURE_SRC_D 8637#define VIRGL_TEXTURE_ARRAY_A 9638#define VIRGL_TEXTURE_ARRAY_B 10639#define VIRGL_TEXTURE_ARRAY_C 11640#define VIRGL_TEXTURE_ARRAY_D 12641642/* virgl create */643#define VIRGL_PIPE_RES_CREATE_SIZE 11644#define VIRGL_PIPE_RES_CREATE_TARGET 1645#define VIRGL_PIPE_RES_CREATE_FORMAT 2646#define VIRGL_PIPE_RES_CREATE_BIND 3647#define VIRGL_PIPE_RES_CREATE_WIDTH 4648#define VIRGL_PIPE_RES_CREATE_HEIGHT 5649#define VIRGL_PIPE_RES_CREATE_DEPTH 6650#define VIRGL_PIPE_RES_CREATE_ARRAY_SIZE 7651#define VIRGL_PIPE_RES_CREATE_LAST_LEVEL 8652#define VIRGL_PIPE_RES_CREATE_NR_SAMPLES 9653#define VIRGL_PIPE_RES_CREATE_FLAGS 10654#define VIRGL_PIPE_RES_CREATE_BLOB_ID 11655656/* VIRGL_CCMD_PIPE_RESOURCE_SET_TYPE */657#define VIRGL_PIPE_RES_SET_TYPE_SIZE(nplanes) (8 + (nplanes) * 2)658#define VIRGL_PIPE_RES_SET_TYPE_RES_HANDLE 1659#define VIRGL_PIPE_RES_SET_TYPE_FORMAT 2660#define VIRGL_PIPE_RES_SET_TYPE_BIND 3661#define VIRGL_PIPE_RES_SET_TYPE_WIDTH 4662#define VIRGL_PIPE_RES_SET_TYPE_HEIGHT 5663#define VIRGL_PIPE_RES_SET_TYPE_USAGE 6664#define VIRGL_PIPE_RES_SET_TYPE_MODIFIER_LO 7665#define VIRGL_PIPE_RES_SET_TYPE_MODIFIER_HI 8666#define VIRGL_PIPE_RES_SET_TYPE_PLANE_STRIDE(plane) (9 + (plane) * 2)667#define VIRGL_PIPE_RES_SET_TYPE_PLANE_OFFSET(plane) (10 + (plane) * 2)668669/* send string marker */670#define VIRGL_SEND_STRING_MARKER_MIN_SIZE 2671#define VIRGL_SEND_STRING_MARKER_STRING_SIZE 1672#define VIRGL_SEND_STRING_MARKER_OFFSET 2673674#endif675676677