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PojavLauncherTeam
GitHub Repository: PojavLauncherTeam/mobile
 Path: blob/master/src/hotspot/cpu/arm/c1_FrameMap_arm.hpp
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/*

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 * Copyright (c) 2008, 2019, Oracle and/or its affiliates. All rights reserved.

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 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

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 *

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 * This code is free software; you can redistribute it and/or modify it

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 * under the terms of the GNU General Public License version 2 only, as

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 * published by the Free Software Foundation.

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 *

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 * This code is distributed in the hope that it will be useful, but WITHOUT

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 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

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 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

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 * version 2 for more details (a copy is included in the LICENSE file that

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 * accompanied this code).

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 *

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 * You should have received a copy of the GNU General Public License version

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 * 2 along with this work; if not, write to the Free Software Foundation,

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 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

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 *

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 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA

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 * or visit www.oracle.com if you need additional information or have any

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 * questions.

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 *

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 */

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#ifndef CPU_ARM_C1_FRAMEMAP_ARM_HPP

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#define CPU_ARM_C1_FRAMEMAP_ARM_HPP

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 public:

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  enum {

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    first_available_sp_in_frame = 0,

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    frame_pad_in_bytes = 2*wordSize      // Account for FP/LR saved at build_frame().

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  };

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  static LIR_Opr R0_opr;

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  static LIR_Opr R1_opr;

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  static LIR_Opr R2_opr;

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  static LIR_Opr R3_opr;

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  static LIR_Opr R4_opr;

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  static LIR_Opr R5_opr;

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  // add more predefined register oprs as needed

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  static LIR_Opr R0_oop_opr;

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  static LIR_Opr R1_oop_opr;

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  static LIR_Opr R2_oop_opr;

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  static LIR_Opr R3_oop_opr;

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  static LIR_Opr R4_oop_opr;

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  static LIR_Opr R5_oop_opr;

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  static LIR_Opr R0_metadata_opr;

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  static LIR_Opr R1_metadata_opr;

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  static LIR_Opr R2_metadata_opr;

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  static LIR_Opr R3_metadata_opr;

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  static LIR_Opr R4_metadata_opr;

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  static LIR_Opr R5_metadata_opr;

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  static LIR_Opr LR_opr;

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  static LIR_Opr LR_oop_opr;

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  static LIR_Opr LR_ptr_opr;

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  static LIR_Opr FP_opr;

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  static LIR_Opr SP_opr;

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  static LIR_Opr Rthread_opr;

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  static LIR_Opr Int_result_opr;

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  static LIR_Opr Long_result_opr;

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  static LIR_Opr Object_result_opr;

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  static LIR_Opr Float_result_opr;

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  static LIR_Opr Double_result_opr;

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  static LIR_Opr Exception_oop_opr;

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  static LIR_Opr Exception_pc_opr;

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  static LIR_Opr as_long_opr(Register r, Register r2) {

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    return LIR_OprFact::double_cpu(cpu_reg2rnr(r), cpu_reg2rnr(r2));

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  }

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  static LIR_Opr as_pointer_opr(Register r) {

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    return LIR_OprFact::single_cpu(cpu_reg2rnr(r));

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  }

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  static LIR_Opr as_double_opr(FloatRegister r) {

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    return LIR_OprFact::double_fpu(r->encoding(), r->successor()->encoding());

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  }

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  static LIR_Opr as_float_opr(FloatRegister r) {

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    return LIR_OprFact::single_fpu(r->encoding());

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  }

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  static VMReg fpu_regname(int n);

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  static bool is_caller_save_register(LIR_Opr opr) {

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    return true;

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  }

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  static int adjust_reg_range(int range) {

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    // Reduce the number of available regs (to free Rheap_base) in case of compressed oops

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    if (UseCompressedOops || UseCompressedClassPointers) return range - 1;

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    return range;

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  }

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  static int nof_caller_save_cpu_regs() {

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    return adjust_reg_range(pd_nof_caller_save_cpu_regs_frame_map);

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  }

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  static int last_cpu_reg() {

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    return pd_last_cpu_reg;

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  }

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#endif // CPU_ARM_C1_FRAMEMAP_ARM_HPP

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