CoCalc -- assembler

GitHub Repository: PojavLauncherTeam/mobile
Path: blob/master/src/hotspot/cpu/ppc/assembler_ppc.hpp
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/*
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 * Copyright (c) 2002, 2021, Oracle and/or its affiliates. All rights reserved.
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 * Copyright (c) 2012, 2021 SAP SE. All rights reserved.
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 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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 *
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 * This code is free software; you can redistribute it and/or modify it
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 * under the terms of the GNU General Public License version 2 only, as
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 * published by the Free Software Foundation.
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 *
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 * This code is distributed in the hope that it will be useful, but WITHOUT
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 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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 * version 2 for more details (a copy is included in the LICENSE file that
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 * accompanied this code).
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 *
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 * You should have received a copy of the GNU General Public License version
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 * 2 along with this work; if not, write to the Free Software Foundation,
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 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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 *
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 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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 * or visit www.oracle.com if you need additional information or have any
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 * questions.
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 *
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 */
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#ifndef CPU_PPC_ASSEMBLER_PPC_HPP
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#define CPU_PPC_ASSEMBLER_PPC_HPP
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#include "asm/assembler.hpp"
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#include "asm/register.hpp"
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// Address is an abstraction used to represent a memory location
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// as used in assembler instructions.
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// PPC instructions grok either baseReg + indexReg or baseReg + disp.
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class Address {
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 private:
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  Register _base;         // Base register.
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  Register _index;        // Index register.
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  intptr_t _disp;         // Displacement.
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 public:
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  Address(Register b, Register i, address d = 0)
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    : _base(b), _index(i), _disp((intptr_t)d) {
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    assert(i == noreg || d == 0, "can't have both");
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  }
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  Address(Register b, address d = 0)
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    : _base(b), _index(noreg), _disp((intptr_t)d) {}
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  Address(Register b, intptr_t d)
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    : _base(b), _index(noreg), _disp(d) {}
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  Address(Register b, RegisterOrConstant roc)
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    : _base(b), _index(noreg), _disp(0) {
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    if (roc.is_constant()) _disp = roc.as_constant(); else _index = roc.as_register();
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  }
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  Address()
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    : _base(noreg), _index(noreg), _disp(0) {}
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  // accessors
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  Register base()  const { return _base; }
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  Register index() const { return _index; }
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  int      disp()  const { return (int)_disp; }
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  bool     is_const() const { return _base == noreg && _index == noreg; }
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};
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class AddressLiteral {
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 private:
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  address          _address;
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  RelocationHolder _rspec;
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  RelocationHolder rspec_from_rtype(relocInfo::relocType rtype, address addr) {
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    switch (rtype) {
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    case relocInfo::external_word_type:
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      return external_word_Relocation::spec(addr);
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    case relocInfo::internal_word_type:
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      return internal_word_Relocation::spec(addr);
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    case relocInfo::opt_virtual_call_type:
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      return opt_virtual_call_Relocation::spec();
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    case relocInfo::static_call_type:
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      return static_call_Relocation::spec();
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    case relocInfo::runtime_call_type:
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      return runtime_call_Relocation::spec();
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    case relocInfo::none:
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      return RelocationHolder();
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    default:
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      ShouldNotReachHere();
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      return RelocationHolder();
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    }
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  }
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 protected:
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  // creation
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  AddressLiteral() : _address(NULL), _rspec(NULL) {}
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 public:
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  AddressLiteral(address addr, RelocationHolder const& rspec)
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    : _address(addr),
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      _rspec(rspec) {}
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  AddressLiteral(address addr, relocInfo::relocType rtype = relocInfo::none)
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    : _address((address) addr),
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      _rspec(rspec_from_rtype(rtype, (address) addr)) {}
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  AddressLiteral(oop* addr, relocInfo::relocType rtype = relocInfo::none)
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    : _address((address) addr),
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      _rspec(rspec_from_rtype(rtype, (address) addr)) {}
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  intptr_t value() const { return (intptr_t) _address; }
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  const RelocationHolder& rspec() const { return _rspec; }
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};
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// Argument is an abstraction used to represent an outgoing
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// actual argument or an incoming formal parameter, whether
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// it resides in memory or in a register, in a manner consistent
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// with the PPC Application Binary Interface, or ABI. This is
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// often referred to as the native or C calling convention.
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class Argument {
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 private:
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  int _number;  // The number of the argument.
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 public:
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  enum {
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    // Only 8 registers may contain integer parameters.
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    n_register_parameters = 8,
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    // Can have up to 8 floating registers.
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    n_float_register_parameters = 8,
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    // PPC C calling conventions.
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    // The first eight arguments are passed in int regs if they are int.
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    n_int_register_parameters_c = 8,
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    // The first thirteen float arguments are passed in float regs.
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    n_float_register_parameters_c = 13,
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    // Only the first 8 parameters are not placed on the stack. Aix disassembly
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    // shows that xlC places all float args after argument 8 on the stack AND
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    // in a register. This is not documented, but we follow this convention, too.
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    n_regs_not_on_stack_c = 8,
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  };
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  // creation
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  Argument(int number) : _number(number) {}
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  int  number() const { return _number; }
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  // Locating register-based arguments:
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  bool is_register() const { return _number < n_register_parameters; }
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  Register as_register() const {
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    assert(is_register(), "must be a register argument");
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    return as_Register(number() + R3_ARG1->encoding());
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  }
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};
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#if !defined(ABI_ELFv2)
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// A ppc64 function descriptor.
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struct FunctionDescriptor {
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 private:
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  address _entry;
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  address _toc;
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  address _env;
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 public:
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  inline address entry() const { return _entry; }
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  inline address toc()   const { return _toc; }
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  inline address env()   const { return _env; }
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  inline void set_entry(address entry) { _entry = entry; }
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  inline void set_toc(  address toc)   { _toc   = toc; }
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  inline void set_env(  address env)   { _env   = env; }
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  inline static ByteSize entry_offset() { return byte_offset_of(FunctionDescriptor, _entry); }
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  inline static ByteSize toc_offset()   { return byte_offset_of(FunctionDescriptor, _toc); }
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  inline static ByteSize env_offset()   { return byte_offset_of(FunctionDescriptor, _env); }
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  // Friend functions can be called without loading toc and env.
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  enum {
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    friend_toc = 0xcafe,
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    friend_env = 0xc0de
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  };
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  inline bool is_friend_function() const {
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    return (toc() == (address) friend_toc) && (env() == (address) friend_env);
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  }
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  // Constructor for stack-allocated instances.
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  FunctionDescriptor() {
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    _entry = (address) 0xbad;
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    _toc   = (address) 0xbad;
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    _env   = (address) 0xbad;
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  }
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};
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#endif
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// The PPC Assembler: Pure assembler doing NO optimizations on the
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// instruction level; i.e., what you write is what you get. The
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// Assembler is generating code into a CodeBuffer.
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class Assembler : public AbstractAssembler {
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 protected:
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  // Displacement routines
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  static int  patched_branch(int dest_pos, int inst, int inst_pos);
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  static int  branch_destination(int inst, int pos);
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  friend class AbstractAssembler;
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  // Code patchers need various routines like inv_wdisp()
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  friend class NativeInstruction;
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  friend class NativeGeneralJump;
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  friend class Relocation;
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 public:
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  enum shifts {
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    XO_21_29_SHIFT = 2,
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    XO_21_30_SHIFT = 1,
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    XO_27_29_SHIFT = 2,
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    XO_30_31_SHIFT = 0,
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    SPR_5_9_SHIFT  = 11u, // SPR_5_9 field in bits 11 -- 15
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    SPR_0_4_SHIFT  = 16u, // SPR_0_4 field in bits 16 -- 20
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    RS_SHIFT       = 21u, // RS field in bits 21 -- 25
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    OPCODE_SHIFT   = 26u, // opcode in bits 26 -- 31
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    // Shift counts in prefix word
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    PRE_TYPE_SHIFT = 24u, // Prefix type in bits 24 -- 25
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    PRE_ST1_SHIFT  = 23u, // ST1 field in bits 23 -- 23
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    PRE_R_SHIFT    = 20u, // R-bit in bits 20 -- 20
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    PRE_ST4_SHIFT  = 20u, // ST4 field in bits 23 -- 20
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  };
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  enum opcdxos_masks {
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    XL_FORM_OPCODE_MASK = (63u << OPCODE_SHIFT) | (1023u << 1),
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    ADDI_OPCODE_MASK    = (63u << OPCODE_SHIFT),
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    ADDIS_OPCODE_MASK   = (63u << OPCODE_SHIFT),
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    BXX_OPCODE_MASK     = (63u << OPCODE_SHIFT),
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    BCXX_OPCODE_MASK    = (63u << OPCODE_SHIFT),
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    // trap instructions
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    TDI_OPCODE_MASK     = (63u << OPCODE_SHIFT),
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    TWI_OPCODE_MASK     = (63u << OPCODE_SHIFT),
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    TD_OPCODE_MASK      = (63u << OPCODE_SHIFT) | (1023u << 1),
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    TW_OPCODE_MASK      = (63u << OPCODE_SHIFT) | (1023u << 1),
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    LD_OPCODE_MASK      = (63u << OPCODE_SHIFT) | (3u << XO_30_31_SHIFT), // DS-FORM
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    STD_OPCODE_MASK     = LD_OPCODE_MASK,
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    STDU_OPCODE_MASK    = STD_OPCODE_MASK,
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    STDX_OPCODE_MASK    = (63u << OPCODE_SHIFT) | (1023u << 1),
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    STDUX_OPCODE_MASK   = STDX_OPCODE_MASK,
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    STW_OPCODE_MASK     = (63u << OPCODE_SHIFT),
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    STWU_OPCODE_MASK    = STW_OPCODE_MASK,
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    STWX_OPCODE_MASK    = (63u << OPCODE_SHIFT) | (1023u << 1),
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    STWUX_OPCODE_MASK   = STWX_OPCODE_MASK,
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    MTCTR_OPCODE_MASK   = ~(31u << RS_SHIFT),
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    ORI_OPCODE_MASK     = (63u << OPCODE_SHIFT),
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    ORIS_OPCODE_MASK    = (63u << OPCODE_SHIFT),
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    RLDICR_OPCODE_MASK  = (63u << OPCODE_SHIFT) | (7u << XO_27_29_SHIFT)
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  };
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  enum opcdxos {
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    ADD_OPCODE    = (31u << OPCODE_SHIFT | 266u << 1),
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    ADDC_OPCODE   = (31u << OPCODE_SHIFT |  10u << 1),
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    ADDI_OPCODE   = (14u << OPCODE_SHIFT),
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    ADDIS_OPCODE  = (15u << OPCODE_SHIFT),
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    ADDIC__OPCODE = (13u << OPCODE_SHIFT),
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    ADDE_OPCODE   = (31u << OPCODE_SHIFT | 138u << 1),
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    ADDME_OPCODE  = (31u << OPCODE_SHIFT | 234u << 1),
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    ADDZE_OPCODE  = (31u << OPCODE_SHIFT | 202u << 1),
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    SUBF_OPCODE   = (31u << OPCODE_SHIFT |  40u << 1),
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    SUBFC_OPCODE  = (31u << OPCODE_SHIFT |   8u << 1),
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    SUBFE_OPCODE  = (31u << OPCODE_SHIFT | 136u << 1),
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    SUBFIC_OPCODE = (8u  << OPCODE_SHIFT),
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    SUBFME_OPCODE = (31u << OPCODE_SHIFT | 232u << 1),
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    SUBFZE_OPCODE = (31u << OPCODE_SHIFT | 200u << 1),
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    DIVW_OPCODE   = (31u << OPCODE_SHIFT | 491u << 1),
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    DIVWU_OPCODE  = (31u << OPCODE_SHIFT | 459u << 1),
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    MULLW_OPCODE  = (31u << OPCODE_SHIFT | 235u << 1),
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    MULHW_OPCODE  = (31u << OPCODE_SHIFT |  75u << 1),
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    MULHWU_OPCODE = (31u << OPCODE_SHIFT |  11u << 1),
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    MULLI_OPCODE  = (7u  << OPCODE_SHIFT),
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    AND_OPCODE    = (31u << OPCODE_SHIFT |  28u << 1),
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    ANDI_OPCODE   = (28u << OPCODE_SHIFT),
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    ANDIS_OPCODE  = (29u << OPCODE_SHIFT),
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    ANDC_OPCODE   = (31u << OPCODE_SHIFT |  60u << 1),
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    ORC_OPCODE    = (31u << OPCODE_SHIFT | 412u << 1),
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    OR_OPCODE     = (31u << OPCODE_SHIFT | 444u << 1),
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    ORI_OPCODE    = (24u << OPCODE_SHIFT),
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    ORIS_OPCODE   = (25u << OPCODE_SHIFT),
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    XOR_OPCODE    = (31u << OPCODE_SHIFT | 316u << 1),
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    XORI_OPCODE   = (26u << OPCODE_SHIFT),
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    XORIS_OPCODE  = (27u << OPCODE_SHIFT),
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    NEG_OPCODE    = (31u << OPCODE_SHIFT | 104u << 1),
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    RLWINM_OPCODE = (21u << OPCODE_SHIFT),
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    CLRRWI_OPCODE = RLWINM_OPCODE,
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    CLRLWI_OPCODE = RLWINM_OPCODE,
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    RLWIMI_OPCODE = (20u << OPCODE_SHIFT),
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    SLW_OPCODE    = (31u << OPCODE_SHIFT |  24u << 1),
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    SLWI_OPCODE   = RLWINM_OPCODE,
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    SRW_OPCODE    = (31u << OPCODE_SHIFT | 536u << 1),
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    SRWI_OPCODE   = RLWINM_OPCODE,
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    SRAW_OPCODE   = (31u << OPCODE_SHIFT | 792u << 1),
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    SRAWI_OPCODE  = (31u << OPCODE_SHIFT | 824u << 1),
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    CMP_OPCODE    = (31u << OPCODE_SHIFT |   0u << 1),
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    CMPI_OPCODE   = (11u << OPCODE_SHIFT),
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    CMPL_OPCODE   = (31u << OPCODE_SHIFT |  32u << 1),
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    CMPLI_OPCODE  = (10u << OPCODE_SHIFT),
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    CMPRB_OPCODE  = (31u << OPCODE_SHIFT | 192u << 1),
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    CMPEQB_OPCODE = (31u << OPCODE_SHIFT | 224u << 1),
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    ISEL_OPCODE   = (31u << OPCODE_SHIFT |  15u << 1),
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    // Special purpose registers
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    MTSPR_OPCODE  = (31u << OPCODE_SHIFT | 467u << 1),
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    MFSPR_OPCODE  = (31u << OPCODE_SHIFT | 339u << 1),
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    MTXER_OPCODE  = (MTSPR_OPCODE | 1 << SPR_0_4_SHIFT),
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    MFXER_OPCODE  = (MFSPR_OPCODE | 1 << SPR_0_4_SHIFT),
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    MTDSCR_OPCODE = (MTSPR_OPCODE | 3 << SPR_0_4_SHIFT),
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    MFDSCR_OPCODE = (MFSPR_OPCODE | 3 << SPR_0_4_SHIFT),
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    MTLR_OPCODE   = (MTSPR_OPCODE | 8 << SPR_0_4_SHIFT),
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    MFLR_OPCODE   = (MFSPR_OPCODE | 8 << SPR_0_4_SHIFT),
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    MTCTR_OPCODE  = (MTSPR_OPCODE | 9 << SPR_0_4_SHIFT),
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    MFCTR_OPCODE  = (MFSPR_OPCODE | 9 << SPR_0_4_SHIFT),
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    // Attention: Higher and lower half are inserted in reversed order.
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    MTTFHAR_OPCODE   = (MTSPR_OPCODE | 4 << SPR_5_9_SHIFT | 0 << SPR_0_4_SHIFT),
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    MFTFHAR_OPCODE   = (MFSPR_OPCODE | 4 << SPR_5_9_SHIFT | 0 << SPR_0_4_SHIFT),
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    MTTFIAR_OPCODE   = (MTSPR_OPCODE | 4 << SPR_5_9_SHIFT | 1 << SPR_0_4_SHIFT),
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    MFTFIAR_OPCODE   = (MFSPR_OPCODE | 4 << SPR_5_9_SHIFT | 1 << SPR_0_4_SHIFT),
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    MTTEXASR_OPCODE  = (MTSPR_OPCODE | 4 << SPR_5_9_SHIFT | 2 << SPR_0_4_SHIFT),
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    MFTEXASR_OPCODE  = (MFSPR_OPCODE | 4 << SPR_5_9_SHIFT | 2 << SPR_0_4_SHIFT),
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    MTTEXASRU_OPCODE = (MTSPR_OPCODE | 4 << SPR_5_9_SHIFT | 3 << SPR_0_4_SHIFT),
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    MFTEXASRU_OPCODE = (MFSPR_OPCODE | 4 << SPR_5_9_SHIFT | 3 << SPR_0_4_SHIFT),
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    MTVRSAVE_OPCODE  = (MTSPR_OPCODE | 8 << SPR_5_9_SHIFT | 0 << SPR_0_4_SHIFT),
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    MFVRSAVE_OPCODE  = (MFSPR_OPCODE | 8 << SPR_5_9_SHIFT | 0 << SPR_0_4_SHIFT),
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    MFTB_OPCODE   = (MFSPR_OPCODE | 8 << SPR_5_9_SHIFT | 12 << SPR_0_4_SHIFT),
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    MTCRF_OPCODE  = (31u << OPCODE_SHIFT | 144u << 1),
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    MFCR_OPCODE   = (31u << OPCODE_SHIFT | 19u << 1),
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    MCRF_OPCODE   = (19u << OPCODE_SHIFT | 0u << 1),
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    MCRXRX_OPCODE = (31u << OPCODE_SHIFT | 576u << 1),
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    SETB_OPCODE   = (31u << OPCODE_SHIFT | 128u << 1),
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    SETBC_OPCODE  = (31u << OPCODE_SHIFT | 384u << 1),
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    SETNBC_OPCODE = (31u << OPCODE_SHIFT | 448u << 1),
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    // condition register logic instructions
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    CRAND_OPCODE  = (19u << OPCODE_SHIFT | 257u << 1),
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    CRNAND_OPCODE = (19u << OPCODE_SHIFT | 225u << 1),
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    CROR_OPCODE   = (19u << OPCODE_SHIFT | 449u << 1),
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    CRXOR_OPCODE  = (19u << OPCODE_SHIFT | 193u << 1),
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    CRNOR_OPCODE  = (19u << OPCODE_SHIFT |  33u << 1),
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    CREQV_OPCODE  = (19u << OPCODE_SHIFT | 289u << 1),
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    CRANDC_OPCODE = (19u << OPCODE_SHIFT | 129u << 1),
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    CRORC_OPCODE  = (19u << OPCODE_SHIFT | 417u << 1),
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365
    BCLR_OPCODE   = (19u << OPCODE_SHIFT | 16u << 1),
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    BXX_OPCODE      = (18u << OPCODE_SHIFT),
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    BCXX_OPCODE     = (16u << OPCODE_SHIFT),
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369
    // CTR-related opcodes
370
    BCCTR_OPCODE  = (19u << OPCODE_SHIFT | 528u << 1),
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372
    LWZ_OPCODE   = (32u << OPCODE_SHIFT),
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    LWZX_OPCODE  = (31u << OPCODE_SHIFT |  23u << 1),
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    LWZU_OPCODE  = (33u << OPCODE_SHIFT),
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    LWBRX_OPCODE = (31u << OPCODE_SHIFT |  534 << 1),
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377
    LHA_OPCODE   = (42u << OPCODE_SHIFT),
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    LHAX_OPCODE  = (31u << OPCODE_SHIFT | 343u << 1),
379
    LHAU_OPCODE  = (43u << OPCODE_SHIFT),
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381
    LHZ_OPCODE   = (40u << OPCODE_SHIFT),
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    LHZX_OPCODE  = (31u << OPCODE_SHIFT | 279u << 1),
383
    LHZU_OPCODE  = (41u << OPCODE_SHIFT),
384
    LHBRX_OPCODE = (31u << OPCODE_SHIFT |  790 << 1),
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386
    LBZ_OPCODE   = (34u << OPCODE_SHIFT),
387
    LBZX_OPCODE  = (31u << OPCODE_SHIFT |  87u << 1),
388
    LBZU_OPCODE  = (35u << OPCODE_SHIFT),
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390
    STW_OPCODE   = (36u << OPCODE_SHIFT),
391
    STWX_OPCODE  = (31u << OPCODE_SHIFT | 151u << 1),
392
    STWU_OPCODE  = (37u << OPCODE_SHIFT),
393
    STWUX_OPCODE = (31u << OPCODE_SHIFT | 183u << 1),
394
    STWBRX_OPCODE = (31u << OPCODE_SHIFT | 662u << 1),
395

396
    STH_OPCODE   = (44u << OPCODE_SHIFT),
397
    STHX_OPCODE  = (31u << OPCODE_SHIFT | 407u << 1),
398
    STHU_OPCODE  = (45u << OPCODE_SHIFT),
399
    STHBRX_OPCODE = (31u << OPCODE_SHIFT | 918u << 1),
400

401
    STB_OPCODE   = (38u << OPCODE_SHIFT),
402
    STBX_OPCODE  = (31u << OPCODE_SHIFT | 215u << 1),
403
    STBU_OPCODE  = (39u << OPCODE_SHIFT),
404

405
    EXTSB_OPCODE = (31u << OPCODE_SHIFT | 954u << 1),
406
    EXTSH_OPCODE = (31u << OPCODE_SHIFT | 922u << 1),
407
    EXTSW_OPCODE = (31u << OPCODE_SHIFT | 986u << 1),               // X-FORM
408

409
    // 32 bit opcode encodings
410

411
    LWA_OPCODE    = (58u << OPCODE_SHIFT |   2u << XO_30_31_SHIFT), // DS-FORM
412
    LWAX_OPCODE   = (31u << OPCODE_SHIFT | 341u << XO_21_30_SHIFT), // X-FORM
413

414
    CNTLZW_OPCODE = (31u << OPCODE_SHIFT |  26u << XO_21_30_SHIFT), // X-FORM
415
    CNTTZW_OPCODE = (31u << OPCODE_SHIFT | 538u << XO_21_30_SHIFT), // X-FORM
416

417
    // 64 bit opcode encodings
418

419
    LD_OPCODE     = (58u << OPCODE_SHIFT |   0u << XO_30_31_SHIFT), // DS-FORM
420
    LDU_OPCODE    = (58u << OPCODE_SHIFT |   1u << XO_30_31_SHIFT), // DS-FORM
421
    LDX_OPCODE    = (31u << OPCODE_SHIFT |  21u << XO_21_30_SHIFT), // X-FORM
422
    LDBRX_OPCODE  = (31u << OPCODE_SHIFT | 532u << 1),              // X-FORM
423

424
    STD_OPCODE    = (62u << OPCODE_SHIFT |   0u << XO_30_31_SHIFT), // DS-FORM
425
    STDU_OPCODE   = (62u << OPCODE_SHIFT |   1u << XO_30_31_SHIFT), // DS-FORM
426
    STDUX_OPCODE  = (31u << OPCODE_SHIFT | 181u << 1),              // X-FORM
427
    STDX_OPCODE   = (31u << OPCODE_SHIFT | 149u << XO_21_30_SHIFT), // X-FORM
428
    STDBRX_OPCODE = (31u << OPCODE_SHIFT | 660u << 1),              // X-FORM
429

430
    RLDICR_OPCODE = (30u << OPCODE_SHIFT |   1u << XO_27_29_SHIFT), // MD-FORM
431
    RLDICL_OPCODE = (30u << OPCODE_SHIFT |   0u << XO_27_29_SHIFT), // MD-FORM
432
    RLDIC_OPCODE  = (30u << OPCODE_SHIFT |   2u << XO_27_29_SHIFT), // MD-FORM
433
    RLDIMI_OPCODE = (30u << OPCODE_SHIFT |   3u << XO_27_29_SHIFT), // MD-FORM
434

435
    SRADI_OPCODE  = (31u << OPCODE_SHIFT | 413u << XO_21_29_SHIFT), // XS-FORM
436

437
    SLD_OPCODE    = (31u << OPCODE_SHIFT |  27u << 1),              // X-FORM
438
    SRD_OPCODE    = (31u << OPCODE_SHIFT | 539u << 1),              // X-FORM
439
    SRAD_OPCODE   = (31u << OPCODE_SHIFT | 794u << 1),              // X-FORM
440

441
    MULLD_OPCODE  = (31u << OPCODE_SHIFT | 233u << 1),              // XO-FORM
442
    MULHD_OPCODE  = (31u << OPCODE_SHIFT |  73u << 1),              // XO-FORM
443
    MULHDU_OPCODE = (31u << OPCODE_SHIFT |   9u << 1),              // XO-FORM
444
    DIVD_OPCODE   = (31u << OPCODE_SHIFT | 489u << 1),              // XO-FORM
445

446
    CNTLZD_OPCODE = (31u << OPCODE_SHIFT |  58u << XO_21_30_SHIFT), // X-FORM
447
    CNTTZD_OPCODE = (31u << OPCODE_SHIFT | 570u << XO_21_30_SHIFT), // X-FORM
448
    NAND_OPCODE   = (31u << OPCODE_SHIFT | 476u << XO_21_30_SHIFT), // X-FORM
449
    NOR_OPCODE    = (31u << OPCODE_SHIFT | 124u << XO_21_30_SHIFT), // X-FORM
450

451
    // Byte reverse opcodes (introduced with Power10)
452
    BRH_OPCODE    = (31u << OPCODE_SHIFT | 219u << 1),              // X-FORM
453
    BRW_OPCODE    = (31u << OPCODE_SHIFT | 155u << 1),              // X-FORM
454
    BRD_OPCODE    = (31u << OPCODE_SHIFT | 187u << 1),              // X-FORM
455

456
    // opcodes only used for floating arithmetic
457
    FADD_OPCODE   = (63u << OPCODE_SHIFT |  21u << 1),
458
    FADDS_OPCODE  = (59u << OPCODE_SHIFT |  21u << 1),
459
    FCMPU_OPCODE  = (63u << OPCODE_SHIFT |  00u << 1),
460
    FDIV_OPCODE   = (63u << OPCODE_SHIFT |  18u << 1),
461
    FDIVS_OPCODE  = (59u << OPCODE_SHIFT |  18u << 1),
462
    FMR_OPCODE    = (63u << OPCODE_SHIFT |  72u << 1),
463
    FRIN_OPCODE   = (63u << OPCODE_SHIFT | 392u << 1),
464
    FRIP_OPCODE   = (63u << OPCODE_SHIFT | 456u << 1),
465
    FRIM_OPCODE   = (63u << OPCODE_SHIFT | 488u << 1),
466
    // These are special Power6 opcodes, reused for "lfdepx" and "stfdepx"
467
    // on Power7.  Do not use.
468
    // MFFGPR_OPCODE  = (31u << OPCODE_SHIFT | 607u << 1),
469
    // MFTGPR_OPCODE  = (31u << OPCODE_SHIFT | 735u << 1),
470
    CMPB_OPCODE    = (31u << OPCODE_SHIFT |  508  << 1),
471
    POPCNTB_OPCODE = (31u << OPCODE_SHIFT |  122  << 1),
472
    POPCNTW_OPCODE = (31u << OPCODE_SHIFT |  378  << 1),
473
    POPCNTD_OPCODE = (31u << OPCODE_SHIFT |  506  << 1),
474
    FABS_OPCODE    = (63u << OPCODE_SHIFT |  264u << 1),
475
    FNABS_OPCODE   = (63u << OPCODE_SHIFT |  136u << 1),
476
    FMUL_OPCODE    = (63u << OPCODE_SHIFT |   25u << 1),
477
    FMULS_OPCODE   = (59u << OPCODE_SHIFT |   25u << 1),
478
    FNEG_OPCODE    = (63u << OPCODE_SHIFT |   40u << 1),
479
    FSUB_OPCODE    = (63u << OPCODE_SHIFT |   20u << 1),
480
    FSUBS_OPCODE   = (59u << OPCODE_SHIFT |   20u << 1),
481

482
    // PPC64-internal FPU conversion opcodes
483
    FCFID_OPCODE   = (63u << OPCODE_SHIFT |  846u << 1),
484
    FCFIDS_OPCODE  = (59u << OPCODE_SHIFT |  846u << 1),
485
    FCTID_OPCODE   = (63u << OPCODE_SHIFT |  814u << 1),
486
    FCTIDZ_OPCODE  = (63u << OPCODE_SHIFT |  815u << 1),
487
    FCTIW_OPCODE   = (63u << OPCODE_SHIFT |   14u << 1),
488
    FCTIWZ_OPCODE  = (63u << OPCODE_SHIFT |   15u << 1),
489
    FRSP_OPCODE    = (63u << OPCODE_SHIFT |   12u << 1),
490

491
    // Fused multiply-accumulate instructions.
492
    FMADD_OPCODE   = (63u << OPCODE_SHIFT |   29u << 1),
493
    FMADDS_OPCODE  = (59u << OPCODE_SHIFT |   29u << 1),
494
    FMSUB_OPCODE   = (63u << OPCODE_SHIFT |   28u << 1),
495
    FMSUBS_OPCODE  = (59u << OPCODE_SHIFT |   28u << 1),
496
    FNMADD_OPCODE  = (63u << OPCODE_SHIFT |   31u << 1),
497
    FNMADDS_OPCODE = (59u << OPCODE_SHIFT |   31u << 1),
498
    FNMSUB_OPCODE  = (63u << OPCODE_SHIFT |   30u << 1),
499
    FNMSUBS_OPCODE = (59u << OPCODE_SHIFT |   30u << 1),
500

501
    LFD_OPCODE     = (50u << OPCODE_SHIFT |   00u << 1),
502
    LFDU_OPCODE    = (51u << OPCODE_SHIFT |   00u << 1),
503
    LFDX_OPCODE    = (31u << OPCODE_SHIFT |  599u << 1),
504
    LFS_OPCODE     = (48u << OPCODE_SHIFT |   00u << 1),
505
    LFSU_OPCODE    = (49u << OPCODE_SHIFT |   00u << 1),
506
    LFSX_OPCODE    = (31u << OPCODE_SHIFT |  535u << 1),
507

508
    STFD_OPCODE    = (54u << OPCODE_SHIFT |   00u << 1),
509
    STFDU_OPCODE   = (55u << OPCODE_SHIFT |   00u << 1),
510
    STFDX_OPCODE   = (31u << OPCODE_SHIFT |  727u << 1),
511
    STFS_OPCODE    = (52u << OPCODE_SHIFT |   00u << 1),
512
    STFSU_OPCODE   = (53u << OPCODE_SHIFT |   00u << 1),
513
    STFSX_OPCODE   = (31u << OPCODE_SHIFT |  663u << 1),
514

515
    FSQRT_OPCODE   = (63u << OPCODE_SHIFT |   22u << 1),            // A-FORM
516
    FSQRTS_OPCODE  = (59u << OPCODE_SHIFT |   22u << 1),            // A-FORM
517

518
    // Vector instruction support for >= Power6
519
    // Vector Storage Access
520
    LVEBX_OPCODE   = (31u << OPCODE_SHIFT |    7u << 1),
521
    LVEHX_OPCODE   = (31u << OPCODE_SHIFT |   39u << 1),
522
    LVEWX_OPCODE   = (31u << OPCODE_SHIFT |   71u << 1),
523
    LVX_OPCODE     = (31u << OPCODE_SHIFT |  103u << 1),
524
    LVXL_OPCODE    = (31u << OPCODE_SHIFT |  359u << 1),
525
    STVEBX_OPCODE  = (31u << OPCODE_SHIFT |  135u << 1),
526
    STVEHX_OPCODE  = (31u << OPCODE_SHIFT |  167u << 1),
527
    STVEWX_OPCODE  = (31u << OPCODE_SHIFT |  199u << 1),
528
    STVX_OPCODE    = (31u << OPCODE_SHIFT |  231u << 1),
529
    STVXL_OPCODE   = (31u << OPCODE_SHIFT |  487u << 1),
530
    LVSL_OPCODE    = (31u << OPCODE_SHIFT |    6u << 1),
531
    LVSR_OPCODE    = (31u << OPCODE_SHIFT |   38u << 1),
532

533
    // Vector-Scalar (VSX) instruction support.
534
    LXV_OPCODE     = (61u << OPCODE_SHIFT |    1u     ),
535
    LXVL_OPCODE    = (31u << OPCODE_SHIFT |  269u << 1),
536
    STXV_OPCODE    = (61u << OPCODE_SHIFT |    5u     ),
537
    STXVL_OPCODE   = (31u << OPCODE_SHIFT |  397u << 1),
538
    LXVD2X_OPCODE  = (31u << OPCODE_SHIFT |  844u << 1),
539
    STXVD2X_OPCODE = (31u << OPCODE_SHIFT |  972u << 1),
540
    MTVSRD_OPCODE  = (31u << OPCODE_SHIFT |  179u << 1),
541
    MTVSRDD_OPCODE = (31u << OPCODE_SHIFT |  435u << 1),
542
    MTVSRWZ_OPCODE = (31u << OPCODE_SHIFT |  243u << 1),
543
    MFVSRD_OPCODE  = (31u << OPCODE_SHIFT |   51u << 1),
544
    MTVSRWA_OPCODE = (31u << OPCODE_SHIFT |  211u << 1),
545
    MFVSRWZ_OPCODE = (31u << OPCODE_SHIFT |  115u << 1),
546
    XXPERMDI_OPCODE= (60u << OPCODE_SHIFT |   10u << 3),
547
    XXMRGHW_OPCODE = (60u << OPCODE_SHIFT |   18u << 3),
548
    XXMRGLW_OPCODE = (60u << OPCODE_SHIFT |   50u << 3),
549
    XXSPLTW_OPCODE = (60u << OPCODE_SHIFT |  164u << 2),
550
    XXLAND_OPCODE  = (60u << OPCODE_SHIFT |  130u << 3),
551
    XXLOR_OPCODE   = (60u << OPCODE_SHIFT |  146u << 3),
552
    XXLXOR_OPCODE  = (60u << OPCODE_SHIFT |  154u << 3),
553
    XXLEQV_OPCODE  = (60u << OPCODE_SHIFT |  186u << 3),
554
    XVDIVSP_OPCODE = (60u << OPCODE_SHIFT |   88u << 3),
555
    XXBRD_OPCODE   = (60u << OPCODE_SHIFT |  475u << 2 | 23u << 16), // XX2-FORM
556
    XXBRW_OPCODE   = (60u << OPCODE_SHIFT |  475u << 2 | 15u << 16), // XX2-FORM
557
    XXPERM_OPCODE  = (60u << OPCODE_SHIFT |   26u << 3),
558
    XXSEL_OPCODE   = (60u << OPCODE_SHIFT |    3u << 4),
559
    XXSPLTIB_OPCODE= (60u << OPCODE_SHIFT |  360u << 1),
560
    XVDIVDP_OPCODE = (60u << OPCODE_SHIFT |  120u << 3),
561
    XVABSSP_OPCODE = (60u << OPCODE_SHIFT |  409u << 2),
562
    XVABSDP_OPCODE = (60u << OPCODE_SHIFT |  473u << 2),
563
    XVNEGSP_OPCODE = (60u << OPCODE_SHIFT |  441u << 2),
564
    XVNEGDP_OPCODE = (60u << OPCODE_SHIFT |  505u << 2),
565
    XVSQRTSP_OPCODE= (60u << OPCODE_SHIFT |  139u << 2),
566
    XVSQRTDP_OPCODE= (60u << OPCODE_SHIFT |  203u << 2),
567
    XSCVDPSPN_OPCODE=(60u << OPCODE_SHIFT |  267u << 2),
568
    XVADDDP_OPCODE = (60u << OPCODE_SHIFT |   96u << 3),
569
    XVSUBDP_OPCODE = (60u << OPCODE_SHIFT |  104u << 3),
570
    XVMULSP_OPCODE = (60u << OPCODE_SHIFT |   80u << 3),
571
    XVMULDP_OPCODE = (60u << OPCODE_SHIFT |  112u << 3),
572
    XVMADDASP_OPCODE=(60u << OPCODE_SHIFT |   65u << 3),
573
    XVMADDADP_OPCODE=(60u << OPCODE_SHIFT |   97u << 3),
574
    XVMSUBASP_OPCODE=(60u << OPCODE_SHIFT |   81u << 3),
575
    XVMSUBADP_OPCODE=(60u << OPCODE_SHIFT |  113u << 3),
576
    XVNMSUBASP_OPCODE=(60u<< OPCODE_SHIFT |  209u << 3),
577
    XVNMSUBADP_OPCODE=(60u<< OPCODE_SHIFT |  241u << 3),
578
    XVRDPI_OPCODE  = (60u << OPCODE_SHIFT |  201u << 2),
579
    XVRDPIM_OPCODE = (60u << OPCODE_SHIFT |  249u << 2),
580
    XVRDPIP_OPCODE = (60u << OPCODE_SHIFT |  233u << 2),
581

582
    // Deliver A Random Number (introduced with POWER9)
583
    DARN_OPCODE    = (31u << OPCODE_SHIFT |  755u << 1),
584

585
    // Vector Permute and Formatting
586
    VPKPX_OPCODE   = (4u  << OPCODE_SHIFT |  782u     ),
587
    VPKSHSS_OPCODE = (4u  << OPCODE_SHIFT |  398u     ),
588
    VPKSWSS_OPCODE = (4u  << OPCODE_SHIFT |  462u     ),
589
    VPKSHUS_OPCODE = (4u  << OPCODE_SHIFT |  270u     ),
590
    VPKSWUS_OPCODE = (4u  << OPCODE_SHIFT |  334u     ),
591
    VPKUHUM_OPCODE = (4u  << OPCODE_SHIFT |   14u     ),
592
    VPKUWUM_OPCODE = (4u  << OPCODE_SHIFT |   78u     ),
593
    VPKUHUS_OPCODE = (4u  << OPCODE_SHIFT |  142u     ),
594
    VPKUWUS_OPCODE = (4u  << OPCODE_SHIFT |  206u     ),
595
    VUPKHPX_OPCODE = (4u  << OPCODE_SHIFT |  846u     ),
596
    VUPKHSB_OPCODE = (4u  << OPCODE_SHIFT |  526u     ),
597
    VUPKHSH_OPCODE = (4u  << OPCODE_SHIFT |  590u     ),
598
    VUPKLPX_OPCODE = (4u  << OPCODE_SHIFT |  974u     ),
599
    VUPKLSB_OPCODE = (4u  << OPCODE_SHIFT |  654u     ),
600
    VUPKLSH_OPCODE = (4u  << OPCODE_SHIFT |  718u     ),
601

602
    VMRGHB_OPCODE  = (4u  << OPCODE_SHIFT |   12u     ),
603
    VMRGHW_OPCODE  = (4u  << OPCODE_SHIFT |  140u     ),
604
    VMRGHH_OPCODE  = (4u  << OPCODE_SHIFT |   76u     ),
605
    VMRGLB_OPCODE  = (4u  << OPCODE_SHIFT |  268u     ),
606
    VMRGLW_OPCODE  = (4u  << OPCODE_SHIFT |  396u     ),
607
    VMRGLH_OPCODE  = (4u  << OPCODE_SHIFT |  332u     ),
608

609
    VSPLT_OPCODE   = (4u  << OPCODE_SHIFT |  524u     ),
610
    VSPLTH_OPCODE  = (4u  << OPCODE_SHIFT |  588u     ),
611
    VSPLTW_OPCODE  = (4u  << OPCODE_SHIFT |  652u     ),
612
    VSPLTISB_OPCODE= (4u  << OPCODE_SHIFT |  780u     ),
613
    VSPLTISH_OPCODE= (4u  << OPCODE_SHIFT |  844u     ),
614
    VSPLTISW_OPCODE= (4u  << OPCODE_SHIFT |  908u     ),
615

616
    VPEXTD_OPCODE  = (4u  << OPCODE_SHIFT | 1421u     ),
617
    VPERM_OPCODE   = (4u  << OPCODE_SHIFT |   43u     ),
618
    VSEL_OPCODE    = (4u  << OPCODE_SHIFT |   42u     ),
619

620
    VSL_OPCODE     = (4u  << OPCODE_SHIFT |  452u     ),
621
    VSLDOI_OPCODE  = (4u  << OPCODE_SHIFT |   44u     ),
622
    VSLO_OPCODE    = (4u  << OPCODE_SHIFT | 1036u     ),
623
    VSR_OPCODE     = (4u  << OPCODE_SHIFT |  708u     ),
624
    VSRO_OPCODE    = (4u  << OPCODE_SHIFT | 1100u     ),
625

626
    // Vector Integer
627
    VADDCUW_OPCODE = (4u  << OPCODE_SHIFT |  384u     ),
628
    VADDSHS_OPCODE = (4u  << OPCODE_SHIFT |  832u     ),
629
    VADDSBS_OPCODE = (4u  << OPCODE_SHIFT |  768u     ),
630
    VADDSWS_OPCODE = (4u  << OPCODE_SHIFT |  896u     ),
631
    VADDUBM_OPCODE = (4u  << OPCODE_SHIFT |    0u     ),
632
    VADDUWM_OPCODE = (4u  << OPCODE_SHIFT |  128u     ),
633
    VADDUHM_OPCODE = (4u  << OPCODE_SHIFT |   64u     ),
634
    VADDUDM_OPCODE = (4u  << OPCODE_SHIFT |  192u     ),
635
    VADDUBS_OPCODE = (4u  << OPCODE_SHIFT |  512u     ),
636
    VADDUWS_OPCODE = (4u  << OPCODE_SHIFT |  640u     ),
637
    VADDUHS_OPCODE = (4u  << OPCODE_SHIFT |  576u     ),
638
    VADDFP_OPCODE  = (4u  << OPCODE_SHIFT |   10u     ),
639
    VSUBCUW_OPCODE = (4u  << OPCODE_SHIFT | 1408u     ),
640
    VSUBSHS_OPCODE = (4u  << OPCODE_SHIFT | 1856u     ),
641
    VSUBSBS_OPCODE = (4u  << OPCODE_SHIFT | 1792u     ),
642
    VSUBSWS_OPCODE = (4u  << OPCODE_SHIFT | 1920u     ),
643
    VSUBUBM_OPCODE = (4u  << OPCODE_SHIFT | 1024u     ),
644
    VSUBUWM_OPCODE = (4u  << OPCODE_SHIFT | 1152u     ),
645
    VSUBUHM_OPCODE = (4u  << OPCODE_SHIFT | 1088u     ),
646
    VSUBUDM_OPCODE = (4u  << OPCODE_SHIFT | 1216u     ),
647
    VSUBUBS_OPCODE = (4u  << OPCODE_SHIFT | 1536u     ),
648
    VSUBUWS_OPCODE = (4u  << OPCODE_SHIFT | 1664u     ),
649
    VSUBUHS_OPCODE = (4u  << OPCODE_SHIFT | 1600u     ),
650
    VSUBFP_OPCODE  = (4u  << OPCODE_SHIFT |   74u     ),
651

652
    VMULESB_OPCODE = (4u  << OPCODE_SHIFT |  776u     ),
653
    VMULEUB_OPCODE = (4u  << OPCODE_SHIFT |  520u     ),
654
    VMULESH_OPCODE = (4u  << OPCODE_SHIFT |  840u     ),
655
    VMULEUH_OPCODE = (4u  << OPCODE_SHIFT |  584u     ),
656
    VMULOSB_OPCODE = (4u  << OPCODE_SHIFT |  264u     ),
657
    VMULOUB_OPCODE = (4u  << OPCODE_SHIFT |    8u     ),
658
    VMULOSH_OPCODE = (4u  << OPCODE_SHIFT |  328u     ),
659
    VMULOSW_OPCODE = (4u  << OPCODE_SHIFT |  392u     ),
660
    VMULOUH_OPCODE = (4u  << OPCODE_SHIFT |   72u     ),
661
    VMULUWM_OPCODE = (4u  << OPCODE_SHIFT |  137u     ),
662
    VMHADDSHS_OPCODE=(4u  << OPCODE_SHIFT |   32u     ),
663
    VMHRADDSHS_OPCODE=(4u << OPCODE_SHIFT |   33u     ),
664
    VMLADDUHM_OPCODE=(4u  << OPCODE_SHIFT |   34u     ),
665
    VMSUBUHM_OPCODE= (4u  << OPCODE_SHIFT |   36u     ),
666
    VMSUMMBM_OPCODE= (4u  << OPCODE_SHIFT |   37u     ),
667
    VMSUMSHM_OPCODE= (4u  << OPCODE_SHIFT |   40u     ),
668
    VMSUMSHS_OPCODE= (4u  << OPCODE_SHIFT |   41u     ),
669
    VMSUMUHM_OPCODE= (4u  << OPCODE_SHIFT |   38u     ),
670
    VMSUMUHS_OPCODE= (4u  << OPCODE_SHIFT |   39u     ),
671
    VMADDFP_OPCODE = (4u  << OPCODE_SHIFT |   46u     ),
672

673
    VSUMSWS_OPCODE = (4u  << OPCODE_SHIFT | 1928u     ),
674
    VSUM2SWS_OPCODE= (4u  << OPCODE_SHIFT | 1672u     ),
675
    VSUM4SBS_OPCODE= (4u  << OPCODE_SHIFT | 1800u     ),
676
    VSUM4UBS_OPCODE= (4u  << OPCODE_SHIFT | 1544u     ),
677
    VSUM4SHS_OPCODE= (4u  << OPCODE_SHIFT | 1608u     ),
678

679
    VAVGSB_OPCODE  = (4u  << OPCODE_SHIFT | 1282u     ),
680
    VAVGSW_OPCODE  = (4u  << OPCODE_SHIFT | 1410u     ),
681
    VAVGSH_OPCODE  = (4u  << OPCODE_SHIFT | 1346u     ),
682
    VAVGUB_OPCODE  = (4u  << OPCODE_SHIFT | 1026u     ),
683
    VAVGUW_OPCODE  = (4u  << OPCODE_SHIFT | 1154u     ),
684
    VAVGUH_OPCODE  = (4u  << OPCODE_SHIFT | 1090u     ),
685

686
    VMAXSB_OPCODE  = (4u  << OPCODE_SHIFT |  258u     ),
687
    VMAXSW_OPCODE  = (4u  << OPCODE_SHIFT |  386u     ),
688
    VMAXSH_OPCODE  = (4u  << OPCODE_SHIFT |  322u     ),
689
    VMAXUB_OPCODE  = (4u  << OPCODE_SHIFT |    2u     ),
690
    VMAXUW_OPCODE  = (4u  << OPCODE_SHIFT |  130u     ),
691
    VMAXUH_OPCODE  = (4u  << OPCODE_SHIFT |   66u     ),
692
    VMINSB_OPCODE  = (4u  << OPCODE_SHIFT |  770u     ),
693
    VMINSW_OPCODE  = (4u  << OPCODE_SHIFT |  898u     ),
694
    VMINSH_OPCODE  = (4u  << OPCODE_SHIFT |  834u     ),
695
    VMINUB_OPCODE  = (4u  << OPCODE_SHIFT |  514u     ),
696
    VMINUW_OPCODE  = (4u  << OPCODE_SHIFT |  642u     ),
697
    VMINUH_OPCODE  = (4u  << OPCODE_SHIFT |  578u     ),
698

699
    VCMPEQUB_OPCODE= (4u  << OPCODE_SHIFT |    6u     ),
700
    VCMPEQUH_OPCODE= (4u  << OPCODE_SHIFT |   70u     ),
701
    VCMPEQUW_OPCODE= (4u  << OPCODE_SHIFT |  134u     ),
702
    VCMPGTSH_OPCODE= (4u  << OPCODE_SHIFT |  838u     ),
703
    VCMPGTSB_OPCODE= (4u  << OPCODE_SHIFT |  774u     ),
704
    VCMPGTSW_OPCODE= (4u  << OPCODE_SHIFT |  902u     ),
705
    VCMPGTUB_OPCODE= (4u  << OPCODE_SHIFT |  518u     ),
706
    VCMPGTUH_OPCODE= (4u  << OPCODE_SHIFT |  582u     ),
707
    VCMPGTUW_OPCODE= (4u  << OPCODE_SHIFT |  646u     ),
708

709
    VAND_OPCODE    = (4u  << OPCODE_SHIFT | 1028u     ),
710
    VANDC_OPCODE   = (4u  << OPCODE_SHIFT | 1092u     ),
711
    VNOR_OPCODE    = (4u  << OPCODE_SHIFT | 1284u     ),
712
    VOR_OPCODE     = (4u  << OPCODE_SHIFT | 1156u     ),
713
    VXOR_OPCODE    = (4u  << OPCODE_SHIFT | 1220u     ),
714
    VRLD_OPCODE    = (4u  << OPCODE_SHIFT |  196u     ),
715
    VRLB_OPCODE    = (4u  << OPCODE_SHIFT |    4u     ),
716
    VRLW_OPCODE    = (4u  << OPCODE_SHIFT |  132u     ),
717
    VRLH_OPCODE    = (4u  << OPCODE_SHIFT |   68u     ),
718
    VSLB_OPCODE    = (4u  << OPCODE_SHIFT |  260u     ),
719
    VSKW_OPCODE    = (4u  << OPCODE_SHIFT |  388u     ),
720
    VSLH_OPCODE    = (4u  << OPCODE_SHIFT |  324u     ),
721
    VSRB_OPCODE    = (4u  << OPCODE_SHIFT |  516u     ),
722
    VSRW_OPCODE    = (4u  << OPCODE_SHIFT |  644u     ),
723
    VSRH_OPCODE    = (4u  << OPCODE_SHIFT |  580u     ),
724
    VSRAB_OPCODE   = (4u  << OPCODE_SHIFT |  772u     ),
725
    VSRAW_OPCODE   = (4u  << OPCODE_SHIFT |  900u     ),
726
    VSRAH_OPCODE   = (4u  << OPCODE_SHIFT |  836u     ),
727
    VPOPCNTW_OPCODE= (4u  << OPCODE_SHIFT | 1923u     ),
728

729
    // Vector Floating-Point
730
    // not implemented yet
731

732
    // Vector Status and Control
733
    MTVSCR_OPCODE  = (4u  << OPCODE_SHIFT | 1604u     ),
734
    MFVSCR_OPCODE  = (4u  << OPCODE_SHIFT | 1540u     ),
735

736
    // AES (introduced with Power 8)
737
    VCIPHER_OPCODE      = (4u  << OPCODE_SHIFT | 1288u),
738
    VCIPHERLAST_OPCODE  = (4u  << OPCODE_SHIFT | 1289u),
739
    VNCIPHER_OPCODE     = (4u  << OPCODE_SHIFT | 1352u),
740
    VNCIPHERLAST_OPCODE = (4u  << OPCODE_SHIFT | 1353u),
741
    VSBOX_OPCODE        = (4u  << OPCODE_SHIFT | 1480u),
742

743
    // SHA (introduced with Power 8)
744
    VSHASIGMAD_OPCODE   = (4u  << OPCODE_SHIFT | 1730u),
745
    VSHASIGMAW_OPCODE   = (4u  << OPCODE_SHIFT | 1666u),
746

747
    // Vector Binary Polynomial Multiplication (introduced with Power 8)
748
    VPMSUMB_OPCODE      = (4u  << OPCODE_SHIFT | 1032u),
749
    VPMSUMD_OPCODE      = (4u  << OPCODE_SHIFT | 1224u),
750
    VPMSUMH_OPCODE      = (4u  << OPCODE_SHIFT | 1096u),
751
    VPMSUMW_OPCODE      = (4u  << OPCODE_SHIFT | 1160u),
752

753
    // Vector Permute and Xor (introduced with Power 8)
754
    VPERMXOR_OPCODE     = (4u  << OPCODE_SHIFT |   45u),
755

756
    // Transactional Memory instructions (introduced with Power 8)
757
    TBEGIN_OPCODE    = (31u << OPCODE_SHIFT |  654u << 1),
758
    TEND_OPCODE      = (31u << OPCODE_SHIFT |  686u << 1),
759
    TABORT_OPCODE    = (31u << OPCODE_SHIFT |  910u << 1),
760
    TABORTWC_OPCODE  = (31u << OPCODE_SHIFT |  782u << 1),
761
    TABORTWCI_OPCODE = (31u << OPCODE_SHIFT |  846u << 1),
762
    TABORTDC_OPCODE  = (31u << OPCODE_SHIFT |  814u << 1),
763
    TABORTDCI_OPCODE = (31u << OPCODE_SHIFT |  878u << 1),
764
    TSR_OPCODE       = (31u << OPCODE_SHIFT |  750u << 1),
765
    TCHECK_OPCODE    = (31u << OPCODE_SHIFT |  718u << 1),
766

767
    // Icache and dcache related instructions
768
    DCBA_OPCODE    = (31u << OPCODE_SHIFT |  758u << 1),
769
    DCBZ_OPCODE    = (31u << OPCODE_SHIFT | 1014u << 1),
770
    DCBST_OPCODE   = (31u << OPCODE_SHIFT |   54u << 1),
771
    DCBF_OPCODE    = (31u << OPCODE_SHIFT |   86u << 1),
772

773
    DCBT_OPCODE    = (31u << OPCODE_SHIFT |  278u << 1),
774
    DCBTST_OPCODE  = (31u << OPCODE_SHIFT |  246u << 1),
775
    ICBI_OPCODE    = (31u << OPCODE_SHIFT |  982u << 1),
776

777
    // Instruction synchronization
778
    ISYNC_OPCODE   = (19u << OPCODE_SHIFT |  150u << 1),
779
    // Memory barriers
780
    SYNC_OPCODE    = (31u << OPCODE_SHIFT |  598u << 1),
781
    EIEIO_OPCODE   = (31u << OPCODE_SHIFT |  854u << 1),
782

783
    // Wait instructions for polling.
784
    WAIT_OPCODE    = (31u << OPCODE_SHIFT |   62u << 1),
785

786
    // Trap instructions
787
    TDI_OPCODE     = (2u  << OPCODE_SHIFT),
788
    TWI_OPCODE     = (3u  << OPCODE_SHIFT),
789
    TD_OPCODE      = (31u << OPCODE_SHIFT |   68u << 1),
790
    TW_OPCODE      = (31u << OPCODE_SHIFT |    4u << 1),
791

792
    // Atomics.
793
    LBARX_OPCODE   = (31u << OPCODE_SHIFT |   52u << 1),
794
    LHARX_OPCODE   = (31u << OPCODE_SHIFT |  116u << 1),
795
    LWARX_OPCODE   = (31u << OPCODE_SHIFT |   20u << 1),
796
    LDARX_OPCODE   = (31u << OPCODE_SHIFT |   84u << 1),
797
    LQARX_OPCODE   = (31u << OPCODE_SHIFT |  276u << 1),
798
    STBCX_OPCODE   = (31u << OPCODE_SHIFT |  694u << 1),
799
    STHCX_OPCODE   = (31u << OPCODE_SHIFT |  726u << 1),
800
    STWCX_OPCODE   = (31u << OPCODE_SHIFT |  150u << 1),
801
    STDCX_OPCODE   = (31u << OPCODE_SHIFT |  214u << 1),
802
    STQCX_OPCODE   = (31u << OPCODE_SHIFT |  182u << 1)
803

804
  };
805

806
  enum opcdeos_mask {
807
    // Mask for prefix primary opcode field
808
    PREFIX_OPCODE_MASK        = (63u << OPCODE_SHIFT),
809
    // Mask for prefix opcode and type fields
810
    PREFIX_OPCODE_TYPE_MASK   = (63u << OPCODE_SHIFT) | (3u << PRE_TYPE_SHIFT),
811
    // Masks for type 00/10 and type 01/11, including opcode, type, and st fieds
812
    PREFIX_OPCODE_TYPEx0_MASK = PREFIX_OPCODE_TYPE_MASK | ( 1u << PRE_ST1_SHIFT),
813
    PREFIX_OPCODE_TYPEx1_MASK = PREFIX_OPCODE_TYPE_MASK | (15u << PRE_ST4_SHIFT),
814

815
    // Masks for each instructions
816
    PADDI_PREFIX_OPCODE_MASK  = PREFIX_OPCODE_TYPEx0_MASK,
817
    PADDI_SUFFIX_OPCODE_MASK  = ADDI_OPCODE_MASK,
818
  };
819

820
  enum opcdeos {
821
    PREFIX_PRIMARY_OPCODE = (1u << OPCODE_SHIFT),
822

823
    // Prefixed addi/li
824
    PADDI_PREFIX_OPCODE   = PREFIX_PRIMARY_OPCODE | (2u << PRE_TYPE_SHIFT),
825
    PADDI_SUFFIX_OPCODE   = ADDI_OPCODE,
826
  };
827

828
  // Trap instructions TO bits
829
  enum trap_to_bits {
830
    // single bits
831
    traptoLessThanSigned      = 1 << 4, // 0, left end
832
    traptoGreaterThanSigned   = 1 << 3,
833
    traptoEqual               = 1 << 2,
834
    traptoLessThanUnsigned    = 1 << 1,
835
    traptoGreaterThanUnsigned = 1 << 0, // 4, right end
836

837
    // compound ones
838
    traptoUnconditional       = (traptoLessThanSigned |
839
                                 traptoGreaterThanSigned |
840
                                 traptoEqual |
841
                                 traptoLessThanUnsigned |
842
                                 traptoGreaterThanUnsigned)
843
  };
844

845
  // Branch hints BH field
846
  enum branch_hint_bh {
847
    // bclr cases:
848
    bhintbhBCLRisReturn            = 0,
849
    bhintbhBCLRisNotReturnButSame  = 1,
850
    bhintbhBCLRisNotPredictable    = 3,
851

852
    // bcctr cases:
853
    bhintbhBCCTRisNotReturnButSame = 0,
854
    bhintbhBCCTRisNotPredictable   = 3
855
  };
856

857
  // Branch prediction hints AT field
858
  enum branch_hint_at {
859
    bhintatNoHint     = 0,  // at=00
860
    bhintatIsNotTaken = 2,  // at=10
861
    bhintatIsTaken    = 3   // at=11
862
  };
863

864
  // Branch prediction hints
865
  enum branch_hint_concept {
866
    // Use the same encoding as branch_hint_at to simply code.
867
    bhintNoHint       = bhintatNoHint,
868
    bhintIsNotTaken   = bhintatIsNotTaken,
869
    bhintIsTaken      = bhintatIsTaken
870
  };
871

872
  // Used in BO field of branch instruction.
873
  enum branch_condition {
874
    bcondCRbiIs0      =  4, // bo=001at
875
    bcondCRbiIs1      = 12, // bo=011at
876
    bcondAlways       = 20  // bo=10100
877
  };
878

879
  // Branch condition with combined prediction hints.
880
  enum branch_condition_with_hint {
881
    bcondCRbiIs0_bhintNoHint     = bcondCRbiIs0 | bhintatNoHint,
882
    bcondCRbiIs0_bhintIsNotTaken = bcondCRbiIs0 | bhintatIsNotTaken,
883
    bcondCRbiIs0_bhintIsTaken    = bcondCRbiIs0 | bhintatIsTaken,
884
    bcondCRbiIs1_bhintNoHint     = bcondCRbiIs1 | bhintatNoHint,
885
    bcondCRbiIs1_bhintIsNotTaken = bcondCRbiIs1 | bhintatIsNotTaken,
886
    bcondCRbiIs1_bhintIsTaken    = bcondCRbiIs1 | bhintatIsTaken,
887
  };
888

889
  // Elemental Memory Barriers (>=Power 8)
890
  enum Elemental_Membar_mask_bits {
891
    StoreStore = 1 << 0,
892
    StoreLoad  = 1 << 1,
893
    LoadStore  = 1 << 2,
894
    LoadLoad   = 1 << 3
895
  };
896

897
  // Branch prediction hints.
898
  inline static int add_bhint_to_boint(const int bhint, const int boint) {
899
    switch (boint) {
900
      case bcondCRbiIs0:
901
      case bcondCRbiIs1:
902
        // branch_hint and branch_hint_at have same encodings
903
        assert(   (int)bhintNoHint     == (int)bhintatNoHint
904
               && (int)bhintIsNotTaken == (int)bhintatIsNotTaken
905
               && (int)bhintIsTaken    == (int)bhintatIsTaken,
906
               "wrong encodings");
907
        assert((bhint & 0x03) == bhint, "wrong encodings");
908
        return (boint & ~0x03) | bhint;
909
      case bcondAlways:
910
        // no branch_hint
911
        return boint;
912
      default:
913
        ShouldNotReachHere();
914
        return 0;
915
    }
916
  }
917

918
  // Extract bcond from boint.
919
  inline static int inv_boint_bcond(const int boint) {
920
    int r_bcond = boint & ~0x03;
921
    assert(r_bcond == bcondCRbiIs0 ||
922
           r_bcond == bcondCRbiIs1 ||
923
           r_bcond == bcondAlways,
924
           "bad branch condition");
925
    return r_bcond;
926
  }
927

928
  // Extract bhint from boint.
929
  inline static int inv_boint_bhint(const int boint) {
930
    int r_bhint = boint & 0x03;
931
    assert(r_bhint == bhintatNoHint ||
932
           r_bhint == bhintatIsNotTaken ||
933
           r_bhint == bhintatIsTaken,
934
           "bad branch hint");
935
    return r_bhint;
936
  }
937

938
  // Calculate opposite of given bcond.
939
  inline static int opposite_bcond(const int bcond) {
940
    switch (bcond) {
941
      case bcondCRbiIs0:
942
        return bcondCRbiIs1;
943
      case bcondCRbiIs1:
944
        return bcondCRbiIs0;
945
      default:
946
        ShouldNotReachHere();
947
        return 0;
948
    }
949
  }
950

951
  // Calculate opposite of given bhint.
952
  inline static int opposite_bhint(const int bhint) {
953
    switch (bhint) {
954
      case bhintatNoHint:
955
        return bhintatNoHint;
956
      case bhintatIsNotTaken:
957
        return bhintatIsTaken;
958
      case bhintatIsTaken:
959
        return bhintatIsNotTaken;
960
      default:
961
        ShouldNotReachHere();
962
        return 0;
963
    }
964
  }
965

966
  // PPC branch instructions
967
  enum ppcops {
968
    b_op    = 18,
969
    bc_op   = 16,
970
    bcr_op  = 19
971
  };
972

973
  enum Condition {
974
    negative         = 0,
975
    less             = 0,
976
    positive         = 1,
977
    greater          = 1,
978
    zero             = 2,
979
    equal            = 2,
980
    summary_overflow = 3,
981
  };
982

983
 public:
984
  // Helper functions for groups of instructions
985

986
  enum Predict { pt = 1, pn = 0 }; // pt = predict taken
987

988
  //---<  calculate length of instruction  >---
989
  // With PPC64 being a RISC architecture, this always is BytesPerInstWord
990
  // instruction must start at passed address
991
  static unsigned int instr_len(unsigned char *instr) { return BytesPerInstWord; }
992

993
  //---<  longest instructions  >---
994
  static unsigned int instr_maxlen() { return BytesPerInstWord; }
995

996
  // Test if x is within signed immediate range for nbits.
997
  static bool is_simm(int x, unsigned int nbits) {
998
    assert(0 < nbits && nbits < 32, "out of bounds");
999
    const int   min      = -(((int)1) << nbits-1);
1000
    const int   maxplus1 =  (((int)1) << nbits-1);
1001
    return min <= x && x < maxplus1;
1002
  }
1003

1004
  static bool is_simm(jlong x, unsigned int nbits) {
1005
    assert(0 < nbits && nbits < 64, "out of bounds");
1006
    const jlong min      = -(((jlong)1) << nbits-1);
1007
    const jlong maxplus1 =  (((jlong)1) << nbits-1);
1008
    return min <= x && x < maxplus1;
1009
  }
1010

1011
  // Test if x is within unsigned immediate range for nbits.
1012
  static bool is_uimm(int x, unsigned int nbits) {
1013
    assert(0 < nbits && nbits < 32, "out of bounds");
1014
    const unsigned int maxplus1 = (((unsigned int)1) << nbits);
1015
    return (unsigned int)x < maxplus1;
1016
  }
1017

1018
  static bool is_uimm(jlong x, unsigned int nbits) {
1019
    assert(0 < nbits && nbits < 64, "out of bounds");
1020
    const julong maxplus1 = (((julong)1) << nbits);
1021
    return (julong)x < maxplus1;
1022
  }
1023

1024
 protected:
1025
  // helpers
1026

1027
  // X is supposed to fit in a field "nbits" wide
1028
  // and be sign-extended. Check the range.
1029
  static void assert_signed_range(intptr_t x, int nbits) {
1030
    assert(nbits == 32 || (-(1 << nbits-1) <= x && x < (1 << nbits-1)),
1031
           "value out of range");
1032
  }
1033

1034
  static void assert_signed_word_disp_range(intptr_t x, int nbits) {
1035
    assert((x & 3) == 0, "not word aligned");
1036
    assert_signed_range(x, nbits + 2);
1037
  }
1038

1039
  static void assert_unsigned_const(int x, int nbits) {
1040
    assert(juint(x) < juint(1 << nbits), "unsigned constant out of range");
1041
  }
1042

1043
  static int fmask(juint hi_bit, juint lo_bit) {
1044
    assert(hi_bit >= lo_bit && hi_bit < 32, "bad bits");
1045
    return (1 << ( hi_bit-lo_bit + 1 )) - 1;
1046
  }
1047

1048
  // inverse of u_field
1049
  static int inv_u_field(int x, int hi_bit, int lo_bit) {
1050
    juint r = juint(x) >> lo_bit;
1051
    r &= fmask(hi_bit, lo_bit);
1052
    return int(r);
1053
  }
1054

1055
  // signed version: extract from field and sign-extend
1056
  static int inv_s_field_ppc(int x, int hi_bit, int lo_bit) {
1057
    x = x << (31-hi_bit);
1058
    x = x >> (31-hi_bit+lo_bit);
1059
    return x;
1060
  }
1061

1062
  static int u_field(int x, int hi_bit, int lo_bit) {
1063
    assert((x & ~fmask(hi_bit, lo_bit)) == 0, "value out of range");
1064
    int r = x << lo_bit;
1065
    assert(inv_u_field(r, hi_bit, lo_bit) == x, "just checking");
1066
    return r;
1067
  }
1068

1069
  // Same as u_field for signed values
1070
  static int s_field(int x, int hi_bit, int lo_bit) {
1071
    int nbits = hi_bit - lo_bit + 1;
1072
    assert(nbits == 32 || (-(1 << nbits-1) <= x && x < (1 << nbits-1)),
1073
      "value out of range");
1074
    x &= fmask(hi_bit, lo_bit);
1075
    int r = x << lo_bit;
1076
    return r;
1077
  }
1078

1079
  // inv_op for ppc instructions
1080
  static int inv_op_ppc(int x) { return inv_u_field(x, 31, 26); }
1081

1082
  // Determine target address from li, bd field of branch instruction.
1083
  static intptr_t inv_li_field(int x) {
1084
    intptr_t r = inv_s_field_ppc(x, 25, 2);
1085
    r = (r << 2);
1086
    return r;
1087
  }
1088
  static intptr_t inv_bd_field(int x, intptr_t pos) {
1089
    intptr_t r = inv_s_field_ppc(x, 15, 2);
1090
    r = (r << 2) + pos;
1091
    return r;
1092
  }
1093

1094
  #define inv_opp_u_field(x, hi_bit, lo_bit) inv_u_field(x, 31-(lo_bit), 31-(hi_bit))
1095
  #define inv_opp_s_field(x, hi_bit, lo_bit) inv_s_field_ppc(x, 31-(lo_bit), 31-(hi_bit))
1096
  // Extract instruction fields from instruction words.
1097
 public:
1098
  static int inv_ra_field(int x)  { return inv_opp_u_field(x, 15, 11); }
1099
  static int inv_rb_field(int x)  { return inv_opp_u_field(x, 20, 16); }
1100
  static int inv_rt_field(int x)  { return inv_opp_u_field(x, 10,  6); }
1101
  static int inv_rta_field(int x) { return inv_opp_u_field(x, 15, 11); }
1102
  static int inv_rs_field(int x)  { return inv_opp_u_field(x, 10,  6); }
1103
  // Ds uses opp_s_field(x, 31, 16), but lowest 2 bits must be 0.
1104
  // Inv_ds_field uses range (x, 29, 16) but shifts by 2 to ensure that lowest bits are 0.
1105
  static int inv_ds_field(int x)  { return inv_opp_s_field(x, 29, 16) << 2; }
1106
  static int inv_d1_field(int x)  { return inv_opp_s_field(x, 31, 16); }
1107
  static int inv_si_field(int x)  { return inv_opp_s_field(x, 31, 16); }
1108
  static int inv_to_field(int x)  { return inv_opp_u_field(x, 10, 6);  }
1109
  static int inv_lk_field(int x)  { return inv_opp_u_field(x, 31, 31); }
1110
  static int inv_bo_field(int x)  { return inv_opp_u_field(x, 10,  6); }
1111
  static int inv_bi_field(int x)  { return inv_opp_u_field(x, 15, 11); }
1112

1113
  // For extended opcodes (prefixed instructions) introduced with Power 10
1114
  static long inv_r_eo(   int x)  { return  inv_opp_u_field(x, 11, 11); }
1115
  static long inv_type(   int x)  { return  inv_opp_u_field(x,  7,  6); }
1116
  static long inv_st_x0(  int x)  { return  inv_opp_u_field(x,  8,  8); }
1117
  static long inv_st_x1(  int x)  { return  inv_opp_u_field(x, 11,  8); }
1118

1119
  //  - 8LS:D/MLS:D Formats
1120
  static long inv_d0_eo( long x)  { return  inv_opp_u_field(x, 31, 14); }
1121

1122
  //  - 8RR:XX4/8RR:D Formats
1123
  static long inv_imm0_eo(int x)  { return  inv_opp_u_field(x, 31, 16); }
1124
  static long inv_uimm_eo(int x)  { return  inv_opp_u_field(x, 31, 29); }
1125
  static long inv_imm_eo( int x)  { return  inv_opp_u_field(x, 31, 24); }
1126

1127
  #define opp_u_field(x, hi_bit, lo_bit) u_field(x, 31-(lo_bit), 31-(hi_bit))
1128
  #define opp_s_field(x, hi_bit, lo_bit) s_field(x, 31-(lo_bit), 31-(hi_bit))
1129

1130
  // instruction fields
1131
  static int aa(       int         x)  { return  opp_u_field(x,             30, 30); }
1132
  static int ba(       int         x)  { return  opp_u_field(x,             15, 11); }
1133
  static int bb(       int         x)  { return  opp_u_field(x,             20, 16); }
1134
  static int bc(       int         x)  { return  opp_u_field(x,             25, 21); }
1135
  static int bd(       int         x)  { return  opp_s_field(x,             29, 16); }
1136
  static int bf( ConditionRegister cr) { return  bf(cr->encoding()); }
1137
  static int bf(       int         x)  { return  opp_u_field(x,              8,  6); }
1138
  static int bfa(ConditionRegister cr) { return  bfa(cr->encoding()); }
1139
  static int bfa(      int         x)  { return  opp_u_field(x,             13, 11); }
1140
  static int bh(       int         x)  { return  opp_u_field(x,             20, 19); }
1141
  static int bi(       int         x)  { return  opp_u_field(x,             15, 11); }
1142
  static int bi0(ConditionRegister cr, Condition c) { return (cr->encoding() << 2) | c; }
1143
  static int bo(       int         x)  { return  opp_u_field(x,             10,  6); }
1144
  static int bt(       int         x)  { return  opp_u_field(x,             10,  6); }
1145
  static int d1(       int         x)  { return  opp_s_field(x,             31, 16); }
1146
  static int ds(       int         x)  { assert((x & 0x3) == 0, "unaligned offset"); return opp_s_field(x, 31, 16); }
1147
  static int eh(       int         x)  { return  opp_u_field(x,             31, 31); }
1148
  static int flm(      int         x)  { return  opp_u_field(x,             14,  7); }
1149
  static int fra(    FloatRegister r)  { return  fra(r->encoding());}
1150
  static int frb(    FloatRegister r)  { return  frb(r->encoding());}
1151
  static int frc(    FloatRegister r)  { return  frc(r->encoding());}
1152
  static int frs(    FloatRegister r)  { return  frs(r->encoding());}
1153
  static int frt(    FloatRegister r)  { return  frt(r->encoding());}
1154
  static int fra(      int         x)  { return  opp_u_field(x,             15, 11); }
1155
  static int frb(      int         x)  { return  opp_u_field(x,             20, 16); }
1156
  static int frc(      int         x)  { return  opp_u_field(x,             25, 21); }
1157
  static int frs(      int         x)  { return  opp_u_field(x,             10,  6); }
1158
  static int frt(      int         x)  { return  opp_u_field(x,             10,  6); }
1159
  static int fxm(      int         x)  { return  opp_u_field(x,             19, 12); }
1160
  static int imm8(     int         x)  { return  opp_u_field(uimm(x, 8),    20, 13); }
1161
  static int l10(      int         x)  { assert(x == 0 || x == 1,  "must be 0 or 1"); return opp_u_field(x, 10, 10); }
1162
  static int l14(      int         x)  { return  opp_u_field(x,             15, 14); }
1163
  static int l15(      int         x)  { return  opp_u_field(x,             15, 15); }
1164
  static int l910(     int         x)  { return  opp_u_field(x,             10,  9); }
1165
  static int e1215(    int         x)  { return  opp_u_field(x,             15, 12); }
1166
  static int lev(      int         x)  { return  opp_u_field(x,             26, 20); }
1167
  static int li(       int         x)  { return  opp_s_field(x,             29,  6); }
1168
  static int lk(       int         x)  { return  opp_u_field(x,             31, 31); }
1169
  static int mb2125(   int         x)  { return  opp_u_field(x,             25, 21); }
1170
  static int me2630(   int         x)  { return  opp_u_field(x,             30, 26); }
1171
  static int mb2126(   int         x)  { return  opp_u_field(((x & 0x1f) << 1) | ((x & 0x20) >> 5), 26, 21); }
1172
  static int me2126(   int         x)  { return  mb2126(x); }
1173
  static int nb(       int         x)  { return  opp_u_field(x,             20, 16); }
1174
  //static int opcd(   int         x)  { return  opp_u_field(x,              5,  0); } // is contained in our opcodes
1175
  static int oe(       int         x)  { return  opp_u_field(x,             21, 21); }
1176
  static int ra(       Register    r)  { return  ra(r->encoding()); }
1177
  static int ra(       int         x)  { return  opp_u_field(x,             15, 11); }
1178
  static int rb(       Register    r)  { return  rb(r->encoding()); }
1179
  static int rb(       int         x)  { return  opp_u_field(x,             20, 16); }
1180
  static int rc(       int         x)  { return  opp_u_field(x,             31, 31); }
1181
  static int rs(       Register    r)  { return  rs(r->encoding()); }
1182
  static int rs(       int         x)  { return  opp_u_field(x,             10,  6); }
1183
  // we don't want to use R0 in memory accesses, because it has value `0' then
1184
  static int ra0mem(   Register    r)  { assert(r != R0, "cannot use register R0 in memory access"); return ra(r); }
1185
  static int ra0mem(   int         x)  { assert(x != 0,  "cannot use register 0 in memory access");  return ra(x); }
1186

1187
  // register r is target
1188
  static int rt(       Register    r)  { return rs(r); }
1189
  static int rt(       int         x)  { return rs(x); }
1190
  static int rta(      Register    r)  { return ra(r); }
1191
  static int rta0mem(  Register    r)  { rta(r); return ra0mem(r); }
1192

1193
  static int sh1620(   int         x)  { return  opp_u_field(x,             20, 16); }
1194
  static int sh30(     int         x)  { return  opp_u_field(x,             30, 30); }
1195
  static int sh162030( int         x)  { return  sh1620(x & 0x1f) | sh30((x & 0x20) >> 5); }
1196
  static int si(       int         x)  { return  opp_s_field(x,             31, 16); }
1197
  static int spr(      int         x)  { return  opp_u_field(x,             20, 11); }
1198
  static int sr(       int         x)  { return  opp_u_field(x,             15, 12); }
1199
  static int tbr(      int         x)  { return  opp_u_field(x,             20, 11); }
1200
  static int th(       int         x)  { return  opp_u_field(x,             10,  7); }
1201
  static int thct(     int         x)  { assert((x&8) == 0, "must be valid cache specification");  return th(x); }
1202
  static int thds(     int         x)  { assert((x&8) == 8, "must be valid stream specification"); return th(x); }
1203
  static int to(       int         x)  { return  opp_u_field(x,             10,  6); }
1204
  static int u(        int         x)  { return  opp_u_field(x,             19, 16); }
1205
  static int ui(       int         x)  { return  opp_u_field(x,             31, 16); }
1206

1207
  // Support vector instructions for >= Power6.
1208
  static int vra(      int         x)  { return  opp_u_field(x,             15, 11); }
1209
  static int vrb(      int         x)  { return  opp_u_field(x,             20, 16); }
1210
  static int vrc(      int         x)  { return  opp_u_field(x,             25, 21); }
1211
  static int vrs(      int         x)  { return  opp_u_field(x,             10,  6); }
1212
  static int vrt(      int         x)  { return  opp_u_field(x,             10,  6); }
1213

1214
  static int vra(   VectorRegister r)  { return  vra(r->encoding());}
1215
  static int vrb(   VectorRegister r)  { return  vrb(r->encoding());}
1216
  static int vrc(   VectorRegister r)  { return  vrc(r->encoding());}
1217
  static int vrs(   VectorRegister r)  { return  vrs(r->encoding());}
1218
  static int vrt(   VectorRegister r)  { return  vrt(r->encoding());}
1219

1220
  // Only used on SHA sigma instructions (VX-form)
1221
  static int vst(      int         x)  { return  opp_u_field(x,             16, 16); }
1222
  static int vsix(     int         x)  { return  opp_u_field(x,             20, 17); }
1223

1224
  // Support Vector-Scalar (VSX) instructions.
1225
  static int vsra(      int         x)  { return  opp_u_field(x & 0x1F,     15, 11) | opp_u_field((x & 0x20) >> 5, 29, 29); }
1226
  static int vsrb(      int         x)  { return  opp_u_field(x & 0x1F,     20, 16) | opp_u_field((x & 0x20) >> 5, 30, 30); }
1227
  static int vsrc(      int         x)  { return  opp_u_field(x & 0x1F,     25, 21) | opp_u_field((x & 0x20) >> 5, 28, 28); }
1228
  static int vsrs(      int         x)  { return  opp_u_field(x & 0x1F,     10,  6) | opp_u_field((x & 0x20) >> 5, 31, 31); }
1229
  static int vsrt(      int         x)  { return  vsrs(x); }
1230
  static int vsdm(      int         x)  { return  opp_u_field(x,            23, 22); }
1231
  static int vsrs_dq(   int         x)  { return  opp_u_field(x & 0x1F,     10,  6) | opp_u_field((x & 0x20) >> 5, 28, 28); }
1232
  static int vsrt_dq(   int         x)  { return  vsrs_dq(x); }
1233

1234
  static int vsra(   VectorSRegister r)  { return  vsra(r->encoding());}
1235
  static int vsrb(   VectorSRegister r)  { return  vsrb(r->encoding());}
1236
  static int vsrc(   VectorSRegister r)  { return  vsrc(r->encoding());}
1237
  static int vsrs(   VectorSRegister r)  { return  vsrs(r->encoding());}
1238
  static int vsrt(   VectorSRegister r)  { return  vsrt(r->encoding());}
1239
  static int vsrs_dq(VectorSRegister r)  { return  vsrs_dq(r->encoding());}
1240
  static int vsrt_dq(VectorSRegister r)  { return  vsrt_dq(r->encoding());}
1241

1242
  static int vsplt_uim( int        x)  { return  opp_u_field(x,             15, 12); } // for vsplt* instructions
1243
  static int vsplti_sim(int        x)  { return  opp_u_field(x,             15, 11); } // for vsplti* instructions
1244
  static int vsldoi_shb(int        x)  { return  opp_u_field(x,             25, 22); } // for vsldoi instruction
1245
  static int vcmp_rc(   int        x)  { return  opp_u_field(x,             21, 21); } // for vcmp* instructions
1246
  static int xxsplt_uim(int        x)  { return  opp_u_field(x,             15, 14); } // for xxsplt* instructions
1247

1248
  // For extended opcodes (prefixed instructions) introduced with Power 10
1249
  static long r_eo(     int        x)  { return  opp_u_field(x,             11, 11); }
1250
  static long type(     int        x)  { return  opp_u_field(x,              7,  6); }
1251
  static long st_x0(    int        x)  { return  opp_u_field(x,              8,  8); }
1252
  static long st_x1(    int        x)  { return  opp_u_field(x,             11,  8); }
1253

1254
  //  - 8LS:D/MLS:D Formats
1255
  static long d0_eo(    long       x)  { return  opp_u_field((x >> 16) & 0x3FFFF, 31, 14); }
1256
  static long d1_eo(    long       x)  { return  opp_u_field(x & 0xFFFF,    31, 16); }
1257
  static long s0_eo(    long       x)  { return  d0_eo(x); }
1258
  static long s1_eo(    long       x)  { return  d1_eo(x); }
1259

1260
  //  - 8RR:XX4/8RR:D Formats
1261
  static long imm0_eo(  int        x)  { return  opp_u_field(x >> 16,       31, 16); }
1262
  static long imm1_eo(  int        x)  { return  opp_u_field(x & 0xFFFF,    31, 16); }
1263
  static long uimm_eo(  int        x)  { return  opp_u_field(x,             31, 29); }
1264
  static long imm_eo(   int        x)  { return  opp_u_field(x,             31, 24); }
1265

1266
  //static int xo1(     int        x)  { return  opp_u_field(x,             29, 21); }// is contained in our opcodes
1267
  //static int xo2(     int        x)  { return  opp_u_field(x,             30, 21); }// is contained in our opcodes
1268
  //static int xo3(     int        x)  { return  opp_u_field(x,             30, 22); }// is contained in our opcodes
1269
  //static int xo4(     int        x)  { return  opp_u_field(x,             30, 26); }// is contained in our opcodes
1270
  //static int xo5(     int        x)  { return  opp_u_field(x,             29, 27); }// is contained in our opcodes
1271
  //static int xo6(     int        x)  { return  opp_u_field(x,             30, 27); }// is contained in our opcodes
1272
  //static int xo7(     int        x)  { return  opp_u_field(x,             31, 30); }// is contained in our opcodes
1273

1274
 protected:
1275
  // Compute relative address for branch.
1276
  static intptr_t disp(intptr_t x, intptr_t off) {
1277
    int xx = x - off;
1278
    xx = xx >> 2;
1279
    return xx;
1280
  }
1281

1282
 public:
1283
  // signed immediate, in low bits, nbits long
1284
  static int simm(int x, int nbits) {
1285
    assert_signed_range(x, nbits);
1286
    return x & ((1 << nbits) - 1);
1287
  }
1288

1289
  // unsigned immediate, in low bits, nbits long
1290
  static int uimm(int x, int nbits) {
1291
    assert_unsigned_const(x, nbits);
1292
    return x & ((1 << nbits) - 1);
1293
  }
1294

1295
  static void set_imm(int* instr, short s) {
1296
    // imm is always in the lower 16 bits of the instruction,
1297
    // so this is endian-neutral. Same for the get_imm below.
1298
    uint32_t w = *(uint32_t *)instr;
1299
    *instr = (int)((w & ~0x0000FFFF) | (s & 0x0000FFFF));
1300
  }
1301

1302
  static int get_imm(address a, int instruction_number) {
1303
    return (short)((int *)a)[instruction_number];
1304
  }
1305

1306
  static inline int hi16_signed(  int x) { return (int)(int16_t)(x >> 16); }
1307
  static inline int lo16_unsigned(int x) { return x & 0xffff; }
1308

1309
 protected:
1310

1311
  // Extract the top 32 bits in a 64 bit word.
1312
  static int32_t hi32(int64_t x) {
1313
    int32_t r = int32_t((uint64_t)x >> 32);
1314
    return r;
1315
  }
1316

1317
 public:
1318

1319
  static inline unsigned int align_addr(unsigned int addr, unsigned int a) {
1320
    return ((addr + (a - 1)) & ~(a - 1));
1321
  }
1322

1323
  static inline bool is_aligned(unsigned int addr, unsigned int a) {
1324
    return (0 == addr % a);
1325
  }
1326

1327
  void flush() {
1328
    AbstractAssembler::flush();
1329
  }
1330

1331
  inline void emit_int32(int);  // shadows AbstractAssembler::emit_int32
1332
  inline void emit_data(int);
1333
  inline void emit_data(int, RelocationHolder const&);
1334
  inline void emit_data(int, relocInfo::relocType rtype);
1335

1336
  // Emit an address.
1337
  inline address emit_addr(const address addr = NULL);
1338

1339
#if !defined(ABI_ELFv2)
1340
  // Emit a function descriptor with the specified entry point, TOC,
1341
  // and ENV. If the entry point is NULL, the descriptor will point
1342
  // just past the descriptor.
1343
  // Use values from friend functions as defaults.
1344
  inline address emit_fd(address entry = NULL,
1345
                         address toc = (address) FunctionDescriptor::friend_toc,
1346
                         address env = (address) FunctionDescriptor::friend_env);
1347
#endif
1348

1349
  /////////////////////////////////////////////////////////////////////////////////////
1350
  // PPC instructions
1351
  /////////////////////////////////////////////////////////////////////////////////////
1352

1353
  // Memory instructions use r0 as hard coded 0, e.g. to simulate loading
1354
  // immediates. The normal instruction encoders enforce that r0 is not
1355
  // passed to them. Use either extended mnemonics encoders or the special ra0
1356
  // versions.
1357

1358
  // Issue an illegal instruction.
1359
  inline void illtrap();
1360
  static inline bool is_illtrap(int x);
1361

1362
  // PPC 1, section 3.3.8, Fixed-Point Arithmetic Instructions
1363
  inline void addi( Register d, Register a, int si16);
1364
  inline void addis(Register d, Register a, int si16);
1365

1366
  // Prefixed add immediate, introduced by POWER10
1367
  inline void paddi(Register d, Register a, long si34, bool r);
1368
  inline void pli(  Register d, long si34);
1369

1370
 private:
1371
  inline void addi_r0ok( Register d, Register a, int si16);
1372
  inline void addis_r0ok(Register d, Register a, int si16);
1373
  inline void paddi_r0ok(Register d, Register a, long si34, bool r);
1374
 public:
1375
  inline void addic_( Register d, Register a, int si16);
1376
  inline void subfic( Register d, Register a, int si16);
1377
  inline void add(    Register d, Register a, Register b);
1378
  inline void add_(   Register d, Register a, Register b);
1379
  inline void subf(   Register d, Register a, Register b);  // d = b - a    "Sub_from", as in ppc spec.
1380
  inline void sub(    Register d, Register a, Register b);  // d = a - b    Swap operands of subf for readability.
1381
  inline void subf_(  Register d, Register a, Register b);
1382
  inline void addc(   Register d, Register a, Register b);
1383
  inline void addc_(  Register d, Register a, Register b);
1384
  inline void subfc(  Register d, Register a, Register b);
1385
  inline void subfc_( Register d, Register a, Register b);
1386
  inline void adde(   Register d, Register a, Register b);
1387
  inline void adde_(  Register d, Register a, Register b);
1388
  inline void subfe(  Register d, Register a, Register b);
1389
  inline void subfe_( Register d, Register a, Register b);
1390
  inline void addme(  Register d, Register a);
1391
  inline void addme_( Register d, Register a);
1392
  inline void subfme( Register d, Register a);
1393
  inline void subfme_(Register d, Register a);
1394
  inline void addze(  Register d, Register a);
1395
  inline void addze_( Register d, Register a);
1396
  inline void subfze( Register d, Register a);
1397
  inline void subfze_(Register d, Register a);
1398
  inline void neg(    Register d, Register a);
1399
  inline void neg_(   Register d, Register a);
1400
  inline void mulli(  Register d, Register a, int si16);
1401
  inline void mulld(  Register d, Register a, Register b);
1402
  inline void mulld_( Register d, Register a, Register b);
1403
  inline void mullw(  Register d, Register a, Register b);
1404
  inline void mullw_( Register d, Register a, Register b);
1405
  inline void mulhw(  Register d, Register a, Register b);
1406
  inline void mulhw_( Register d, Register a, Register b);
1407
  inline void mulhwu( Register d, Register a, Register b);
1408
  inline void mulhwu_(Register d, Register a, Register b);
1409
  inline void mulhd(  Register d, Register a, Register b);
1410
  inline void mulhd_( Register d, Register a, Register b);
1411
  inline void mulhdu( Register d, Register a, Register b);
1412
  inline void mulhdu_(Register d, Register a, Register b);
1413
  inline void divd(   Register d, Register a, Register b);
1414
  inline void divd_(  Register d, Register a, Register b);
1415
  inline void divw(   Register d, Register a, Register b);
1416
  inline void divw_(  Register d, Register a, Register b);
1417
  inline void divwu(  Register d, Register a, Register b);
1418
  inline void divwu_( Register d, Register a, Register b);
1419

1420
  // Fixed-Point Arithmetic Instructions with Overflow detection
1421
  inline void addo(    Register d, Register a, Register b);
1422
  inline void addo_(   Register d, Register a, Register b);
1423
  inline void subfo(   Register d, Register a, Register b);
1424
  inline void subfo_(  Register d, Register a, Register b);
1425
  inline void addco(   Register d, Register a, Register b);
1426
  inline void addco_(  Register d, Register a, Register b);
1427
  inline void subfco(  Register d, Register a, Register b);
1428
  inline void subfco_( Register d, Register a, Register b);
1429
  inline void addeo(   Register d, Register a, Register b);
1430
  inline void addeo_(  Register d, Register a, Register b);
1431
  inline void subfeo(  Register d, Register a, Register b);
1432
  inline void subfeo_( Register d, Register a, Register b);
1433
  inline void addmeo(  Register d, Register a);
1434
  inline void addmeo_( Register d, Register a);
1435
  inline void subfmeo( Register d, Register a);
1436
  inline void subfmeo_(Register d, Register a);
1437
  inline void addzeo(  Register d, Register a);
1438
  inline void addzeo_( Register d, Register a);
1439
  inline void subfzeo( Register d, Register a);
1440
  inline void subfzeo_(Register d, Register a);
1441
  inline void nego(    Register d, Register a);
1442
  inline void nego_(   Register d, Register a);
1443
  inline void mulldo(  Register d, Register a, Register b);
1444
  inline void mulldo_( Register d, Register a, Register b);
1445
  inline void mullwo(  Register d, Register a, Register b);
1446
  inline void mullwo_( Register d, Register a, Register b);
1447
  inline void divdo(   Register d, Register a, Register b);
1448
  inline void divdo_(  Register d, Register a, Register b);
1449
  inline void divwo(   Register d, Register a, Register b);
1450
  inline void divwo_(  Register d, Register a, Register b);
1451

1452
  // extended mnemonics
1453
  inline void li(   Register d, int si16);
1454
  inline void lis(  Register d, int si16);
1455
  inline void addir(Register d, int si16, Register a);
1456
  inline void subi( Register d, Register a, int si16);
1457

1458
  static bool is_addi(int x) {
1459
     return ADDI_OPCODE == (x & ADDI_OPCODE_MASK);
1460
  }
1461
  static bool is_addis(int x) {
1462
     return ADDIS_OPCODE == (x & ADDIS_OPCODE_MASK);
1463
  }
1464
  static bool is_bxx(int x) {
1465
     return BXX_OPCODE == (x & BXX_OPCODE_MASK);
1466
  }
1467
  static bool is_b(int x) {
1468
     return BXX_OPCODE == (x & BXX_OPCODE_MASK) && inv_lk_field(x) == 0;
1469
  }
1470
  static bool is_bl(int x) {
1471
     return BXX_OPCODE == (x & BXX_OPCODE_MASK) && inv_lk_field(x) == 1;
1472
  }
1473
  static bool is_bcxx(int x) {
1474
     return BCXX_OPCODE == (x & BCXX_OPCODE_MASK);
1475
  }
1476
  static bool is_bxx_or_bcxx(int x) {
1477
     return is_bxx(x) || is_bcxx(x);
1478
  }
1479
  static bool is_bctrl(int x) {
1480
     return x == 0x4e800421;
1481
  }
1482
  static bool is_bctr(int x) {
1483
     return x == 0x4e800420;
1484
  }
1485
  static bool is_bclr(int x) {
1486
     return BCLR_OPCODE == (x & XL_FORM_OPCODE_MASK);
1487
  }
1488
  static bool is_li(int x) {
1489
     return is_addi(x) && inv_ra_field(x)==0;
1490
  }
1491
  static bool is_lis(int x) {
1492
     return is_addis(x) && inv_ra_field(x)==0;
1493
  }
1494
  static bool is_mtctr(int x) {
1495
     return MTCTR_OPCODE == (x & MTCTR_OPCODE_MASK);
1496
  }
1497
  static bool is_ld(int x) {
1498
     return LD_OPCODE == (x & LD_OPCODE_MASK);
1499
  }
1500
  static bool is_std(int x) {
1501
     return STD_OPCODE == (x & STD_OPCODE_MASK);
1502
  }
1503
  static bool is_stdu(int x) {
1504
     return STDU_OPCODE == (x & STDU_OPCODE_MASK);
1505
  }
1506
  static bool is_stdx(int x) {
1507
     return STDX_OPCODE == (x & STDX_OPCODE_MASK);
1508
  }
1509
  static bool is_stdux(int x) {
1510
     return STDUX_OPCODE == (x & STDUX_OPCODE_MASK);
1511
  }
1512
  static bool is_stwx(int x) {
1513
     return STWX_OPCODE == (x & STWX_OPCODE_MASK);
1514
  }
1515
  static bool is_stwux(int x) {
1516
     return STWUX_OPCODE == (x & STWUX_OPCODE_MASK);
1517
  }
1518
  static bool is_stw(int x) {
1519
     return STW_OPCODE == (x & STW_OPCODE_MASK);
1520
  }
1521
  static bool is_stwu(int x) {
1522
     return STWU_OPCODE == (x & STWU_OPCODE_MASK);
1523
  }
1524
  static bool is_ori(int x) {
1525
     return ORI_OPCODE == (x & ORI_OPCODE_MASK);
1526
  };
1527
  static bool is_oris(int x) {
1528
     return ORIS_OPCODE == (x & ORIS_OPCODE_MASK);
1529
  };
1530
  static bool is_rldicr(int x) {
1531
     return (RLDICR_OPCODE == (x & RLDICR_OPCODE_MASK));
1532
  };
1533
  static bool is_nop(int x) {
1534
    return x == 0x60000000;
1535
  }
1536
  // endgroup opcode for Power6
1537
  static bool is_endgroup(int x) {
1538
    return is_ori(x) && inv_ra_field(x) == 1 && inv_rs_field(x) == 1 && inv_d1_field(x) == 0;
1539
  }
1540

1541

1542
 private:
1543
  // PPC 1, section 3.3.9, Fixed-Point Compare Instructions
1544
  inline void cmpi( ConditionRegister bf, int l, Register a, int si16);
1545
  inline void cmp(  ConditionRegister bf, int l, Register a, Register b);
1546
  inline void cmpli(ConditionRegister bf, int l, Register a, int ui16);
1547
  inline void cmpl( ConditionRegister bf, int l, Register a, Register b);
1548

1549
 public:
1550
  // extended mnemonics of Compare Instructions
1551
  inline void cmpwi( ConditionRegister crx, Register a, int si16);
1552
  inline void cmpdi( ConditionRegister crx, Register a, int si16);
1553
  inline void cmpw(  ConditionRegister crx, Register a, Register b);
1554
  inline void cmpd(  ConditionRegister crx, Register a, Register b);
1555
  inline void cmplwi(ConditionRegister crx, Register a, int ui16);
1556
  inline void cmpldi(ConditionRegister crx, Register a, int ui16);
1557
  inline void cmplw( ConditionRegister crx, Register a, Register b);
1558
  inline void cmpld( ConditionRegister crx, Register a, Register b);
1559

1560
  // >= Power9
1561
  inline void cmprb( ConditionRegister bf, int l, Register a, Register b);
1562
  inline void cmpeqb(ConditionRegister bf, Register a, Register b);
1563

1564
  inline void isel(   Register d, Register a, Register b, int bc);
1565
  // Convenient version which takes: Condition register, Condition code and invert flag. Omit b to keep old value.
1566
  inline void isel(   Register d, ConditionRegister cr, Condition cc, bool inv, Register a, Register b = noreg);
1567
  // Set d = 0 if (cr.cc) equals 1, otherwise b.
1568
  inline void isel_0( Register d, ConditionRegister cr, Condition cc, Register b = noreg);
1569

1570
  // PPC 1, section 3.3.11, Fixed-Point Logical Instructions
1571
         void andi(   Register a, Register s, long ui16);   // optimized version
1572
  inline void andi_(  Register a, Register s, int ui16);
1573
  inline void andis_( Register a, Register s, int ui16);
1574
  inline void ori(    Register a, Register s, int ui16);
1575
  inline void oris(   Register a, Register s, int ui16);
1576
  inline void xori(   Register a, Register s, int ui16);
1577
  inline void xoris(  Register a, Register s, int ui16);
1578
  inline void andr(   Register a, Register s, Register b);  // suffixed by 'r' as 'and' is C++ keyword
1579
  inline void and_(   Register a, Register s, Register b);
1580
  // Turn or0(rx,rx,rx) into a nop and avoid that we accidently emit a
1581
  // SMT-priority change instruction (see SMT instructions below).
1582
  inline void or_unchecked(Register a, Register s, Register b);
1583
  inline void orr(    Register a, Register s, Register b);  // suffixed by 'r' as 'or' is C++ keyword
1584
  inline void or_(    Register a, Register s, Register b);
1585
  inline void xorr(   Register a, Register s, Register b);  // suffixed by 'r' as 'xor' is C++ keyword
1586
  inline void xor_(   Register a, Register s, Register b);
1587
  inline void nand(   Register a, Register s, Register b);
1588
  inline void nand_(  Register a, Register s, Register b);
1589
  inline void nor(    Register a, Register s, Register b);
1590
  inline void nor_(   Register a, Register s, Register b);
1591
  inline void andc(   Register a, Register s, Register b);
1592
  inline void andc_(  Register a, Register s, Register b);
1593
  inline void orc(    Register a, Register s, Register b);
1594
  inline void orc_(   Register a, Register s, Register b);
1595
  inline void extsb(  Register a, Register s);
1596
  inline void extsb_( Register a, Register s);
1597
  inline void extsh(  Register a, Register s);
1598
  inline void extsh_( Register a, Register s);
1599
  inline void extsw(  Register a, Register s);
1600
  inline void extsw_( Register a, Register s);
1601

1602
  // extended mnemonics
1603
  inline void nop();
1604
  // NOP for FP and BR units (different versions to allow them to be in one group)
1605
  inline void fpnop0();
1606
  inline void fpnop1();
1607
  inline void brnop0();
1608
  inline void brnop1();
1609
  inline void brnop2();
1610

1611
  inline void mr(      Register d, Register s);
1612
  inline void ori_opt( Register d, int ui16);
1613
  inline void oris_opt(Register d, int ui16);
1614

1615
  // endgroup opcode for Power6
1616
  inline void endgroup();
1617

1618
  // count instructions
1619
  inline void cntlzw(  Register a, Register s);
1620
  inline void cntlzw_( Register a, Register s);
1621
  inline void cntlzd(  Register a, Register s);
1622
  inline void cntlzd_( Register a, Register s);
1623
  inline void cnttzw(  Register a, Register s);
1624
  inline void cnttzw_( Register a, Register s);
1625
  inline void cnttzd(  Register a, Register s);
1626
  inline void cnttzd_( Register a, Register s);
1627

1628
  // PPC 1, section 3.3.12, Fixed-Point Rotate and Shift Instructions
1629
  inline void sld(     Register a, Register s, Register b);
1630
  inline void sld_(    Register a, Register s, Register b);
1631
  inline void slw(     Register a, Register s, Register b);
1632
  inline void slw_(    Register a, Register s, Register b);
1633
  inline void srd(     Register a, Register s, Register b);
1634
  inline void srd_(    Register a, Register s, Register b);
1635
  inline void srw(     Register a, Register s, Register b);
1636
  inline void srw_(    Register a, Register s, Register b);
1637
  inline void srad(    Register a, Register s, Register b);
1638
  inline void srad_(   Register a, Register s, Register b);
1639
  inline void sraw(    Register a, Register s, Register b);
1640
  inline void sraw_(   Register a, Register s, Register b);
1641
  inline void sradi(   Register a, Register s, int sh6);
1642
  inline void sradi_(  Register a, Register s, int sh6);
1643
  inline void srawi(   Register a, Register s, int sh5);
1644
  inline void srawi_(  Register a, Register s, int sh5);
1645

1646
  // extended mnemonics for Shift Instructions
1647
  inline void sldi(    Register a, Register s, int sh6);
1648
  inline void sldi_(   Register a, Register s, int sh6);
1649
  inline void slwi(    Register a, Register s, int sh5);
1650
  inline void slwi_(   Register a, Register s, int sh5);
1651
  inline void srdi(    Register a, Register s, int sh6);
1652
  inline void srdi_(   Register a, Register s, int sh6);
1653
  inline void srwi(    Register a, Register s, int sh5);
1654
  inline void srwi_(   Register a, Register s, int sh5);
1655

1656
  inline void clrrdi(  Register a, Register s, int ui6);
1657
  inline void clrrdi_( Register a, Register s, int ui6);
1658
  inline void clrldi(  Register a, Register s, int ui6);
1659
  inline void clrldi_( Register a, Register s, int ui6);
1660
  inline void clrlsldi(Register a, Register s, int clrl6, int shl6);
1661
  inline void clrlsldi_(Register a, Register s, int clrl6, int shl6);
1662
  inline void extrdi(  Register a, Register s, int n, int b);
1663
  // testbit with condition register
1664
  inline void testbitdi(ConditionRegister cr, Register a, Register s, int ui6);
1665

1666
  // Byte reverse instructions (introduced with Power10)
1667
  inline void brh(     Register a, Register s);
1668
  inline void brw(     Register a, Register s);
1669
  inline void brd(     Register a, Register s);
1670

1671
  // rotate instructions
1672
  inline void rotldi(  Register a, Register s, int n);
1673
  inline void rotrdi(  Register a, Register s, int n);
1674
  inline void rotlwi(  Register a, Register s, int n);
1675
  inline void rotrwi(  Register a, Register s, int n);
1676

1677
  // Rotate Instructions
1678
  inline void rldic(   Register a, Register s, int sh6, int mb6);
1679
  inline void rldic_(  Register a, Register s, int sh6, int mb6);
1680
  inline void rldicr(  Register a, Register s, int sh6, int mb6);
1681
  inline void rldicr_( Register a, Register s, int sh6, int mb6);
1682
  inline void rldicl(  Register a, Register s, int sh6, int mb6);
1683
  inline void rldicl_( Register a, Register s, int sh6, int mb6);
1684
  inline void rlwinm(  Register a, Register s, int sh5, int mb5, int me5);
1685
  inline void rlwinm_( Register a, Register s, int sh5, int mb5, int me5);
1686
  inline void rldimi(  Register a, Register s, int sh6, int mb6);
1687
  inline void rldimi_( Register a, Register s, int sh6, int mb6);
1688
  inline void rlwimi(  Register a, Register s, int sh5, int mb5, int me5);
1689
  inline void insrdi(  Register a, Register s, int n,   int b);
1690
  inline void insrwi(  Register a, Register s, int n,   int b);
1691

1692
  // PPC 1, section 3.3.2 Fixed-Point Load Instructions
1693
  // 4 bytes
1694
  inline void lwzx( Register d, Register s1, Register s2);
1695
  inline void lwz(  Register d, int si16,    Register s1);
1696
  inline void lwzu( Register d, int si16,    Register s1);
1697

1698
  // 4 bytes
1699
  inline void lwax( Register d, Register s1, Register s2);
1700
  inline void lwa(  Register d, int si16,    Register s1);
1701

1702
  // 4 bytes reversed
1703
  inline void lwbrx( Register d, Register s1, Register s2);
1704

1705
  // 2 bytes
1706
  inline void lhzx( Register d, Register s1, Register s2);
1707
  inline void lhz(  Register d, int si16,    Register s1);
1708
  inline void lhzu( Register d, int si16,    Register s1);
1709

1710
  // 2 bytes reversed
1711
  inline void lhbrx( Register d, Register s1, Register s2);
1712

1713
  // 2 bytes
1714
  inline void lhax( Register d, Register s1, Register s2);
1715
  inline void lha(  Register d, int si16,    Register s1);
1716
  inline void lhau( Register d, int si16,    Register s1);
1717

1718
  // 1 byte
1719
  inline void lbzx( Register d, Register s1, Register s2);
1720
  inline void lbz(  Register d, int si16,    Register s1);
1721
  inline void lbzu( Register d, int si16,    Register s1);
1722

1723
  // 8 bytes
1724
  inline void ldx(  Register d, Register s1, Register s2);
1725
  inline void ld(   Register d, int si16,    Register s1);
1726
  inline void ldu(  Register d, int si16,    Register s1);
1727

1728
  // 8 bytes reversed
1729
  inline void ldbrx( Register d, Register s1, Register s2);
1730

1731
  // For convenience. Load pointer into d from b+s1.
1732
  inline void ld_ptr(Register d, int b, Register s1);
1733
  inline void ld_ptr(Register d, ByteSize b, Register s1);
1734

1735
  //  PPC 1, section 3.3.3 Fixed-Point Store Instructions
1736
  inline void stwx( Register d, Register s1, Register s2);
1737
  inline void stw(  Register d, int si16,    Register s1);
1738
  inline void stwu( Register d, int si16,    Register s1);
1739
  inline void stwbrx( Register d, Register s1, Register s2);
1740

1741
  inline void sthx( Register d, Register s1, Register s2);
1742
  inline void sth(  Register d, int si16,    Register s1);
1743
  inline void sthu( Register d, int si16,    Register s1);
1744
  inline void sthbrx( Register d, Register s1, Register s2);
1745

1746
  inline void stbx( Register d, Register s1, Register s2);
1747
  inline void stb(  Register d, int si16,    Register s1);
1748
  inline void stbu( Register d, int si16,    Register s1);
1749

1750
  inline void stdx( Register d, Register s1, Register s2);
1751
  inline void std(  Register d, int si16,    Register s1);
1752
  inline void stdu( Register d, int si16,    Register s1);
1753
  inline void stdux(Register s, Register a,  Register b);
1754
  inline void stdbrx( Register d, Register s1, Register s2);
1755

1756
  inline void st_ptr(Register d, int si16,    Register s1);
1757
  inline void st_ptr(Register d, ByteSize b, Register s1);
1758

1759
  // PPC 1, section 3.3.13 Move To/From System Register Instructions
1760
  inline void mtlr( Register s1);
1761
  inline void mflr( Register d);
1762
  inline void mtctr(Register s1);
1763
  inline void mfctr(Register d);
1764
  inline void mtcrf(int fxm, Register s);
1765
  inline void mfcr( Register d);
1766
  inline void mcrf( ConditionRegister crd, ConditionRegister cra);
1767
  inline void mtcr( Register s);
1768
  // >= Power9
1769
  inline void mcrxrx(ConditionRegister cra);
1770
  inline void setb( Register d, ConditionRegister cra);
1771

1772
  // >= Power10
1773
  inline void setbc( Register d, int biint);
1774
  inline void setbc( Register d, ConditionRegister cr, Condition cc);
1775
  inline void setnbc(Register d, int biint);
1776
  inline void setnbc(Register d, ConditionRegister cr, Condition cc);
1777

1778
  // Special purpose registers
1779
  // Exception Register
1780
  inline void mtxer(Register s1);
1781
  inline void mfxer(Register d);
1782
  // Vector Register Save Register
1783
  inline void mtvrsave(Register s1);
1784
  inline void mfvrsave(Register d);
1785
  // Timebase
1786
  inline void mftb(Register d);
1787
  // Introduced with Power 8:
1788
  // Data Stream Control Register
1789
  inline void mtdscr(Register s1);
1790
  inline void mfdscr(Register d );
1791
  // Transactional Memory Registers
1792
  inline void mftfhar(Register d);
1793
  inline void mftfiar(Register d);
1794
  inline void mftexasr(Register d);
1795
  inline void mftexasru(Register d);
1796

1797
  // TEXASR bit description
1798
  enum transaction_failure_reason {
1799
    // Upper half (TEXASRU):
1800
    tm_failure_code       =  0, // The Failure Code is copied from tabort or treclaim operand.
1801
    tm_failure_persistent =  7, // The failure is likely to recur on each execution.
1802
    tm_disallowed         =  8, // The instruction is not permitted.
1803
    tm_nesting_of         =  9, // The maximum transaction level was exceeded.
1804
    tm_footprint_of       = 10, // The tracking limit for transactional storage accesses was exceeded.
1805
    tm_self_induced_cf    = 11, // A self-induced conflict occurred in Suspended state.
1806
    tm_non_trans_cf       = 12, // A conflict occurred with a non-transactional access by another processor.
1807
    tm_trans_cf           = 13, // A conflict occurred with another transaction.
1808
    tm_translation_cf     = 14, // A conflict occurred with a TLB invalidation.
1809
    tm_inst_fetch_cf      = 16, // An instruction fetch was performed from a block that was previously written transactionally.
1810
    tm_tabort             = 31, // Termination was caused by the execution of an abort instruction.
1811
    // Lower half:
1812
    tm_suspended          = 32, // Failure was recorded in Suspended state.
1813
    tm_failure_summary    = 36, // Failure has been detected and recorded.
1814
    tm_tfiar_exact        = 37, // Value in the TFIAR is exact.
1815
    tm_rot                = 38, // Rollback-only transaction.
1816
    tm_transaction_level  = 52, // Transaction level (nesting depth + 1).
1817
  };
1818

1819
  // PPC 1, section 2.4.1 Branch Instructions
1820
  inline void b(  address a, relocInfo::relocType rt = relocInfo::none);
1821
  inline void b(  Label& L);
1822
  inline void bl( address a, relocInfo::relocType rt = relocInfo::none);
1823
  inline void bl( Label& L);
1824
  inline void bc( int boint, int biint, address a, relocInfo::relocType rt = relocInfo::none);
1825
  inline void bc( int boint, int biint, Label& L);
1826
  inline void bcl(int boint, int biint, address a, relocInfo::relocType rt = relocInfo::none);
1827
  inline void bcl(int boint, int biint, Label& L);
1828

1829
  inline void bclr(  int boint, int biint, int bhint, relocInfo::relocType rt = relocInfo::none);
1830
  inline void bclrl( int boint, int biint, int bhint, relocInfo::relocType rt = relocInfo::none);
1831
  inline void bcctr( int boint, int biint, int bhint = bhintbhBCCTRisNotReturnButSame,
1832
                         relocInfo::relocType rt = relocInfo::none);
1833
  inline void bcctrl(int boint, int biint, int bhint = bhintbhBCLRisReturn,
1834
                         relocInfo::relocType rt = relocInfo::none);
1835

1836
  // helper function for b, bcxx
1837
  inline bool is_within_range_of_b(address a, address pc);
1838
  inline bool is_within_range_of_bcxx(address a, address pc);
1839

1840
  // get the destination of a bxx branch (b, bl, ba, bla)
1841
  static inline address  bxx_destination(address baddr);
1842
  static inline address  bxx_destination(int instr, address pc);
1843
  static inline intptr_t bxx_destination_offset(int instr, intptr_t bxx_pos);
1844

1845
  // extended mnemonics for branch instructions
1846
  inline void blt(ConditionRegister crx, Label& L);
1847
  inline void bgt(ConditionRegister crx, Label& L);
1848
  inline void beq(ConditionRegister crx, Label& L);
1849
  inline void bso(ConditionRegister crx, Label& L);
1850
  inline void bge(ConditionRegister crx, Label& L);
1851
  inline void ble(ConditionRegister crx, Label& L);
1852
  inline void bne(ConditionRegister crx, Label& L);
1853
  inline void bns(ConditionRegister crx, Label& L);
1854

1855
  // Branch instructions with static prediction hints.
1856
  inline void blt_predict_taken(    ConditionRegister crx, Label& L);
1857
  inline void bgt_predict_taken(    ConditionRegister crx, Label& L);
1858
  inline void beq_predict_taken(    ConditionRegister crx, Label& L);
1859
  inline void bso_predict_taken(    ConditionRegister crx, Label& L);
1860
  inline void bge_predict_taken(    ConditionRegister crx, Label& L);
1861
  inline void ble_predict_taken(    ConditionRegister crx, Label& L);
1862
  inline void bne_predict_taken(    ConditionRegister crx, Label& L);
1863
  inline void bns_predict_taken(    ConditionRegister crx, Label& L);
1864
  inline void blt_predict_not_taken(ConditionRegister crx, Label& L);
1865
  inline void bgt_predict_not_taken(ConditionRegister crx, Label& L);
1866
  inline void beq_predict_not_taken(ConditionRegister crx, Label& L);
1867
  inline void bso_predict_not_taken(ConditionRegister crx, Label& L);
1868
  inline void bge_predict_not_taken(ConditionRegister crx, Label& L);
1869
  inline void ble_predict_not_taken(ConditionRegister crx, Label& L);
1870
  inline void bne_predict_not_taken(ConditionRegister crx, Label& L);
1871
  inline void bns_predict_not_taken(ConditionRegister crx, Label& L);
1872

1873
  // for use in conjunction with testbitdi:
1874
  inline void btrue( ConditionRegister crx, Label& L);
1875
  inline void bfalse(ConditionRegister crx, Label& L);
1876

1877
  inline void bltl(ConditionRegister crx, Label& L);
1878
  inline void bgtl(ConditionRegister crx, Label& L);
1879
  inline void beql(ConditionRegister crx, Label& L);
1880
  inline void bsol(ConditionRegister crx, Label& L);
1881
  inline void bgel(ConditionRegister crx, Label& L);
1882
  inline void blel(ConditionRegister crx, Label& L);
1883
  inline void bnel(ConditionRegister crx, Label& L);
1884
  inline void bnsl(ConditionRegister crx, Label& L);
1885

1886
  // extended mnemonics for Branch Instructions via LR
1887
  // We use `blr' for returns.
1888
  inline void blr(relocInfo::relocType rt = relocInfo::none);
1889

1890
  // extended mnemonics for Branch Instructions with CTR
1891
  // bdnz means `decrement CTR and jump to L if CTR is not zero'
1892
  inline void bdnz(Label& L);
1893
  // Decrement and branch if result is zero.
1894
  inline void bdz(Label& L);
1895
  // we use `bctr[l]' for jumps/calls in function descriptor glue
1896
  // code, e.g. calls to runtime functions
1897
  inline void bctr( relocInfo::relocType rt = relocInfo::none);
1898
  inline void bctrl(relocInfo::relocType rt = relocInfo::none);
1899
  // conditional jumps/branches via CTR
1900
  inline void beqctr( ConditionRegister crx, relocInfo::relocType rt = relocInfo::none);
1901
  inline void beqctrl(ConditionRegister crx, relocInfo::relocType rt = relocInfo::none);
1902
  inline void bnectr( ConditionRegister crx, relocInfo::relocType rt = relocInfo::none);
1903
  inline void bnectrl(ConditionRegister crx, relocInfo::relocType rt = relocInfo::none);
1904

1905
  // condition register logic instructions
1906
  // NOTE: There's a preferred form: d and s2 should point into the same condition register.
1907
  inline void crand( int d, int s1, int s2);
1908
  inline void crnand(int d, int s1, int s2);
1909
  inline void cror(  int d, int s1, int s2);
1910
  inline void crxor( int d, int s1, int s2);
1911
  inline void crnor( int d, int s1, int s2);
1912
  inline void creqv( int d, int s1, int s2);
1913
  inline void crandc(int d, int s1, int s2);
1914
  inline void crorc( int d, int s1, int s2);
1915

1916
  // More convenient version.
1917
  int condition_register_bit(ConditionRegister cr, Condition c) {
1918
    return 4 * (int)(intptr_t)cr + c;
1919
  }
1920
  void crand( ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc);
1921
  void crnand(ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc);
1922
  void cror(  ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc);
1923
  void crxor( ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc);
1924
  void crnor( ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc);
1925
  void creqv( ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc);
1926
  void crandc(ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc);
1927
  void crorc( ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc);
1928

1929
  // icache and dcache related instructions
1930
  inline void icbi(  Register s1, Register s2);
1931
  //inline void dcba(Register s1, Register s2); // Instruction for embedded processor only.
1932
  inline void dcbz(  Register s1, Register s2);
1933
  inline void dcbst( Register s1, Register s2);
1934
  inline void dcbf(  Register s1, Register s2);
1935

1936
  enum ct_cache_specification {
1937
    ct_primary_cache   = 0,
1938
    ct_secondary_cache = 2
1939
  };
1940
  // dcache read hint
1941
  inline void dcbt(    Register s1, Register s2);
1942
  inline void dcbtct(  Register s1, Register s2, int ct);
1943
  inline void dcbtds(  Register s1, Register s2, int ds);
1944
  // dcache write hint
1945
  inline void dcbtst(  Register s1, Register s2);
1946
  inline void dcbtstct(Register s1, Register s2, int ct);
1947

1948
  //  machine barrier instructions:
1949
  //
1950
  //  - sync    two-way memory barrier, aka fence
1951
  //  - lwsync  orders  Store|Store,
1952
  //                     Load|Store,
1953
  //                     Load|Load,
1954
  //            but not Store|Load
1955
  //  - eieio   orders memory accesses for device memory (only)
1956
  //  - isync   invalidates speculatively executed instructions
1957
  //            From the Power ISA 2.06 documentation:
1958
  //             "[...] an isync instruction prevents the execution of
1959
  //            instructions following the isync until instructions
1960
  //            preceding the isync have completed, [...]"
1961
  //            From IBM's AIX assembler reference:
1962
  //             "The isync [...] instructions causes the processor to
1963
  //            refetch any instructions that might have been fetched
1964
  //            prior to the isync instruction. The instruction isync
1965
  //            causes the processor to wait for all previous instructions
1966
  //            to complete. Then any instructions already fetched are
1967
  //            discarded and instruction processing continues in the
1968
  //            environment established by the previous instructions."
1969
  //
1970
  //  semantic barrier instructions:
1971
  //  (as defined in orderAccess.hpp)
1972
  //
1973
  //  - release  orders Store|Store,       (maps to lwsync)
1974
  //                     Load|Store
1975
  //  - acquire  orders  Load|Store,       (maps to lwsync)
1976
  //                     Load|Load
1977
  //  - fence    orders Store|Store,       (maps to sync)
1978
  //                     Load|Store,
1979
  //                     Load|Load,
1980
  //                    Store|Load
1981
  //
1982
 private:
1983
  inline void sync(int l);
1984
 public:
1985
  inline void sync();
1986
  inline void lwsync();
1987
  inline void ptesync();
1988
  inline void eieio();
1989
  inline void isync();
1990
  inline void elemental_membar(int e); // Elemental Memory Barriers (>=Power 8)
1991

1992
  // Wait instructions for polling. Attention: May result in SIGILL.
1993
  inline void wait();
1994
  inline void waitrsv(); // >=Power7
1995

1996
  // atomics
1997
  inline void lbarx_unchecked(Register d, Register a, Register b, int eh1 = 0); // >=Power 8
1998
  inline void lharx_unchecked(Register d, Register a, Register b, int eh1 = 0); // >=Power 8
1999
  inline void lwarx_unchecked(Register d, Register a, Register b, int eh1 = 0);
2000
  inline void ldarx_unchecked(Register d, Register a, Register b, int eh1 = 0);
2001
  inline void lqarx_unchecked(Register d, Register a, Register b, int eh1 = 0); // >=Power 8
2002
  inline bool lxarx_hint_exclusive_access();
2003
  inline void lbarx(  Register d, Register a, Register b, bool hint_exclusive_access = false);
2004
  inline void lharx(  Register d, Register a, Register b, bool hint_exclusive_access = false);
2005
  inline void lwarx(  Register d, Register a, Register b, bool hint_exclusive_access = false);
2006
  inline void ldarx(  Register d, Register a, Register b, bool hint_exclusive_access = false);
2007
  inline void lqarx(  Register d, Register a, Register b, bool hint_exclusive_access = false);
2008
  inline void stbcx_( Register s, Register a, Register b);
2009
  inline void sthcx_( Register s, Register a, Register b);
2010
  inline void stwcx_( Register s, Register a, Register b);
2011
  inline void stdcx_( Register s, Register a, Register b);
2012
  inline void stqcx_( Register s, Register a, Register b);
2013

2014
  // Instructions for adjusting thread priority for simultaneous
2015
  // multithreading (SMT) on Power5.
2016
 private:
2017
  inline void smt_prio_very_low();
2018
  inline void smt_prio_medium_high();
2019
  inline void smt_prio_high();
2020

2021
 public:
2022
  inline void smt_prio_low();
2023
  inline void smt_prio_medium_low();
2024
  inline void smt_prio_medium();
2025
  // >= Power7
2026
  inline void smt_yield();
2027
  inline void smt_mdoio();
2028
  inline void smt_mdoom();
2029
  // >= Power8
2030
  inline void smt_miso();
2031

2032
  // trap instructions
2033
  inline void twi_0(Register a); // for load with acquire semantics use load+twi_0+isync (trap can't occur)
2034
  // NOT FOR DIRECT USE!!
2035
 protected:
2036
  inline void tdi_unchecked(int tobits, Register a, int si16);
2037
  inline void twi_unchecked(int tobits, Register a, int si16);
2038
  inline void tdi(          int tobits, Register a, int si16);   // asserts UseSIGTRAP
2039
  inline void twi(          int tobits, Register a, int si16);   // asserts UseSIGTRAP
2040
  inline void td(           int tobits, Register a, Register b); // asserts UseSIGTRAP
2041
  inline void tw(           int tobits, Register a, Register b); // asserts UseSIGTRAP
2042

2043
 public:
2044
  static bool is_tdi(int x, int tobits, int ra, int si16) {
2045
     return (TDI_OPCODE == (x & TDI_OPCODE_MASK))
2046
         && (tobits == inv_to_field(x))
2047
         && (ra == -1/*any reg*/ || ra == inv_ra_field(x))
2048
         && (si16 == inv_si_field(x));
2049
  }
2050

2051
  static int tdi_get_si16(int x, int tobits, int ra) {
2052
    if (TDI_OPCODE == (x & TDI_OPCODE_MASK)
2053
        && (tobits == inv_to_field(x))
2054
        && (ra == -1/*any reg*/ || ra == inv_ra_field(x))) {
2055
      return inv_si_field(x);
2056
    }
2057
    return -1; // No valid tdi instruction.
2058
  }
2059

2060
  static bool is_twi(int x, int tobits, int ra, int si16) {
2061
     return (TWI_OPCODE == (x & TWI_OPCODE_MASK))
2062
         && (tobits == inv_to_field(x))
2063
         && (ra == -1/*any reg*/ || ra == inv_ra_field(x))
2064
         && (si16 == inv_si_field(x));
2065
  }
2066

2067
  static bool is_twi(int x, int tobits, int ra) {
2068
     return (TWI_OPCODE == (x & TWI_OPCODE_MASK))
2069
         && (tobits == inv_to_field(x))
2070
         && (ra == -1/*any reg*/ || ra == inv_ra_field(x));
2071
  }
2072

2073
  static bool is_td(int x, int tobits, int ra, int rb) {
2074
     return (TD_OPCODE == (x & TD_OPCODE_MASK))
2075
         && (tobits == inv_to_field(x))
2076
         && (ra == -1/*any reg*/ || ra == inv_ra_field(x))
2077
         && (rb == -1/*any reg*/ || rb == inv_rb_field(x));
2078
  }
2079

2080
  static bool is_tw(int x, int tobits, int ra, int rb) {
2081
     return (TW_OPCODE == (x & TW_OPCODE_MASK))
2082
         && (tobits == inv_to_field(x))
2083
         && (ra == -1/*any reg*/ || ra == inv_ra_field(x))
2084
         && (rb == -1/*any reg*/ || rb == inv_rb_field(x));
2085
  }
2086

2087
  // PPC floating point instructions
2088
  // PPC 1, section 4.6.2 Floating-Point Load Instructions
2089
  inline void lfs(  FloatRegister d, int si16,   Register a);
2090
  inline void lfsu( FloatRegister d, int si16,   Register a);
2091
  inline void lfsx( FloatRegister d, Register a, Register b);
2092
  inline void lfd(  FloatRegister d, int si16,   Register a);
2093
  inline void lfdu( FloatRegister d, int si16,   Register a);
2094
  inline void lfdx( FloatRegister d, Register a, Register b);
2095

2096
  // PPC 1, section 4.6.3 Floating-Point Store Instructions
2097
  inline void stfs(  FloatRegister s, int si16,   Register a);
2098
  inline void stfsu( FloatRegister s, int si16,   Register a);
2099
  inline void stfsx( FloatRegister s, Register a, Register b);
2100
  inline void stfd(  FloatRegister s, int si16,   Register a);
2101
  inline void stfdu( FloatRegister s, int si16,   Register a);
2102
  inline void stfdx( FloatRegister s, Register a, Register b);
2103

2104
  // PPC 1, section 4.6.4 Floating-Point Move Instructions
2105
  inline void fmr(  FloatRegister d, FloatRegister b);
2106
  inline void fmr_( FloatRegister d, FloatRegister b);
2107

2108
  inline void frin( FloatRegister d, FloatRegister b);
2109
  inline void frip( FloatRegister d, FloatRegister b);
2110
  inline void frim( FloatRegister d, FloatRegister b);
2111

2112
  //  inline void mffgpr( FloatRegister d, Register b);
2113
  //  inline void mftgpr( Register d, FloatRegister b);
2114
  inline void cmpb(   Register a, Register s, Register b);
2115
  inline void popcntb(Register a, Register s);
2116
  inline void popcntw(Register a, Register s);
2117
  inline void popcntd(Register a, Register s);
2118

2119
  inline void fneg(  FloatRegister d, FloatRegister b);
2120
  inline void fneg_( FloatRegister d, FloatRegister b);
2121
  inline void fabs(  FloatRegister d, FloatRegister b);
2122
  inline void fabs_( FloatRegister d, FloatRegister b);
2123
  inline void fnabs( FloatRegister d, FloatRegister b);
2124
  inline void fnabs_(FloatRegister d, FloatRegister b);
2125

2126
  // PPC 1, section 4.6.5.1 Floating-Point Elementary Arithmetic Instructions
2127
  inline void fadd(  FloatRegister d, FloatRegister a, FloatRegister b);
2128
  inline void fadd_( FloatRegister d, FloatRegister a, FloatRegister b);
2129
  inline void fadds( FloatRegister d, FloatRegister a, FloatRegister b);
2130
  inline void fadds_(FloatRegister d, FloatRegister a, FloatRegister b);
2131
  inline void fsub(  FloatRegister d, FloatRegister a, FloatRegister b);
2132
  inline void fsub_( FloatRegister d, FloatRegister a, FloatRegister b);
2133
  inline void fsubs( FloatRegister d, FloatRegister a, FloatRegister b);
2134
  inline void fsubs_(FloatRegister d, FloatRegister a, FloatRegister b);
2135
  inline void fmul(  FloatRegister d, FloatRegister a, FloatRegister c);
2136
  inline void fmul_( FloatRegister d, FloatRegister a, FloatRegister c);
2137
  inline void fmuls( FloatRegister d, FloatRegister a, FloatRegister c);
2138
  inline void fmuls_(FloatRegister d, FloatRegister a, FloatRegister c);
2139
  inline void fdiv(  FloatRegister d, FloatRegister a, FloatRegister b);
2140
  inline void fdiv_( FloatRegister d, FloatRegister a, FloatRegister b);
2141
  inline void fdivs( FloatRegister d, FloatRegister a, FloatRegister b);
2142
  inline void fdivs_(FloatRegister d, FloatRegister a, FloatRegister b);
2143

2144
  // Fused multiply-accumulate instructions.
2145
  // WARNING: Use only when rounding between the 2 parts is not desired.
2146
  // Some floating point tck tests will fail if used incorrectly.
2147
  inline void fmadd(   FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b);
2148
  inline void fmadd_(  FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b);
2149
  inline void fmadds(  FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b);
2150
  inline void fmadds_( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b);
2151
  inline void fmsub(   FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b);
2152
  inline void fmsub_(  FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b);
2153
  inline void fmsubs(  FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b);
2154
  inline void fmsubs_( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b);
2155
  inline void fnmadd(  FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b);
2156
  inline void fnmadd_( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b);
2157
  inline void fnmadds( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b);
2158
  inline void fnmadds_(FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b);
2159
  inline void fnmsub(  FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b);
2160
  inline void fnmsub_( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b);
2161
  inline void fnmsubs( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b);
2162
  inline void fnmsubs_(FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b);
2163

2164
  // PPC 1, section 4.6.6 Floating-Point Rounding and Conversion Instructions
2165
  inline void frsp(  FloatRegister d, FloatRegister b);
2166
  inline void fctid( FloatRegister d, FloatRegister b);
2167
  inline void fctidz(FloatRegister d, FloatRegister b);
2168
  inline void fctiw( FloatRegister d, FloatRegister b);
2169
  inline void fctiwz(FloatRegister d, FloatRegister b);
2170
  inline void fcfid( FloatRegister d, FloatRegister b);
2171
  inline void fcfids(FloatRegister d, FloatRegister b);
2172

2173
  // PPC 1, section 4.6.7 Floating-Point Compare Instructions
2174
  inline void fcmpu( ConditionRegister crx, FloatRegister a, FloatRegister b);
2175

2176
  inline void fsqrt( FloatRegister d, FloatRegister b);
2177
  inline void fsqrts(FloatRegister d, FloatRegister b);
2178

2179
  // Vector instructions for >= Power6.
2180
  inline void lvebx(    VectorRegister d, Register s1, Register s2);
2181
  inline void lvehx(    VectorRegister d, Register s1, Register s2);
2182
  inline void lvewx(    VectorRegister d, Register s1, Register s2);
2183
  inline void lvx(      VectorRegister d, Register s1, Register s2);
2184
  inline void lvxl(     VectorRegister d, Register s1, Register s2);
2185
  inline void stvebx(   VectorRegister d, Register s1, Register s2);
2186
  inline void stvehx(   VectorRegister d, Register s1, Register s2);
2187
  inline void stvewx(   VectorRegister d, Register s1, Register s2);
2188
  inline void stvx(     VectorRegister d, Register s1, Register s2);
2189
  inline void stvxl(    VectorRegister d, Register s1, Register s2);
2190
  inline void lvsl(     VectorRegister d, Register s1, Register s2);
2191
  inline void lvsr(     VectorRegister d, Register s1, Register s2);
2192
  inline void vpkpx(    VectorRegister d, VectorRegister a, VectorRegister b);
2193
  inline void vpkshss(  VectorRegister d, VectorRegister a, VectorRegister b);
2194
  inline void vpkswss(  VectorRegister d, VectorRegister a, VectorRegister b);
2195
  inline void vpkshus(  VectorRegister d, VectorRegister a, VectorRegister b);
2196
  inline void vpkswus(  VectorRegister d, VectorRegister a, VectorRegister b);
2197
  inline void vpkuhum(  VectorRegister d, VectorRegister a, VectorRegister b);
2198
  inline void vpkuwum(  VectorRegister d, VectorRegister a, VectorRegister b);
2199
  inline void vpkuhus(  VectorRegister d, VectorRegister a, VectorRegister b);
2200
  inline void vpkuwus(  VectorRegister d, VectorRegister a, VectorRegister b);
2201
  inline void vupkhpx(  VectorRegister d, VectorRegister b);
2202
  inline void vupkhsb(  VectorRegister d, VectorRegister b);
2203
  inline void vupkhsh(  VectorRegister d, VectorRegister b);
2204
  inline void vupklpx(  VectorRegister d, VectorRegister b);
2205
  inline void vupklsb(  VectorRegister d, VectorRegister b);
2206
  inline void vupklsh(  VectorRegister d, VectorRegister b);
2207
  inline void vmrghb(   VectorRegister d, VectorRegister a, VectorRegister b);
2208
  inline void vmrghw(   VectorRegister d, VectorRegister a, VectorRegister b);
2209
  inline void vmrghh(   VectorRegister d, VectorRegister a, VectorRegister b);
2210
  inline void vmrglb(   VectorRegister d, VectorRegister a, VectorRegister b);
2211
  inline void vmrglw(   VectorRegister d, VectorRegister a, VectorRegister b);
2212
  inline void vmrglh(   VectorRegister d, VectorRegister a, VectorRegister b);
2213
  inline void vsplt(    VectorRegister d, int ui4,          VectorRegister b);
2214
  inline void vsplth(   VectorRegister d, int ui3,          VectorRegister b);
2215
  inline void vspltw(   VectorRegister d, int ui2,          VectorRegister b);
2216
  inline void vspltisb( VectorRegister d, int si5);
2217
  inline void vspltish( VectorRegister d, int si5);
2218
  inline void vspltisw( VectorRegister d, int si5);
2219
  inline void vperm(    VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
2220
  inline void vpextd(   VectorRegister d, VectorRegister a, VectorRegister b);
2221
  inline void vsel(     VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
2222
  inline void vsl(      VectorRegister d, VectorRegister a, VectorRegister b);
2223
  inline void vsldoi(   VectorRegister d, VectorRegister a, VectorRegister b, int ui4);
2224
  inline void vslo(     VectorRegister d, VectorRegister a, VectorRegister b);
2225
  inline void vsr(      VectorRegister d, VectorRegister a, VectorRegister b);
2226
  inline void vsro(     VectorRegister d, VectorRegister a, VectorRegister b);
2227
  inline void vaddcuw(  VectorRegister d, VectorRegister a, VectorRegister b);
2228
  inline void vaddshs(  VectorRegister d, VectorRegister a, VectorRegister b);
2229
  inline void vaddsbs(  VectorRegister d, VectorRegister a, VectorRegister b);
2230
  inline void vaddsws(  VectorRegister d, VectorRegister a, VectorRegister b);
2231
  inline void vaddubm(  VectorRegister d, VectorRegister a, VectorRegister b);
2232
  inline void vadduwm(  VectorRegister d, VectorRegister a, VectorRegister b);
2233
  inline void vadduhm(  VectorRegister d, VectorRegister a, VectorRegister b);
2234
  inline void vaddudm(  VectorRegister d, VectorRegister a, VectorRegister b);
2235
  inline void vaddubs(  VectorRegister d, VectorRegister a, VectorRegister b);
2236
  inline void vadduws(  VectorRegister d, VectorRegister a, VectorRegister b);
2237
  inline void vadduhs(  VectorRegister d, VectorRegister a, VectorRegister b);
2238
  inline void vaddfp(   VectorRegister d, VectorRegister a, VectorRegister b);
2239
  inline void vsubcuw(  VectorRegister d, VectorRegister a, VectorRegister b);
2240
  inline void vsubshs(  VectorRegister d, VectorRegister a, VectorRegister b);
2241
  inline void vsubsbs(  VectorRegister d, VectorRegister a, VectorRegister b);
2242
  inline void vsubsws(  VectorRegister d, VectorRegister a, VectorRegister b);
2243
  inline void vsububm(  VectorRegister d, VectorRegister a, VectorRegister b);
2244
  inline void vsubuwm(  VectorRegister d, VectorRegister a, VectorRegister b);
2245
  inline void vsubuhm(  VectorRegister d, VectorRegister a, VectorRegister b);
2246
  inline void vsubudm(  VectorRegister d, VectorRegister a, VectorRegister b);
2247
  inline void vsububs(  VectorRegister d, VectorRegister a, VectorRegister b);
2248
  inline void vsubuws(  VectorRegister d, VectorRegister a, VectorRegister b);
2249
  inline void vsubuhs(  VectorRegister d, VectorRegister a, VectorRegister b);
2250
  inline void vsubfp(   VectorRegister d, VectorRegister a, VectorRegister b);
2251
  inline void vmulesb(  VectorRegister d, VectorRegister a, VectorRegister b);
2252
  inline void vmuleub(  VectorRegister d, VectorRegister a, VectorRegister b);
2253
  inline void vmulesh(  VectorRegister d, VectorRegister a, VectorRegister b);
2254
  inline void vmuleuh(  VectorRegister d, VectorRegister a, VectorRegister b);
2255
  inline void vmulosb(  VectorRegister d, VectorRegister a, VectorRegister b);
2256
  inline void vmuloub(  VectorRegister d, VectorRegister a, VectorRegister b);
2257
  inline void vmulosh(  VectorRegister d, VectorRegister a, VectorRegister b);
2258
  inline void vmulosw(  VectorRegister d, VectorRegister a, VectorRegister b);
2259
  inline void vmulouh(  VectorRegister d, VectorRegister a, VectorRegister b);
2260
  inline void vmuluwm(  VectorRegister d, VectorRegister a, VectorRegister b);
2261
  inline void vmhaddshs(VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
2262
  inline void vmhraddshs(VectorRegister d,VectorRegister a, VectorRegister b, VectorRegister c);
2263
  inline void vmladduhm(VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
2264
  inline void vmsubuhm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
2265
  inline void vmsummbm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
2266
  inline void vmsumshm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
2267
  inline void vmsumshs( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
2268
  inline void vmsumuhm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
2269
  inline void vmsumuhs( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
2270
  inline void vmaddfp(  VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
2271
  inline void vsumsws(  VectorRegister d, VectorRegister a, VectorRegister b);
2272
  inline void vsum2sws( VectorRegister d, VectorRegister a, VectorRegister b);
2273
  inline void vsum4sbs( VectorRegister d, VectorRegister a, VectorRegister b);
2274
  inline void vsum4ubs( VectorRegister d, VectorRegister a, VectorRegister b);
2275
  inline void vsum4shs( VectorRegister d, VectorRegister a, VectorRegister b);
2276
  inline void vavgsb(   VectorRegister d, VectorRegister a, VectorRegister b);
2277
  inline void vavgsw(   VectorRegister d, VectorRegister a, VectorRegister b);
2278
  inline void vavgsh(   VectorRegister d, VectorRegister a, VectorRegister b);
2279
  inline void vavgub(   VectorRegister d, VectorRegister a, VectorRegister b);
2280
  inline void vavguw(   VectorRegister d, VectorRegister a, VectorRegister b);
2281
  inline void vavguh(   VectorRegister d, VectorRegister a, VectorRegister b);
2282
  inline void vmaxsb(   VectorRegister d, VectorRegister a, VectorRegister b);
2283
  inline void vmaxsw(   VectorRegister d, VectorRegister a, VectorRegister b);
2284
  inline void vmaxsh(   VectorRegister d, VectorRegister a, VectorRegister b);
2285
  inline void vmaxub(   VectorRegister d, VectorRegister a, VectorRegister b);
2286
  inline void vmaxuw(   VectorRegister d, VectorRegister a, VectorRegister b);
2287
  inline void vmaxuh(   VectorRegister d, VectorRegister a, VectorRegister b);
2288
  inline void vminsb(   VectorRegister d, VectorRegister a, VectorRegister b);
2289
  inline void vminsw(   VectorRegister d, VectorRegister a, VectorRegister b);
2290
  inline void vminsh(   VectorRegister d, VectorRegister a, VectorRegister b);
2291
  inline void vminub(   VectorRegister d, VectorRegister a, VectorRegister b);
2292
  inline void vminuw(   VectorRegister d, VectorRegister a, VectorRegister b);
2293
  inline void vminuh(   VectorRegister d, VectorRegister a, VectorRegister b);
2294
  inline void vcmpequb( VectorRegister d, VectorRegister a, VectorRegister b);
2295
  inline void vcmpequh( VectorRegister d, VectorRegister a, VectorRegister b);
2296
  inline void vcmpequw( VectorRegister d, VectorRegister a, VectorRegister b);
2297
  inline void vcmpgtsh( VectorRegister d, VectorRegister a, VectorRegister b);
2298
  inline void vcmpgtsb( VectorRegister d, VectorRegister a, VectorRegister b);
2299
  inline void vcmpgtsw( VectorRegister d, VectorRegister a, VectorRegister b);
2300
  inline void vcmpgtub( VectorRegister d, VectorRegister a, VectorRegister b);
2301
  inline void vcmpgtuh( VectorRegister d, VectorRegister a, VectorRegister b);
2302
  inline void vcmpgtuw( VectorRegister d, VectorRegister a, VectorRegister b);
2303
  inline void vcmpequb_(VectorRegister d, VectorRegister a, VectorRegister b);
2304
  inline void vcmpequh_(VectorRegister d, VectorRegister a, VectorRegister b);
2305
  inline void vcmpequw_(VectorRegister d, VectorRegister a, VectorRegister b);
2306
  inline void vcmpgtsh_(VectorRegister d, VectorRegister a, VectorRegister b);
2307
  inline void vcmpgtsb_(VectorRegister d, VectorRegister a, VectorRegister b);
2308
  inline void vcmpgtsw_(VectorRegister d, VectorRegister a, VectorRegister b);
2309
  inline void vcmpgtub_(VectorRegister d, VectorRegister a, VectorRegister b);
2310
  inline void vcmpgtuh_(VectorRegister d, VectorRegister a, VectorRegister b);
2311
  inline void vcmpgtuw_(VectorRegister d, VectorRegister a, VectorRegister b);
2312
  inline void vand(     VectorRegister d, VectorRegister a, VectorRegister b);
2313
  inline void vandc(    VectorRegister d, VectorRegister a, VectorRegister b);
2314
  inline void vnor(     VectorRegister d, VectorRegister a, VectorRegister b);
2315
  inline void vor(      VectorRegister d, VectorRegister a, VectorRegister b);
2316
  inline void vmr(      VectorRegister d, VectorRegister a);
2317
  inline void vxor(     VectorRegister d, VectorRegister a, VectorRegister b);
2318
  inline void vrld(     VectorRegister d, VectorRegister a, VectorRegister b);
2319
  inline void vrlb(     VectorRegister d, VectorRegister a, VectorRegister b);
2320
  inline void vrlw(     VectorRegister d, VectorRegister a, VectorRegister b);
2321
  inline void vrlh(     VectorRegister d, VectorRegister a, VectorRegister b);
2322
  inline void vslb(     VectorRegister d, VectorRegister a, VectorRegister b);
2323
  inline void vskw(     VectorRegister d, VectorRegister a, VectorRegister b);
2324
  inline void vslh(     VectorRegister d, VectorRegister a, VectorRegister b);
2325
  inline void vsrb(     VectorRegister d, VectorRegister a, VectorRegister b);
2326
  inline void vsrw(     VectorRegister d, VectorRegister a, VectorRegister b);
2327
  inline void vsrh(     VectorRegister d, VectorRegister a, VectorRegister b);
2328
  inline void vsrab(    VectorRegister d, VectorRegister a, VectorRegister b);
2329
  inline void vsraw(    VectorRegister d, VectorRegister a, VectorRegister b);
2330
  inline void vsrah(    VectorRegister d, VectorRegister a, VectorRegister b);
2331
  inline void vpopcntw( VectorRegister d, VectorRegister b);
2332
  // Vector Floating-Point not implemented yet
2333
  inline void mtvscr(   VectorRegister b);
2334
  inline void mfvscr(   VectorRegister d);
2335

2336
  // Vector-Scalar (VSX) instructions.
2337
  inline void lxv(      VectorSRegister d, int si16, Register a);
2338
  inline void stxv(     VectorSRegister d, int si16, Register a);
2339
  inline void lxvl(     VectorSRegister d, Register a, Register b);
2340
  inline void stxvl(    VectorSRegister d, Register a, Register b);
2341
  inline void lxvd2x(   VectorSRegister d, Register a);
2342
  inline void lxvd2x(   VectorSRegister d, Register a, Register b);
2343
  inline void stxvd2x(  VectorSRegister d, Register a);
2344
  inline void stxvd2x(  VectorSRegister d, Register a, Register b);
2345
  inline void mtvrwz(   VectorRegister  d, Register a);
2346
  inline void mfvrwz(   Register        a, VectorRegister d);
2347
  inline void mtvrd(    VectorRegister  d, Register a);
2348
  inline void mfvrd(    Register        a, VectorRegister d);
2349
  inline void xxperm(   VectorSRegister d, VectorSRegister a, VectorSRegister b);
2350
  inline void xxpermdi( VectorSRegister d, VectorSRegister a, VectorSRegister b, int dm);
2351
  inline void xxmrghw(  VectorSRegister d, VectorSRegister a, VectorSRegister b);
2352
  inline void xxmrglw(  VectorSRegister d, VectorSRegister a, VectorSRegister b);
2353
  inline void mtvsrd(   VectorSRegister d, Register a);
2354
  inline void mfvsrd(   Register        d, VectorSRegister a);
2355
  inline void mtvsrdd(  VectorSRegister d, Register a, Register b);
2356
  inline void mtvsrwz(  VectorSRegister d, Register a);
2357
  inline void mfvsrwz(  Register        d, VectorSRegister a);
2358
  inline void xxspltw(  VectorSRegister d, VectorSRegister b, int ui2);
2359
  inline void xxlor(    VectorSRegister d, VectorSRegister a, VectorSRegister b);
2360
  inline void xxlxor(   VectorSRegister d, VectorSRegister a, VectorSRegister b);
2361
  inline void xxleqv(   VectorSRegister d, VectorSRegister a, VectorSRegister b);
2362
  inline void xxbrd(    VectorSRegister d, VectorSRegister b);
2363
  inline void xxbrw(    VectorSRegister d, VectorSRegister b);
2364
  inline void xxland(   VectorSRegister d, VectorSRegister a, VectorSRegister b);
2365
  inline void xxsel(    VectorSRegister d, VectorSRegister a, VectorSRegister b, VectorSRegister c);
2366
  inline void xxspltib( VectorSRegister d, int ui8);
2367
  inline void xvdivsp(  VectorSRegister d, VectorSRegister a, VectorSRegister b);
2368
  inline void xvdivdp(  VectorSRegister d, VectorSRegister a, VectorSRegister b);
2369
  inline void xvabssp(  VectorSRegister d, VectorSRegister b);
2370
  inline void xvabsdp(  VectorSRegister d, VectorSRegister b);
2371
  inline void xvnegsp(  VectorSRegister d, VectorSRegister b);
2372
  inline void xvnegdp(  VectorSRegister d, VectorSRegister b);
2373
  inline void xvsqrtsp( VectorSRegister d, VectorSRegister b);
2374
  inline void xvsqrtdp( VectorSRegister d, VectorSRegister b);
2375
  inline void xscvdpspn(VectorSRegister d, VectorSRegister b);
2376
  inline void xvadddp(  VectorSRegister d, VectorSRegister a, VectorSRegister b);
2377
  inline void xvsubdp(  VectorSRegister d, VectorSRegister a, VectorSRegister b);
2378
  inline void xvmulsp(  VectorSRegister d, VectorSRegister a, VectorSRegister b);
2379
  inline void xvmuldp(  VectorSRegister d, VectorSRegister a, VectorSRegister b);
2380
  inline void xvmaddasp(VectorSRegister d, VectorSRegister a, VectorSRegister b);
2381
  inline void xvmaddadp(VectorSRegister d, VectorSRegister a, VectorSRegister b);
2382
  inline void xvmsubasp(VectorSRegister d, VectorSRegister a, VectorSRegister b);
2383
  inline void xvmsubadp(VectorSRegister d, VectorSRegister a, VectorSRegister b);
2384
  inline void xvnmsubasp(VectorSRegister d, VectorSRegister a, VectorSRegister b);
2385
  inline void xvnmsubadp(VectorSRegister d, VectorSRegister a, VectorSRegister b);
2386
  inline void xvrdpi(   VectorSRegister d, VectorSRegister b);
2387
  inline void xvrdpim(  VectorSRegister d, VectorSRegister b);
2388
  inline void xvrdpip(  VectorSRegister d, VectorSRegister b);
2389

2390
  // VSX Extended Mnemonics
2391
  inline void xxspltd(  VectorSRegister d, VectorSRegister a, int x);
2392
  inline void xxmrghd(  VectorSRegister d, VectorSRegister a, VectorSRegister b);
2393
  inline void xxmrgld(  VectorSRegister d, VectorSRegister a, VectorSRegister b);
2394
  inline void xxswapd(  VectorSRegister d, VectorSRegister a);
2395

2396
  // Vector-Scalar (VSX) instructions.
2397
  inline void mtfprd(   FloatRegister   d, Register a);
2398
  inline void mtfprwa(  FloatRegister   d, Register a);
2399
  inline void mffprd(   Register        a, FloatRegister d);
2400

2401
  // Deliver A Random Number (introduced with POWER9)
2402
  inline void darn( Register d, int l = 1 /*L=CRN*/);
2403

2404
  // AES (introduced with Power 8)
2405
  inline void vcipher(     VectorRegister d, VectorRegister a, VectorRegister b);
2406
  inline void vcipherlast( VectorRegister d, VectorRegister a, VectorRegister b);
2407
  inline void vncipher(    VectorRegister d, VectorRegister a, VectorRegister b);
2408
  inline void vncipherlast(VectorRegister d, VectorRegister a, VectorRegister b);
2409
  inline void vsbox(       VectorRegister d, VectorRegister a);
2410

2411
  // SHA (introduced with Power 8)
2412
  inline void vshasigmad(VectorRegister d, VectorRegister a, bool st, int six);
2413
  inline void vshasigmaw(VectorRegister d, VectorRegister a, bool st, int six);
2414

2415
  // Vector Binary Polynomial Multiplication (introduced with Power 8)
2416
  inline void vpmsumb(  VectorRegister d, VectorRegister a, VectorRegister b);
2417
  inline void vpmsumd(  VectorRegister d, VectorRegister a, VectorRegister b);
2418
  inline void vpmsumh(  VectorRegister d, VectorRegister a, VectorRegister b);
2419
  inline void vpmsumw(  VectorRegister d, VectorRegister a, VectorRegister b);
2420

2421
  // Vector Permute and Xor (introduced with Power 8)
2422
  inline void vpermxor( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
2423

2424
  // Transactional Memory instructions (introduced with Power 8)
2425
  inline void tbegin_();    // R=0
2426
  inline void tbeginrot_(); // R=1 Rollback-Only Transaction
2427
  inline void tend_();    // A=0
2428
  inline void tendall_(); // A=1
2429
  inline void tabort_();
2430
  inline void tabort_(Register a);
2431
  inline void tabortwc_(int t, Register a, Register b);
2432
  inline void tabortwci_(int t, Register a, int si);
2433
  inline void tabortdc_(int t, Register a, Register b);
2434
  inline void tabortdci_(int t, Register a, int si);
2435
  inline void tsuspend_(); // tsr with L=0
2436
  inline void tresume_();  // tsr with L=1
2437
  inline void tcheck(int f);
2438

2439
  static bool is_tbegin(int x) {
2440
    return TBEGIN_OPCODE == (x & (0x3f << OPCODE_SHIFT | 0x3ff << 1));
2441
  }
2442

2443
  // The following encoders use r0 as second operand. These instructions
2444
  // read r0 as '0'.
2445
  inline void lwzx( Register d, Register s2);
2446
  inline void lwz(  Register d, int si16);
2447
  inline void lwax( Register d, Register s2);
2448
  inline void lwa(  Register d, int si16);
2449
  inline void lwbrx(Register d, Register s2);
2450
  inline void lhzx( Register d, Register s2);
2451
  inline void lhz(  Register d, int si16);
2452
  inline void lhax( Register d, Register s2);
2453
  inline void lha(  Register d, int si16);
2454
  inline void lhbrx(Register d, Register s2);
2455
  inline void lbzx( Register d, Register s2);
2456
  inline void lbz(  Register d, int si16);
2457
  inline void ldx(  Register d, Register s2);
2458
  inline void ld(   Register d, int si16);
2459
  inline void ldbrx(Register d, Register s2);
2460
  inline void stwx( Register d, Register s2);
2461
  inline void stw(  Register d, int si16);
2462
  inline void stwbrx( Register d, Register s2);
2463
  inline void sthx( Register d, Register s2);
2464
  inline void sth(  Register d, int si16);
2465
  inline void sthbrx( Register d, Register s2);
2466
  inline void stbx( Register d, Register s2);
2467
  inline void stb(  Register d, int si16);
2468
  inline void stdx( Register d, Register s2);
2469
  inline void std(  Register d, int si16);
2470
  inline void stdbrx( Register d, Register s2);
2471

2472
  // PPC 2, section 3.2.1 Instruction Cache Instructions
2473
  inline void icbi(    Register s2);
2474
  // PPC 2, section 3.2.2 Data Cache Instructions
2475
  //inlinevoid dcba(   Register s2); // Instruction for embedded processor only.
2476
  inline void dcbz(    Register s2);
2477
  inline void dcbst(   Register s2);
2478
  inline void dcbf(    Register s2);
2479
  // dcache read hint
2480
  inline void dcbt(    Register s2);
2481
  inline void dcbtct(  Register s2, int ct);
2482
  inline void dcbtds(  Register s2, int ds);
2483
  // dcache write hint
2484
  inline void dcbtst(  Register s2);
2485
  inline void dcbtstct(Register s2, int ct);
2486

2487
  // Atomics: use ra0mem to disallow R0 as base.
2488
  inline void lbarx_unchecked(Register d, Register b, int eh1);
2489
  inline void lharx_unchecked(Register d, Register b, int eh1);
2490
  inline void lwarx_unchecked(Register d, Register b, int eh1);
2491
  inline void ldarx_unchecked(Register d, Register b, int eh1);
2492
  inline void lqarx_unchecked(Register d, Register b, int eh1);
2493
  inline void lbarx( Register d, Register b, bool hint_exclusive_access);
2494
  inline void lharx( Register d, Register b, bool hint_exclusive_access);
2495
  inline void lwarx( Register d, Register b, bool hint_exclusive_access);
2496
  inline void ldarx( Register d, Register b, bool hint_exclusive_access);
2497
  inline void lqarx( Register d, Register b, bool hint_exclusive_access);
2498
  inline void stbcx_(Register s, Register b);
2499
  inline void sthcx_(Register s, Register b);
2500
  inline void stwcx_(Register s, Register b);
2501
  inline void stdcx_(Register s, Register b);
2502
  inline void stqcx_(Register s, Register b);
2503
  inline void lfs(   FloatRegister d, int si16);
2504
  inline void lfsx(  FloatRegister d, Register b);
2505
  inline void lfd(   FloatRegister d, int si16);
2506
  inline void lfdx(  FloatRegister d, Register b);
2507
  inline void stfs(  FloatRegister s, int si16);
2508
  inline void stfsx( FloatRegister s, Register b);
2509
  inline void stfd(  FloatRegister s, int si16);
2510
  inline void stfdx( FloatRegister s, Register b);
2511
  inline void lvebx( VectorRegister d, Register s2);
2512
  inline void lvehx( VectorRegister d, Register s2);
2513
  inline void lvewx( VectorRegister d, Register s2);
2514
  inline void lvx(   VectorRegister d, Register s2);
2515
  inline void lvxl(  VectorRegister d, Register s2);
2516
  inline void stvebx(VectorRegister d, Register s2);
2517
  inline void stvehx(VectorRegister d, Register s2);
2518
  inline void stvewx(VectorRegister d, Register s2);
2519
  inline void stvx(  VectorRegister d, Register s2);
2520
  inline void stvxl( VectorRegister d, Register s2);
2521
  inline void lvsl(  VectorRegister d, Register s2);
2522
  inline void lvsr(  VectorRegister d, Register s2);
2523

2524
  // Endianess specific concatenation of 2 loaded vectors.
2525
  inline void load_perm(VectorRegister perm, Register addr);
2526
  inline void vec_perm(VectorRegister first_dest, VectorRegister second, VectorRegister perm);
2527
  inline void vec_perm(VectorRegister dest, VectorRegister first, VectorRegister second, VectorRegister perm);
2528

2529
  // RegisterOrConstant versions.
2530
  // These emitters choose between the versions using two registers and
2531
  // those with register and immediate, depending on the content of roc.
2532
  // If the constant is not encodable as immediate, instructions to
2533
  // load the constant are emitted beforehand. Store instructions need a
2534
  // tmp reg if the constant is not encodable as immediate.
2535
  // Size unpredictable.
2536
  void ld(  Register d, RegisterOrConstant roc, Register s1 = noreg);
2537
  void lwa( Register d, RegisterOrConstant roc, Register s1 = noreg);
2538
  void lwz( Register d, RegisterOrConstant roc, Register s1 = noreg);
2539
  void lha( Register d, RegisterOrConstant roc, Register s1 = noreg);
2540
  void lhz( Register d, RegisterOrConstant roc, Register s1 = noreg);
2541
  void lbz( Register d, RegisterOrConstant roc, Register s1 = noreg);
2542
  void std( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg);
2543
  void stw( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg);
2544
  void sth( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg);
2545
  void stb( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg);
2546
  void add( Register d, RegisterOrConstant roc, Register s1);
2547
  void subf(Register d, RegisterOrConstant roc, Register s1);
2548
  void cmpd(ConditionRegister d, RegisterOrConstant roc, Register s1);
2549
  // Load pointer d from s1+roc.
2550
  void ld_ptr(Register d, RegisterOrConstant roc, Register s1 = noreg) { ld(d, roc, s1); }
2551

2552
  // Emit several instructions to load a 64 bit constant. This issues a fixed
2553
  // instruction pattern so that the constant can be patched later on.
2554
  enum {
2555
    load_const_size = 5 * BytesPerInstWord
2556
  };
2557
         void load_const(Register d, long a,            Register tmp = noreg);
2558
  inline void load_const(Register d, void* a,           Register tmp = noreg);
2559
  inline void load_const(Register d, Label& L,          Register tmp = noreg);
2560
  inline void load_const(Register d, AddressLiteral& a, Register tmp = noreg);
2561
  inline void load_const32(Register d, int i); // load signed int (patchable)
2562

2563
  // Load a 64 bit constant, optimized, not identifyable.
2564
  // Tmp can be used to increase ILP. Set return_simm16_rest = true to get a
2565
  // 16 bit immediate offset. This is useful if the offset can be encoded in
2566
  // a succeeding instruction.
2567
         int load_const_optimized(Register d, long a,  Register tmp = noreg, bool return_simm16_rest = false);
2568
  inline int load_const_optimized(Register d, void* a, Register tmp = noreg, bool return_simm16_rest = false) {
2569
    return load_const_optimized(d, (long)(unsigned long)a, tmp, return_simm16_rest);
2570
  }
2571

2572
  // If return_simm16_rest, the return value needs to get added afterwards.
2573
         int add_const_optimized(Register d, Register s, long x, Register tmp = R0, bool return_simm16_rest = false);
2574
  inline int add_const_optimized(Register d, Register s, void* a, Register tmp = R0, bool return_simm16_rest = false) {
2575
    return add_const_optimized(d, s, (long)(unsigned long)a, tmp, return_simm16_rest);
2576
  }
2577

2578
  // If return_simm16_rest, the return value needs to get added afterwards.
2579
  inline int sub_const_optimized(Register d, Register s, long x, Register tmp = R0, bool return_simm16_rest = false) {
2580
    return add_const_optimized(d, s, -x, tmp, return_simm16_rest);
2581
  }
2582
  inline int sub_const_optimized(Register d, Register s, void* a, Register tmp = R0, bool return_simm16_rest = false) {
2583
    return sub_const_optimized(d, s, (long)(unsigned long)a, tmp, return_simm16_rest);
2584
  }
2585

2586
  // Creation
2587
  Assembler(CodeBuffer* code) : AbstractAssembler(code) {
2588
#ifdef CHECK_DELAY
2589
    delay_state = no_delay;
2590
#endif
2591
  }
2592

2593
  // Testing
2594
#ifndef PRODUCT
2595
  void test_asm();
2596
#endif
2597
};
2598

2599

2600
#endif // CPU_PPC_ASSEMBLER_PPC_HPP
2601

2602
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