Path: blob/aarch64-shenandoah-jdk8u272-b10/hotspot/src/cpu/sparc/vm/c1_LIRAssembler_sparc.hpp
32285 views
/*1* Copyright (c) 2000, 2012, Oracle and/or its affiliates. All rights reserved.2* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.3*4* This code is free software; you can redistribute it and/or modify it5* under the terms of the GNU General Public License version 2 only, as6* published by the Free Software Foundation.7*8* This code is distributed in the hope that it will be useful, but WITHOUT9* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or10* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License11* version 2 for more details (a copy is included in the LICENSE file that12* accompanied this code).13*14* You should have received a copy of the GNU General Public License version15* 2 along with this work; if not, write to the Free Software Foundation,16* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.17*18* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA19* or visit www.oracle.com if you need additional information or have any20* questions.21*22*/2324#ifndef CPU_SPARC_VM_C1_LIRASSEMBLER_SPARC_HPP25#define CPU_SPARC_VM_C1_LIRASSEMBLER_SPARC_HPP2627private:2829//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////30//31// Sparc load/store emission32//33// The sparc ld/st instructions cannot accomodate displacements > 13 bits long.34// The following "pseudo" sparc instructions (load/store) make it easier to use the indexed addressing mode35// by allowing 32 bit displacements:36//37// When disp <= 13 bits long, a single load or store instruction is emitted with (disp + [d]).38// When disp > 13 bits long, code is emitted to set the displacement into the O7 register,39// and then a load or store is emitted with ([O7] + [d]).40//4142int store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool wide, bool unaligned);43int store(LIR_Opr from_reg, Register base, Register disp, BasicType type, bool wide);4445int load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool wide, bool unaligned);46int load(Register base, Register disp, LIR_Opr to_reg, BasicType type, bool wide);4748void monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register hdr, int monitor_no);4950int shift_amount(BasicType t);5152static bool is_single_instruction(LIR_Op* op);5354// Record the type of the receiver in ReceiverTypeData55void type_profile_helper(Register mdo, int mdo_offset_bias,56ciMethodData *md, ciProfileData *data,57Register recv, Register tmp1, Label* update_done);58// Setup pointers to MDO, MDO slot, also compute offset bias to access the slot.59void setup_md_access(ciMethod* method, int bci,60ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias);61public:62void pack64(LIR_Opr src, LIR_Opr dst);63void unpack64(LIR_Opr src, LIR_Opr dst);6465enum {66#ifdef _LP6467call_stub_size = 68,68#else69call_stub_size = 20,70#endif // _LP6471exception_handler_size = DEBUG_ONLY(1*K) NOT_DEBUG(128),72deopt_handler_size = DEBUG_ONLY(1*K) NOT_DEBUG(64) };7374#endif // CPU_SPARC_VM_C1_LIRASSEMBLER_SPARC_HPP757677