Path: blob/aarch64-shenandoah-jdk8u272-b10/hotspot/src/cpu/x86/vm/c1_Defs_x86.hpp
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/*1* Copyright (c) 2000, 2010, Oracle and/or its affiliates. All rights reserved.2* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.3*4* This code is free software; you can redistribute it and/or modify it5* under the terms of the GNU General Public License version 2 only, as6* published by the Free Software Foundation.7*8* This code is distributed in the hope that it will be useful, but WITHOUT9* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or10* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License11* version 2 for more details (a copy is included in the LICENSE file that12* accompanied this code).13*14* You should have received a copy of the GNU General Public License version15* 2 along with this work; if not, write to the Free Software Foundation,16* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.17*18* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA19* or visit www.oracle.com if you need additional information or have any20* questions.21*22*/2324#ifndef CPU_X86_VM_C1_DEFS_X86_HPP25#define CPU_X86_VM_C1_DEFS_X86_HPP2627// native word offsets from memory address (little endian)28enum {29pd_lo_word_offset_in_bytes = 0,30pd_hi_word_offset_in_bytes = BytesPerWord31};3233// explicit rounding operations are required to implement the strictFP mode34enum {35pd_strict_fp_requires_explicit_rounding = true36};373839// registers40enum {41pd_nof_cpu_regs_frame_map = RegisterImpl::number_of_registers, // number of registers used during code emission42pd_nof_fpu_regs_frame_map = FloatRegisterImpl::number_of_registers, // number of registers used during code emission43pd_nof_xmm_regs_frame_map = XMMRegisterImpl::number_of_registers, // number of registers used during code emission4445#ifdef _LP6446#define UNALLOCATED 4 // rsp, rbp, r15, r1047#else48#define UNALLOCATED 2 // rsp, rbp49#endif // LP645051pd_nof_caller_save_cpu_regs_frame_map = pd_nof_cpu_regs_frame_map - UNALLOCATED, // number of registers killed by calls52pd_nof_caller_save_fpu_regs_frame_map = pd_nof_fpu_regs_frame_map, // number of registers killed by calls53pd_nof_caller_save_xmm_regs_frame_map = pd_nof_xmm_regs_frame_map, // number of registers killed by calls5455pd_nof_cpu_regs_reg_alloc = pd_nof_caller_save_cpu_regs_frame_map, // number of registers that are visible to register allocator56pd_nof_fpu_regs_reg_alloc = 6, // number of registers that are visible to register allocator5758pd_nof_cpu_regs_linearscan = pd_nof_cpu_regs_frame_map, // number of registers visible to linear scan59pd_nof_fpu_regs_linearscan = pd_nof_fpu_regs_frame_map, // number of registers visible to linear scan60pd_nof_xmm_regs_linearscan = pd_nof_xmm_regs_frame_map, // number of registers visible to linear scan61pd_first_cpu_reg = 0,62pd_last_cpu_reg = NOT_LP64(5) LP64_ONLY(11),63pd_first_byte_reg = NOT_LP64(2) LP64_ONLY(0),64pd_last_byte_reg = NOT_LP64(5) LP64_ONLY(11),65pd_first_fpu_reg = pd_nof_cpu_regs_frame_map,66pd_last_fpu_reg = pd_first_fpu_reg + 7,67pd_first_xmm_reg = pd_nof_cpu_regs_frame_map + pd_nof_fpu_regs_frame_map,68pd_last_xmm_reg = pd_first_xmm_reg + pd_nof_xmm_regs_frame_map - 169};707172// encoding of float value in debug info:73enum {74pd_float_saved_as_double = true75};7677#endif // CPU_X86_VM_C1_DEFS_X86_HPP787980