Path: blob/aarch64-shenandoah-jdk8u272-b10/hotspot/src/cpu/x86/vm/c1_FrameMap_x86.hpp
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/*1* Copyright (c) 1999, 2013, Oracle and/or its affiliates. All rights reserved.2* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.3*4* This code is free software; you can redistribute it and/or modify it5* under the terms of the GNU General Public License version 2 only, as6* published by the Free Software Foundation.7*8* This code is distributed in the hope that it will be useful, but WITHOUT9* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or10* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License11* version 2 for more details (a copy is included in the LICENSE file that12* accompanied this code).13*14* You should have received a copy of the GNU General Public License version15* 2 along with this work; if not, write to the Free Software Foundation,16* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.17*18* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA19* or visit www.oracle.com if you need additional information or have any20* questions.21*22*/2324#ifndef CPU_X86_VM_C1_FRAMEMAP_X86_HPP25#define CPU_X86_VM_C1_FRAMEMAP_X86_HPP2627// On i486 the frame looks as follows:28//29// +-----------------------------+---------+----------------------------------------+----------------+-----------30// | size_arguments-nof_reg_args | 2 words | size_locals-size_arguments+numreg_args | _size_monitors | spilling .31// +-----------------------------+---------+----------------------------------------+----------------+-----------32//33// The FPU registers are mapped with their offset from TOS; therefore the34// status of FPU stack must be updated during code emission.3536public:37static const int pd_c_runtime_reserved_arg_size;3839enum {40nof_xmm_regs = pd_nof_xmm_regs_frame_map,41nof_caller_save_xmm_regs = pd_nof_caller_save_xmm_regs_frame_map,42first_available_sp_in_frame = 0,43#ifndef _LP6444frame_pad_in_bytes = 8,45nof_reg_args = 246#else47frame_pad_in_bytes = 16,48nof_reg_args = 649#endif // _LP6450};5152private:53static LIR_Opr _caller_save_xmm_regs [nof_caller_save_xmm_regs];5455static XMMRegister _xmm_regs[nof_xmm_regs];5657public:58static LIR_Opr receiver_opr;5960static LIR_Opr rsi_opr;61static LIR_Opr rdi_opr;62static LIR_Opr rbx_opr;63static LIR_Opr rax_opr;64static LIR_Opr rdx_opr;65static LIR_Opr rcx_opr;66static LIR_Opr rsp_opr;67static LIR_Opr rbp_opr;6869static LIR_Opr rsi_oop_opr;70static LIR_Opr rdi_oop_opr;71static LIR_Opr rbx_oop_opr;72static LIR_Opr rax_oop_opr;73static LIR_Opr rdx_oop_opr;74static LIR_Opr rcx_oop_opr;7576static LIR_Opr rsi_metadata_opr;77static LIR_Opr rdi_metadata_opr;78static LIR_Opr rbx_metadata_opr;79static LIR_Opr rax_metadata_opr;80static LIR_Opr rdx_metadata_opr;81static LIR_Opr rcx_metadata_opr;8283#ifdef _LP648485static LIR_Opr r8_opr;86static LIR_Opr r9_opr;87static LIR_Opr r10_opr;88static LIR_Opr r11_opr;89static LIR_Opr r12_opr;90static LIR_Opr r13_opr;91static LIR_Opr r14_opr;92static LIR_Opr r15_opr;9394static LIR_Opr r8_oop_opr;95static LIR_Opr r9_oop_opr;9697static LIR_Opr r11_oop_opr;98static LIR_Opr r12_oop_opr;99static LIR_Opr r13_oop_opr;100static LIR_Opr r14_oop_opr;101102static LIR_Opr r8_metadata_opr;103static LIR_Opr r9_metadata_opr;104105static LIR_Opr r11_metadata_opr;106static LIR_Opr r12_metadata_opr;107static LIR_Opr r13_metadata_opr;108static LIR_Opr r14_metadata_opr;109110#endif // _LP64111112static LIR_Opr long0_opr;113static LIR_Opr long1_opr;114static LIR_Opr fpu0_float_opr;115static LIR_Opr fpu0_double_opr;116static LIR_Opr xmm0_float_opr;117static LIR_Opr xmm0_double_opr;118119#ifdef _LP64120static LIR_Opr as_long_opr(Register r) {121return LIR_OprFact::double_cpu(cpu_reg2rnr(r), cpu_reg2rnr(r));122}123static LIR_Opr as_pointer_opr(Register r) {124return LIR_OprFact::double_cpu(cpu_reg2rnr(r), cpu_reg2rnr(r));125}126#else127static LIR_Opr as_long_opr(Register r, Register r2) {128return LIR_OprFact::double_cpu(cpu_reg2rnr(r), cpu_reg2rnr(r2));129}130static LIR_Opr as_pointer_opr(Register r) {131return LIR_OprFact::single_cpu(cpu_reg2rnr(r));132}133#endif // _LP64134135// VMReg name for spilled physical FPU stack slot n136static VMReg fpu_regname (int n);137138static XMMRegister nr2xmmreg(int rnr);139140static bool is_caller_save_register (LIR_Opr opr) { return true; }141static bool is_caller_save_register (Register r) { return true; }142143static LIR_Opr caller_save_xmm_reg_at(int i) {144assert(i >= 0 && i < nof_caller_save_xmm_regs, "out of bounds");145return _caller_save_xmm_regs[i];146}147148static int adjust_reg_range(int range) {149// Reduce the number of available regs (to free r12) in case of compressed oops150if (UseCompressedOops || UseCompressedClassPointers) return range - 1;151return range;152}153154static int nof_caller_save_cpu_regs() { return adjust_reg_range(pd_nof_caller_save_cpu_regs_frame_map); }155static int last_cpu_reg() { return adjust_reg_range(pd_last_cpu_reg); }156static int last_byte_reg() { return adjust_reg_range(pd_last_byte_reg); }157158#endif // CPU_X86_VM_C1_FRAMEMAP_X86_HPP159160161162