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PojavLauncherTeam
GitHub Repository: PojavLauncherTeam/openjdk-multiarch-jdk8u
 Path: blob/aarch64-shenandoah-jdk8u272-b10/hotspot/src/os_cpu/solaris_sparc/vm/solaris_sparc.s
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!!

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!! Copyright (c) 2005, 2013, Oracle and/or its affiliates. All rights reserved.

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!! DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.

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!!

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!! This code is free software; you can redistribute it and/or modify it

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!! under the terms of the GNU General Public License version 2 only, as

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!! published by the Free Software Foundation.

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!!

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!! This code is distributed in the hope that it will be useful, but WITHOUT

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!! ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

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!! FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

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!! version 2 for more details (a copy is included in the LICENSE file that

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!! accompanied this code).

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!!

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!! You should have received a copy of the GNU General Public License version

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!! 2 along with this work; if not, write to the Free Software Foundation,

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!! Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.

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!!

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!! Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA

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!! or visit www.oracle.com if you need additional information or have any

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!! questions.

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!!

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    !! Possibilities:

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    !! -- membar

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    !! -- CAS (SP + BIAS, G0, G0)

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    !! -- wr %g0, %asi

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    .global SpinPause

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    .align  32

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SpinPause:

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    retl

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    mov %g0, %o0

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    .globl _Copy_conjoint_jlongs_atomic

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    .align 32

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    .global   _Copy_conjoint_jlongs_atomic

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 _Copy_conjoint_jlongs_atomic:

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         cmp     %o0, %o1

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         bleu    4f

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         sll     %o2, 3, %o4

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         ba      2f

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    1:

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         subcc   %o4, 8, %o4

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         std     %o2, [%o1]

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         add     %o0, 8, %o0

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         add     %o1, 8, %o1

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    2:

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         bge,a   1b

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         ldd     [%o0], %o2

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         ba      5f

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         nop

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    3:

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         std     %o2, [%o1+%o4]

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    4:

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         subcc   %o4, 8, %o4

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         bge,a   3b

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         ldd     [%o0+%o4], %o2

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    5:      

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         retl

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         nop

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    .globl _raw_thread_id

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    .align 32

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 _raw_thread_id:

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    .register %g7, #scratch

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        retl

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        mov     %g7, %o0

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    .globl _flush_reg_windows

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    .align 32

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 _flush_reg_windows:

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        ta 0x03

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        retl

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        mov     %fp, %o0

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