Path: blob/master/3rdparty/libwebp/src/dsp/enc_mips_dsp_r2.c
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// Copyright 2014 Google Inc. All Rights Reserved.1//2// Use of this source code is governed by a BSD-style license3// that can be found in the COPYING file in the root of the source4// tree. An additional intellectual property rights grant can be found5// in the file PATENTS. All contributing project authors may6// be found in the AUTHORS file in the root of the source tree.7// -----------------------------------------------------------------------------8//9// MIPS version of speed-critical encoding functions.10//11// Author(s): Darko Laus ([email protected])12// Mirko Raus ([email protected])1314#include "src/dsp/dsp.h"1516#if defined(WEBP_USE_MIPS_DSP_R2)1718#include "src/dsp/mips_macro.h"19#include "src/enc/cost_enc.h"20#include "src/enc/vp8i_enc.h"2122static const int kC1 = 20091 + (1 << 16);23static const int kC2 = 35468;2425// O - output26// I - input (macro doesn't change it)27#define ADD_SUB_HALVES_X4(O0, O1, O2, O3, O4, O5, O6, O7, \28I0, I1, I2, I3, I4, I5, I6, I7) \29"addq.ph %[" #O0 "], %[" #I0 "], %[" #I1 "] \n\t" \30"subq.ph %[" #O1 "], %[" #I0 "], %[" #I1 "] \n\t" \31"addq.ph %[" #O2 "], %[" #I2 "], %[" #I3 "] \n\t" \32"subq.ph %[" #O3 "], %[" #I2 "], %[" #I3 "] \n\t" \33"addq.ph %[" #O4 "], %[" #I4 "], %[" #I5 "] \n\t" \34"subq.ph %[" #O5 "], %[" #I4 "], %[" #I5 "] \n\t" \35"addq.ph %[" #O6 "], %[" #I6 "], %[" #I7 "] \n\t" \36"subq.ph %[" #O7 "], %[" #I6 "], %[" #I7 "] \n\t"3738// IO - input/output39#define ABS_X8(IO0, IO1, IO2, IO3, IO4, IO5, IO6, IO7) \40"absq_s.ph %[" #IO0 "], %[" #IO0 "] \n\t" \41"absq_s.ph %[" #IO1 "], %[" #IO1 "] \n\t" \42"absq_s.ph %[" #IO2 "], %[" #IO2 "] \n\t" \43"absq_s.ph %[" #IO3 "], %[" #IO3 "] \n\t" \44"absq_s.ph %[" #IO4 "], %[" #IO4 "] \n\t" \45"absq_s.ph %[" #IO5 "], %[" #IO5 "] \n\t" \46"absq_s.ph %[" #IO6 "], %[" #IO6 "] \n\t" \47"absq_s.ph %[" #IO7 "], %[" #IO7 "] \n\t"4849// dpa.w.ph $ac0 temp0 ,temp150// $ac += temp0[31..16] * temp1[31..16] + temp0[15..0] * temp1[15..0]51// dpax.w.ph $ac0 temp0 ,temp152// $ac += temp0[31..16] * temp1[15..0] + temp0[15..0] * temp1[31..16]53// O - output54// I - input (macro doesn't change it)55#define MUL_HALF(O0, I0, I1, I2, I3, I4, I5, I6, I7, \56I8, I9, I10, I11, I12, I13, I14, I15) \57"mult $ac0, $zero, $zero \n\t" \58"dpa.w.ph $ac0, %[" #I2 "], %[" #I0 "] \n\t" \59"dpax.w.ph $ac0, %[" #I5 "], %[" #I6 "] \n\t" \60"dpa.w.ph $ac0, %[" #I8 "], %[" #I9 "] \n\t" \61"dpax.w.ph $ac0, %[" #I11 "], %[" #I4 "] \n\t" \62"dpa.w.ph $ac0, %[" #I12 "], %[" #I7 "] \n\t" \63"dpax.w.ph $ac0, %[" #I13 "], %[" #I1 "] \n\t" \64"dpa.w.ph $ac0, %[" #I14 "], %[" #I3 "] \n\t" \65"dpax.w.ph $ac0, %[" #I15 "], %[" #I10 "] \n\t" \66"mflo %[" #O0 "], $ac0 \n\t"6768#define OUTPUT_EARLY_CLOBBER_REGS_17() \69OUTPUT_EARLY_CLOBBER_REGS_10(), \70[temp11]"=&r"(temp11), [temp12]"=&r"(temp12), [temp13]"=&r"(temp13), \71[temp14]"=&r"(temp14), [temp15]"=&r"(temp15), [temp16]"=&r"(temp16), \72[temp17]"=&r"(temp17)7374// macro for one horizontal pass in FTransform75// temp0..temp15 holds tmp[0]..tmp[15]76// A - offset in bytes to load from src and ref buffers77// TEMP0..TEMP3 - registers for corresponding tmp elements78#define HORIZONTAL_PASS(A, TEMP0, TEMP1, TEMP2, TEMP3) \79"lw %[" #TEMP0 "], 0(%[args]) \n\t" \80"lw %[" #TEMP1 "], 4(%[args]) \n\t" \81"lw %[" #TEMP2 "], " XSTR(BPS) "*" #A "(%[" #TEMP0 "]) \n\t" \82"lw %[" #TEMP3 "], " XSTR(BPS) "*" #A "(%[" #TEMP1 "]) \n\t" \83"preceu.ph.qbl %[" #TEMP0 "], %[" #TEMP2 "] \n\t" \84"preceu.ph.qbl %[" #TEMP1 "], %[" #TEMP3 "] \n\t" \85"preceu.ph.qbr %[" #TEMP2 "], %[" #TEMP2 "] \n\t" \86"preceu.ph.qbr %[" #TEMP3 "], %[" #TEMP3 "] \n\t" \87"subq.ph %[" #TEMP0 "], %[" #TEMP0 "], %[" #TEMP1 "] \n\t" \88"subq.ph %[" #TEMP2 "], %[" #TEMP2 "], %[" #TEMP3 "] \n\t" \89"rotr %[" #TEMP0 "], %[" #TEMP0 "], 16 \n\t" \90"addq.ph %[" #TEMP1 "], %[" #TEMP2 "], %[" #TEMP0 "] \n\t" \91"subq.ph %[" #TEMP3 "], %[" #TEMP2 "], %[" #TEMP0 "] \n\t" \92"seh %[" #TEMP0 "], %[" #TEMP1 "] \n\t" \93"sra %[temp16], %[" #TEMP1 "], 16 \n\t" \94"seh %[temp19], %[" #TEMP3 "] \n\t" \95"sra %[" #TEMP3 "], %[" #TEMP3 "], 16 \n\t" \96"subu %[" #TEMP2 "], %[" #TEMP0 "], %[temp16] \n\t" \97"addu %[" #TEMP0 "], %[" #TEMP0 "], %[temp16] \n\t" \98"mul %[temp17], %[temp19], %[c2217] \n\t" \99"mul %[temp18], %[" #TEMP3 "], %[c5352] \n\t" \100"mul %[" #TEMP1 "], %[temp19], %[c5352] \n\t" \101"mul %[temp16], %[" #TEMP3 "], %[c2217] \n\t" \102"sll %[" #TEMP2 "], %[" #TEMP2 "], 3 \n\t" \103"sll %[" #TEMP0 "], %[" #TEMP0 "], 3 \n\t" \104"subu %[" #TEMP3 "], %[temp17], %[temp18] \n\t" \105"addu %[" #TEMP1 "], %[temp16], %[" #TEMP1 "] \n\t" \106"addiu %[" #TEMP3 "], %[" #TEMP3 "], 937 \n\t" \107"addiu %[" #TEMP1 "], %[" #TEMP1 "], 1812 \n\t" \108"sra %[" #TEMP3 "], %[" #TEMP3 "], 9 \n\t" \109"sra %[" #TEMP1 "], %[" #TEMP1 "], 9 \n\t"110111// macro for one vertical pass in FTransform112// temp0..temp15 holds tmp[0]..tmp[15]113// A..D - offsets in bytes to store to out buffer114// TEMP0, TEMP4, TEMP8 and TEMP12 - registers for corresponding tmp elements115#define VERTICAL_PASS(A, B, C, D, TEMP0, TEMP4, TEMP8, TEMP12) \116"addu %[temp16], %[" #TEMP0 "], %[" #TEMP12 "] \n\t" \117"subu %[temp19], %[" #TEMP0 "], %[" #TEMP12 "] \n\t" \118"addu %[temp17], %[" #TEMP4 "], %[" #TEMP8 "] \n\t" \119"subu %[temp18], %[" #TEMP4 "], %[" #TEMP8 "] \n\t" \120"mul %[" #TEMP8 "], %[temp19], %[c2217] \n\t" \121"mul %[" #TEMP12 "], %[temp18], %[c2217] \n\t" \122"mul %[" #TEMP4 "], %[temp19], %[c5352] \n\t" \123"mul %[temp18], %[temp18], %[c5352] \n\t" \124"addiu %[temp16], %[temp16], 7 \n\t" \125"addu %[" #TEMP0 "], %[temp16], %[temp17] \n\t" \126"sra %[" #TEMP0 "], %[" #TEMP0 "], 4 \n\t" \127"addu %[" #TEMP12 "], %[" #TEMP12 "], %[" #TEMP4 "] \n\t" \128"subu %[" #TEMP4 "], %[temp16], %[temp17] \n\t" \129"sra %[" #TEMP4 "], %[" #TEMP4 "], 4 \n\t" \130"addiu %[" #TEMP8 "], %[" #TEMP8 "], 30000 \n\t" \131"addiu %[" #TEMP12 "], %[" #TEMP12 "], 12000 \n\t" \132"addiu %[" #TEMP8 "], %[" #TEMP8 "], 21000 \n\t" \133"subu %[" #TEMP8 "], %[" #TEMP8 "], %[temp18] \n\t" \134"sra %[" #TEMP12 "], %[" #TEMP12 "], 16 \n\t" \135"sra %[" #TEMP8 "], %[" #TEMP8 "], 16 \n\t" \136"addiu %[temp16], %[" #TEMP12 "], 1 \n\t" \137"movn %[" #TEMP12 "], %[temp16], %[temp19] \n\t" \138"sh %[" #TEMP0 "], " #A "(%[temp20]) \n\t" \139"sh %[" #TEMP4 "], " #C "(%[temp20]) \n\t" \140"sh %[" #TEMP8 "], " #D "(%[temp20]) \n\t" \141"sh %[" #TEMP12 "], " #B "(%[temp20]) \n\t"142143static void FTransform_MIPSdspR2(const uint8_t* src, const uint8_t* ref,144int16_t* out) {145const int c2217 = 2217;146const int c5352 = 5352;147int temp0, temp1, temp2, temp3, temp4, temp5, temp6, temp7, temp8;148int temp9, temp10, temp11, temp12, temp13, temp14, temp15, temp16;149int temp17, temp18, temp19, temp20;150const int* const args[3] =151{ (const int*)src, (const int*)ref, (const int*)out };152153__asm__ volatile (154HORIZONTAL_PASS(0, temp0, temp1, temp2, temp3)155HORIZONTAL_PASS(1, temp4, temp5, temp6, temp7)156HORIZONTAL_PASS(2, temp8, temp9, temp10, temp11)157HORIZONTAL_PASS(3, temp12, temp13, temp14, temp15)158"lw %[temp20], 8(%[args]) \n\t"159VERTICAL_PASS(0, 8, 16, 24, temp0, temp4, temp8, temp12)160VERTICAL_PASS(2, 10, 18, 26, temp1, temp5, temp9, temp13)161VERTICAL_PASS(4, 12, 20, 28, temp2, temp6, temp10, temp14)162VERTICAL_PASS(6, 14, 22, 30, temp3, temp7, temp11, temp15)163OUTPUT_EARLY_CLOBBER_REGS_18(),164[temp0]"=&r"(temp0), [temp19]"=&r"(temp19), [temp20]"=&r"(temp20)165: [args]"r"(args), [c2217]"r"(c2217), [c5352]"r"(c5352)166: "memory", "hi", "lo"167);168}169170#undef VERTICAL_PASS171#undef HORIZONTAL_PASS172173static WEBP_INLINE void ITransformOne(const uint8_t* ref, const int16_t* in,174uint8_t* dst) {175int temp1, temp2, temp3, temp4, temp5, temp6, temp7, temp8, temp9;176int temp10, temp11, temp12, temp13, temp14, temp15, temp16, temp17, temp18;177178__asm__ volatile (179"ulw %[temp1], 0(%[in]) \n\t"180"ulw %[temp2], 16(%[in]) \n\t"181LOAD_IN_X2(temp5, temp6, 24, 26)182ADD_SUB_HALVES(temp3, temp4, temp1, temp2)183LOAD_IN_X2(temp1, temp2, 8, 10)184MUL_SHIFT_SUM(temp7, temp8, temp9, temp10, temp11, temp12, temp13, temp14,185temp10, temp8, temp9, temp7, temp1, temp2, temp5, temp6,186temp13, temp11, temp14, temp12)187INSERT_HALF_X2(temp8, temp7, temp10, temp9)188"ulw %[temp17], 4(%[in]) \n\t"189"ulw %[temp18], 20(%[in]) \n\t"190ADD_SUB_HALVES(temp1, temp2, temp3, temp8)191ADD_SUB_HALVES(temp5, temp6, temp4, temp7)192ADD_SUB_HALVES(temp7, temp8, temp17, temp18)193LOAD_IN_X2(temp17, temp18, 12, 14)194LOAD_IN_X2(temp9, temp10, 28, 30)195MUL_SHIFT_SUM(temp11, temp12, temp13, temp14, temp15, temp16, temp4, temp17,196temp12, temp14, temp11, temp13, temp17, temp18, temp9, temp10,197temp15, temp4, temp16, temp17)198INSERT_HALF_X2(temp11, temp12, temp13, temp14)199ADD_SUB_HALVES(temp17, temp8, temp8, temp11)200ADD_SUB_HALVES(temp3, temp4, temp7, temp12)201202// horizontal203SRA_16(temp9, temp10, temp11, temp12, temp1, temp2, temp5, temp6)204INSERT_HALF_X2(temp1, temp6, temp5, temp2)205SRA_16(temp13, temp14, temp15, temp16, temp3, temp4, temp17, temp8)206"repl.ph %[temp2], 0x4 \n\t"207INSERT_HALF_X2(temp3, temp8, temp17, temp4)208"addq.ph %[temp1], %[temp1], %[temp2] \n\t"209"addq.ph %[temp6], %[temp6], %[temp2] \n\t"210ADD_SUB_HALVES(temp2, temp4, temp1, temp3)211ADD_SUB_HALVES(temp5, temp7, temp6, temp8)212MUL_SHIFT_SUM(temp1, temp3, temp6, temp8, temp9, temp13, temp17, temp18,213temp3, temp13, temp1, temp9, temp9, temp13, temp11, temp15,214temp6, temp17, temp8, temp18)215MUL_SHIFT_SUM(temp6, temp8, temp18, temp17, temp11, temp15, temp12, temp16,216temp8, temp15, temp6, temp11, temp12, temp16, temp10, temp14,217temp18, temp12, temp17, temp16)218INSERT_HALF_X2(temp1, temp3, temp9, temp13)219INSERT_HALF_X2(temp6, temp8, temp11, temp15)220SHIFT_R_SUM_X2(temp9, temp10, temp11, temp12, temp13, temp14, temp15,221temp16, temp2, temp4, temp5, temp7, temp3, temp1, temp8,222temp6)223PACK_2_HALVES_TO_WORD(temp1, temp2, temp3, temp4, temp9, temp12, temp13,224temp16, temp11, temp10, temp15, temp14)225LOAD_WITH_OFFSET_X4(temp10, temp11, temp14, temp15, ref,2260, 0, 0, 0,2270, 1, 2, 3,228BPS)229CONVERT_2_BYTES_TO_HALF(temp5, temp6, temp7, temp8, temp17, temp18, temp10,230temp11, temp10, temp11, temp14, temp15)231STORE_SAT_SUM_X2(temp5, temp6, temp7, temp8, temp17, temp18, temp10, temp11,232temp9, temp12, temp1, temp2, temp13, temp16, temp3, temp4,233dst, 0, 1, 2, 3, BPS)234235OUTPUT_EARLY_CLOBBER_REGS_18()236: [dst]"r"(dst), [in]"r"(in), [kC1]"r"(kC1), [kC2]"r"(kC2), [ref]"r"(ref)237: "memory", "hi", "lo"238);239}240241static void ITransform_MIPSdspR2(const uint8_t* ref, const int16_t* in,242uint8_t* dst, int do_two) {243ITransformOne(ref, in, dst);244if (do_two) {245ITransformOne(ref + 4, in + 16, dst + 4);246}247}248249static int Disto4x4_MIPSdspR2(const uint8_t* const a, const uint8_t* const b,250const uint16_t* const w) {251int temp1, temp2, temp3, temp4, temp5, temp6, temp7, temp8, temp9;252int temp10, temp11, temp12, temp13, temp14, temp15, temp16, temp17;253254__asm__ volatile (255LOAD_WITH_OFFSET_X4(temp1, temp2, temp3, temp4, a,2560, 0, 0, 0,2570, 1, 2, 3,258BPS)259CONVERT_2_BYTES_TO_HALF(temp5, temp6, temp7, temp8, temp9,temp10, temp11,260temp12, temp1, temp2, temp3, temp4)261ADD_SUB_HALVES_X4(temp1, temp2, temp3, temp4, temp5, temp6, temp7, temp8,262temp5, temp6, temp7, temp8, temp9, temp10, temp11, temp12)263PACK_2_HALVES_TO_WORD(temp9, temp10, temp11, temp12, temp1, temp3, temp5,264temp7, temp2, temp4, temp6, temp8)265ADD_SUB_HALVES_X4(temp2, temp4, temp6, temp8, temp9, temp1, temp3, temp10,266temp1, temp9, temp3, temp10, temp5, temp11, temp7, temp12)267ADD_SUB_HALVES_X4(temp5, temp11, temp7, temp2, temp9, temp3, temp6, temp12,268temp2, temp9, temp6, temp3, temp4, temp1, temp8, temp10)269ADD_SUB_HALVES_X4(temp1, temp4, temp10, temp8, temp7, temp11, temp5, temp2,270temp5, temp7, temp11, temp2, temp9, temp6, temp3, temp12)271ABS_X8(temp1, temp4, temp10, temp8, temp7, temp11, temp5, temp2)272LOAD_WITH_OFFSET_X4(temp3, temp6, temp9, temp12, w,2730, 4, 8, 12,2740, 0, 0, 0,2750)276LOAD_WITH_OFFSET_X4(temp13, temp14, temp15, temp16, w,2770, 4, 8, 12,2781, 1, 1, 1,27916)280MUL_HALF(temp17, temp1, temp2, temp3, temp4, temp5, temp6, temp7, temp8,281temp9, temp10, temp11, temp12, temp13, temp14, temp15, temp16)282LOAD_WITH_OFFSET_X4(temp1, temp2, temp3, temp4, b,2830, 0, 0, 0,2840, 1, 2, 3,285BPS)286CONVERT_2_BYTES_TO_HALF(temp5,temp6, temp7, temp8, temp9,temp10, temp11,287temp12, temp1, temp2, temp3, temp4)288ADD_SUB_HALVES_X4(temp1, temp2, temp3, temp4, temp5, temp6, temp7, temp8,289temp5, temp6, temp7, temp8, temp9, temp10, temp11, temp12)290PACK_2_HALVES_TO_WORD(temp9, temp10, temp11, temp12, temp1, temp3, temp5,291temp7, temp2, temp4, temp6, temp8)292ADD_SUB_HALVES_X4(temp2, temp4, temp6, temp8, temp9, temp1, temp3, temp10,293temp1, temp9, temp3, temp10, temp5, temp11, temp7, temp12)294ADD_SUB_HALVES_X4(temp5, temp11, temp7, temp2, temp9, temp3, temp6, temp12,295temp2, temp9, temp6, temp3, temp4, temp1, temp8, temp10)296ADD_SUB_HALVES_X4(temp1, temp4, temp10, temp8, temp7, temp11, temp5, temp2,297temp5, temp7, temp11, temp2, temp9, temp6, temp3, temp12)298ABS_X8(temp1, temp4, temp10, temp8, temp7, temp11, temp5, temp2)299LOAD_WITH_OFFSET_X4(temp3, temp6, temp9, temp12, w,3000, 4, 8, 12,3010, 0, 0, 0,3020)303LOAD_WITH_OFFSET_X4(temp13, temp14, temp15, temp16, w,3040, 4, 8, 12,3051, 1, 1, 1,30616)307MUL_HALF(temp3, temp1, temp2, temp3, temp4, temp5, temp6, temp7, temp8,308temp9, temp10, temp11, temp12, temp13, temp14, temp15, temp16)309OUTPUT_EARLY_CLOBBER_REGS_17()310: [a]"r"(a), [b]"r"(b), [w]"r"(w)311: "memory", "hi", "lo"312);313return abs(temp3 - temp17) >> 5;314}315316static int Disto16x16_MIPSdspR2(const uint8_t* const a,317const uint8_t* const b,318const uint16_t* const w) {319int D = 0;320int x, y;321for (y = 0; y < 16 * BPS; y += 4 * BPS) {322for (x = 0; x < 16; x += 4) {323D += Disto4x4_MIPSdspR2(a + x + y, b + x + y, w);324}325}326return D;327}328329//------------------------------------------------------------------------------330// Intra predictions331332#define FILL_PART(J, SIZE) \333"usw %[value], 0+" #J "*" XSTR(BPS) "(%[dst]) \n\t" \334"usw %[value], 4+" #J "*" XSTR(BPS) "(%[dst]) \n\t" \335".if " #SIZE " == 16 \n\t" \336"usw %[value], 8+" #J "*" XSTR(BPS) "(%[dst]) \n\t" \337"usw %[value], 12+" #J "*" XSTR(BPS) "(%[dst]) \n\t" \338".endif \n\t"339340#define FILL_8_OR_16(DST, VALUE, SIZE) do { \341int value = (VALUE); \342__asm__ volatile ( \343"replv.qb %[value], %[value] \n\t" \344FILL_PART( 0, SIZE) \345FILL_PART( 1, SIZE) \346FILL_PART( 2, SIZE) \347FILL_PART( 3, SIZE) \348FILL_PART( 4, SIZE) \349FILL_PART( 5, SIZE) \350FILL_PART( 6, SIZE) \351FILL_PART( 7, SIZE) \352".if " #SIZE " == 16 \n\t" \353FILL_PART( 8, 16) \354FILL_PART( 9, 16) \355FILL_PART(10, 16) \356FILL_PART(11, 16) \357FILL_PART(12, 16) \358FILL_PART(13, 16) \359FILL_PART(14, 16) \360FILL_PART(15, 16) \361".endif \n\t" \362: [value]"+&r"(value) \363: [dst]"r"((DST)) \364: "memory" \365); \366} while (0)367368#define VERTICAL_PRED(DST, TOP, SIZE) \369static WEBP_INLINE void VerticalPred##SIZE(uint8_t* (DST), \370const uint8_t* (TOP)) { \371int j; \372if ((TOP)) { \373for (j = 0; j < (SIZE); ++j) memcpy((DST) + j * BPS, (TOP), (SIZE)); \374} else { \375FILL_8_OR_16((DST), 127, (SIZE)); \376} \377}378379VERTICAL_PRED(dst, top, 8)380VERTICAL_PRED(dst, top, 16)381382#undef VERTICAL_PRED383384#define HORIZONTAL_PRED(DST, LEFT, SIZE) \385static WEBP_INLINE void HorizontalPred##SIZE(uint8_t* (DST), \386const uint8_t* (LEFT)) { \387if (LEFT) { \388int j; \389for (j = 0; j < (SIZE); ++j) { \390memset((DST) + j * BPS, (LEFT)[j], (SIZE)); \391} \392} else { \393FILL_8_OR_16((DST), 129, (SIZE)); \394} \395}396397HORIZONTAL_PRED(dst, left, 8)398HORIZONTAL_PRED(dst, left, 16)399400#undef HORIZONTAL_PRED401402#define CLIPPING() \403"preceu.ph.qbl %[temp2], %[temp0] \n\t" \404"preceu.ph.qbr %[temp0], %[temp0] \n\t" \405"preceu.ph.qbl %[temp3], %[temp1] \n\t" \406"preceu.ph.qbr %[temp1], %[temp1] \n\t" \407"addu.ph %[temp2], %[temp2], %[leftY_1] \n\t" \408"addu.ph %[temp0], %[temp0], %[leftY_1] \n\t" \409"addu.ph %[temp3], %[temp3], %[leftY_1] \n\t" \410"addu.ph %[temp1], %[temp1], %[leftY_1] \n\t" \411"shll_s.ph %[temp2], %[temp2], 7 \n\t" \412"shll_s.ph %[temp0], %[temp0], 7 \n\t" \413"shll_s.ph %[temp3], %[temp3], 7 \n\t" \414"shll_s.ph %[temp1], %[temp1], 7 \n\t" \415"precrqu_s.qb.ph %[temp0], %[temp2], %[temp0] \n\t" \416"precrqu_s.qb.ph %[temp1], %[temp3], %[temp1] \n\t"417418#define CLIP_8B_TO_DST(DST, LEFT, TOP, SIZE) do { \419int leftY_1 = ((int)(LEFT)[y] << 16) + (LEFT)[y]; \420int temp0, temp1, temp2, temp3; \421__asm__ volatile ( \422"replv.ph %[leftY_1], %[leftY_1] \n\t" \423"ulw %[temp0], 0(%[top]) \n\t" \424"ulw %[temp1], 4(%[top]) \n\t" \425"subu.ph %[leftY_1], %[leftY_1], %[left_1] \n\t" \426CLIPPING() \427"usw %[temp0], 0(%[dst]) \n\t" \428"usw %[temp1], 4(%[dst]) \n\t" \429".if " #SIZE " == 16 \n\t" \430"ulw %[temp0], 8(%[top]) \n\t" \431"ulw %[temp1], 12(%[top]) \n\t" \432CLIPPING() \433"usw %[temp0], 8(%[dst]) \n\t" \434"usw %[temp1], 12(%[dst]) \n\t" \435".endif \n\t" \436: [leftY_1]"+&r"(leftY_1), [temp0]"=&r"(temp0), [temp1]"=&r"(temp1), \437[temp2]"=&r"(temp2), [temp3]"=&r"(temp3) \438: [left_1]"r"(left_1), [top]"r"((TOP)), [dst]"r"((DST)) \439: "memory" \440); \441} while (0)442443#define CLIP_TO_DST(DST, LEFT, TOP, SIZE) do { \444int y; \445const int left_1 = ((int)(LEFT)[-1] << 16) + (LEFT)[-1]; \446for (y = 0; y < (SIZE); ++y) { \447CLIP_8B_TO_DST((DST), (LEFT), (TOP), (SIZE)); \448(DST) += BPS; \449} \450} while (0)451452#define TRUE_MOTION(DST, LEFT, TOP, SIZE) \453static WEBP_INLINE void TrueMotion##SIZE(uint8_t* (DST), const uint8_t* (LEFT),\454const uint8_t* (TOP)) { \455if ((LEFT) != NULL) { \456if ((TOP) != NULL) { \457CLIP_TO_DST((DST), (LEFT), (TOP), (SIZE)); \458} else { \459HorizontalPred##SIZE((DST), (LEFT)); \460} \461} else { \462/* true motion without left samples (hence: with default 129 value) */ \463/* is equivalent to VE prediction where you just copy the top samples. */ \464/* Note that if top samples are not available, the default value is */ \465/* then 129, and not 127 as in the VerticalPred case. */ \466if ((TOP) != NULL) { \467VerticalPred##SIZE((DST), (TOP)); \468} else { \469FILL_8_OR_16((DST), 129, (SIZE)); \470} \471} \472}473474TRUE_MOTION(dst, left, top, 8)475TRUE_MOTION(dst, left, top, 16)476477#undef TRUE_MOTION478#undef CLIP_TO_DST479#undef CLIP_8B_TO_DST480#undef CLIPPING481482static WEBP_INLINE void DCMode16(uint8_t* dst, const uint8_t* left,483const uint8_t* top) {484int DC, DC1;485int temp0, temp1, temp2, temp3;486487__asm__ volatile(488"beqz %[top], 2f \n\t"489LOAD_WITH_OFFSET_X4(temp0, temp1, temp2, temp3, top,4900, 4, 8, 12,4910, 0, 0, 0,4920)493"raddu.w.qb %[temp0], %[temp0] \n\t"494"raddu.w.qb %[temp1], %[temp1] \n\t"495"raddu.w.qb %[temp2], %[temp2] \n\t"496"raddu.w.qb %[temp3], %[temp3] \n\t"497"addu %[temp0], %[temp0], %[temp1] \n\t"498"addu %[temp2], %[temp2], %[temp3] \n\t"499"addu %[DC], %[temp0], %[temp2] \n\t"500"move %[DC1], %[DC] \n\t"501"beqz %[left], 1f \n\t"502LOAD_WITH_OFFSET_X4(temp0, temp1, temp2, temp3, left,5030, 4, 8, 12,5040, 0, 0, 0,5050)506"raddu.w.qb %[temp0], %[temp0] \n\t"507"raddu.w.qb %[temp1], %[temp1] \n\t"508"raddu.w.qb %[temp2], %[temp2] \n\t"509"raddu.w.qb %[temp3], %[temp3] \n\t"510"addu %[temp0], %[temp0], %[temp1] \n\t"511"addu %[temp2], %[temp2], %[temp3] \n\t"512"addu %[DC1], %[temp0], %[temp2] \n\t"513"1: \n\t"514"addu %[DC], %[DC], %[DC1] \n\t"515"j 3f \n\t"516"2: \n\t"517"beqz %[left], 4f \n\t"518LOAD_WITH_OFFSET_X4(temp0, temp1, temp2, temp3, left,5190, 4, 8, 12,5200, 0, 0, 0,5210)522"raddu.w.qb %[temp0], %[temp0] \n\t"523"raddu.w.qb %[temp1], %[temp1] \n\t"524"raddu.w.qb %[temp2], %[temp2] \n\t"525"raddu.w.qb %[temp3], %[temp3] \n\t"526"addu %[temp0], %[temp0], %[temp1] \n\t"527"addu %[temp2], %[temp2], %[temp3] \n\t"528"addu %[DC], %[temp0], %[temp2] \n\t"529"addu %[DC], %[DC], %[DC] \n\t"530"3: \n\t"531"shra_r.w %[DC], %[DC], 5 \n\t"532"j 5f \n\t"533"4: \n\t"534"li %[DC], 0x80 \n\t"535"5: \n\t"536: [temp0]"=&r"(temp0), [temp1]"=&r"(temp1), [DC]"=&r"(DC),537[temp2]"=&r"(temp2), [temp3]"=&r"(temp3), [DC1]"=&r"(DC1)538: [left]"r"(left), [top]"r"(top)539: "memory"540);541542FILL_8_OR_16(dst, DC, 16);543}544545static WEBP_INLINE void DCMode8(uint8_t* dst, const uint8_t* left,546const uint8_t* top) {547int DC, DC1;548int temp0, temp1, temp2, temp3;549550__asm__ volatile(551"beqz %[top], 2f \n\t"552"ulw %[temp0], 0(%[top]) \n\t"553"ulw %[temp1], 4(%[top]) \n\t"554"raddu.w.qb %[temp0], %[temp0] \n\t"555"raddu.w.qb %[temp1], %[temp1] \n\t"556"addu %[DC], %[temp0], %[temp1] \n\t"557"move %[DC1], %[DC] \n\t"558"beqz %[left], 1f \n\t"559"ulw %[temp2], 0(%[left]) \n\t"560"ulw %[temp3], 4(%[left]) \n\t"561"raddu.w.qb %[temp2], %[temp2] \n\t"562"raddu.w.qb %[temp3], %[temp3] \n\t"563"addu %[DC1], %[temp2], %[temp3] \n\t"564"1: \n\t"565"addu %[DC], %[DC], %[DC1] \n\t"566"j 3f \n\t"567"2: \n\t"568"beqz %[left], 4f \n\t"569"ulw %[temp2], 0(%[left]) \n\t"570"ulw %[temp3], 4(%[left]) \n\t"571"raddu.w.qb %[temp2], %[temp2] \n\t"572"raddu.w.qb %[temp3], %[temp3] \n\t"573"addu %[DC], %[temp2], %[temp3] \n\t"574"addu %[DC], %[DC], %[DC] \n\t"575"3: \n\t"576"shra_r.w %[DC], %[DC], 4 \n\t"577"j 5f \n\t"578"4: \n\t"579"li %[DC], 0x80 \n\t"580"5: \n\t"581: [temp0]"=&r"(temp0), [temp1]"=&r"(temp1), [DC]"=&r"(DC),582[temp2]"=&r"(temp2), [temp3]"=&r"(temp3), [DC1]"=&r"(DC1)583: [left]"r"(left), [top]"r"(top)584: "memory"585);586587FILL_8_OR_16(dst, DC, 8);588}589590static void DC4(uint8_t* dst, const uint8_t* top) {591int temp0, temp1;592__asm__ volatile(593"ulw %[temp0], 0(%[top]) \n\t"594"ulw %[temp1], -5(%[top]) \n\t"595"raddu.w.qb %[temp0], %[temp0] \n\t"596"raddu.w.qb %[temp1], %[temp1] \n\t"597"addu %[temp0], %[temp0], %[temp1] \n\t"598"addiu %[temp0], %[temp0], 4 \n\t"599"srl %[temp0], %[temp0], 3 \n\t"600"replv.qb %[temp0], %[temp0] \n\t"601"usw %[temp0], 0*" XSTR(BPS) "(%[dst]) \n\t"602"usw %[temp0], 1*" XSTR(BPS) "(%[dst]) \n\t"603"usw %[temp0], 2*" XSTR(BPS) "(%[dst]) \n\t"604"usw %[temp0], 3*" XSTR(BPS) "(%[dst]) \n\t"605: [temp0]"=&r"(temp0), [temp1]"=&r"(temp1)606: [top]"r"(top), [dst]"r"(dst)607: "memory"608);609}610611static void TM4(uint8_t* dst, const uint8_t* top) {612int a10, a32, temp0, temp1, temp2, temp3, temp4, temp5;613const int c35 = 0xff00ff;614__asm__ volatile (615"lbu %[temp1], 0(%[top]) \n\t"616"lbu %[a10], 1(%[top]) \n\t"617"lbu %[temp2], 2(%[top]) \n\t"618"lbu %[a32], 3(%[top]) \n\t"619"ulw %[temp0], -5(%[top]) \n\t"620"lbu %[temp4], -1(%[top]) \n\t"621"append %[a10], %[temp1], 16 \n\t"622"append %[a32], %[temp2], 16 \n\t"623"replv.ph %[temp4], %[temp4] \n\t"624"shrl.ph %[temp1], %[temp0], 8 \n\t"625"and %[temp0], %[temp0], %[c35] \n\t"626"subu.ph %[temp1], %[temp1], %[temp4] \n\t"627"subu.ph %[temp0], %[temp0], %[temp4] \n\t"628"srl %[temp2], %[temp1], 16 \n\t"629"srl %[temp3], %[temp0], 16 \n\t"630"replv.ph %[temp2], %[temp2] \n\t"631"replv.ph %[temp3], %[temp3] \n\t"632"replv.ph %[temp4], %[temp1] \n\t"633"replv.ph %[temp5], %[temp0] \n\t"634"addu.ph %[temp0], %[temp3], %[a10] \n\t"635"addu.ph %[temp1], %[temp3], %[a32] \n\t"636"addu.ph %[temp3], %[temp2], %[a10] \n\t"637"addu.ph %[temp2], %[temp2], %[a32] \n\t"638"shll_s.ph %[temp0], %[temp0], 7 \n\t"639"shll_s.ph %[temp1], %[temp1], 7 \n\t"640"shll_s.ph %[temp3], %[temp3], 7 \n\t"641"shll_s.ph %[temp2], %[temp2], 7 \n\t"642"precrqu_s.qb.ph %[temp0], %[temp1], %[temp0] \n\t"643"precrqu_s.qb.ph %[temp1], %[temp2], %[temp3] \n\t"644"addu.ph %[temp2], %[temp5], %[a10] \n\t"645"addu.ph %[temp3], %[temp5], %[a32] \n\t"646"addu.ph %[temp5], %[temp4], %[a10] \n\t"647"addu.ph %[temp4], %[temp4], %[a32] \n\t"648"shll_s.ph %[temp2], %[temp2], 7 \n\t"649"shll_s.ph %[temp3], %[temp3], 7 \n\t"650"shll_s.ph %[temp4], %[temp4], 7 \n\t"651"shll_s.ph %[temp5], %[temp5], 7 \n\t"652"precrqu_s.qb.ph %[temp2], %[temp3], %[temp2] \n\t"653"precrqu_s.qb.ph %[temp3], %[temp4], %[temp5] \n\t"654"usw %[temp1], 0*" XSTR(BPS) "(%[dst]) \n\t"655"usw %[temp0], 1*" XSTR(BPS) "(%[dst]) \n\t"656"usw %[temp3], 2*" XSTR(BPS) "(%[dst]) \n\t"657"usw %[temp2], 3*" XSTR(BPS) "(%[dst]) \n\t"658: [temp0]"=&r"(temp0), [temp1]"=&r"(temp1), [temp2]"=&r"(temp2),659[temp3]"=&r"(temp3), [temp4]"=&r"(temp4), [temp5]"=&r"(temp5),660[a10]"=&r"(a10), [a32]"=&r"(a32)661: [c35]"r"(c35), [top]"r"(top), [dst]"r"(dst)662: "memory"663);664}665666static void VE4(uint8_t* dst, const uint8_t* top) {667int temp0, temp1, temp2, temp3, temp4, temp5, temp6;668__asm__ volatile(669"ulw %[temp0], -1(%[top]) \n\t"670"ulh %[temp1], 3(%[top]) \n\t"671"preceu.ph.qbr %[temp2], %[temp0] \n\t"672"preceu.ph.qbl %[temp3], %[temp0] \n\t"673"preceu.ph.qbr %[temp4], %[temp1] \n\t"674"packrl.ph %[temp5], %[temp3], %[temp2] \n\t"675"packrl.ph %[temp6], %[temp4], %[temp3] \n\t"676"shll.ph %[temp5], %[temp5], 1 \n\t"677"shll.ph %[temp6], %[temp6], 1 \n\t"678"addq.ph %[temp2], %[temp5], %[temp2] \n\t"679"addq.ph %[temp6], %[temp6], %[temp4] \n\t"680"addq.ph %[temp2], %[temp2], %[temp3] \n\t"681"addq.ph %[temp6], %[temp6], %[temp3] \n\t"682"shra_r.ph %[temp2], %[temp2], 2 \n\t"683"shra_r.ph %[temp6], %[temp6], 2 \n\t"684"precr.qb.ph %[temp4], %[temp6], %[temp2] \n\t"685"usw %[temp4], 0*" XSTR(BPS) "(%[dst]) \n\t"686"usw %[temp4], 1*" XSTR(BPS) "(%[dst]) \n\t"687"usw %[temp4], 2*" XSTR(BPS) "(%[dst]) \n\t"688"usw %[temp4], 3*" XSTR(BPS) "(%[dst]) \n\t"689: [temp0]"=&r"(temp0), [temp1]"=&r"(temp1), [temp2]"=&r"(temp2),690[temp3]"=&r"(temp3), [temp4]"=&r"(temp4), [temp5]"=&r"(temp5),691[temp6]"=&r"(temp6)692: [top]"r"(top), [dst]"r"(dst)693: "memory"694);695}696697static void HE4(uint8_t* dst, const uint8_t* top) {698int temp0, temp1, temp2, temp3, temp4, temp5, temp6;699__asm__ volatile(700"ulw %[temp0], -4(%[top]) \n\t"701"lbu %[temp1], -5(%[top]) \n\t"702"preceu.ph.qbr %[temp2], %[temp0] \n\t"703"preceu.ph.qbl %[temp3], %[temp0] \n\t"704"replv.ph %[temp4], %[temp1] \n\t"705"packrl.ph %[temp5], %[temp3], %[temp2] \n\t"706"packrl.ph %[temp6], %[temp2], %[temp4] \n\t"707"shll.ph %[temp5], %[temp5], 1 \n\t"708"shll.ph %[temp6], %[temp6], 1 \n\t"709"addq.ph %[temp3], %[temp3], %[temp5] \n\t"710"addq.ph %[temp3], %[temp3], %[temp2] \n\t"711"addq.ph %[temp2], %[temp2], %[temp6] \n\t"712"addq.ph %[temp2], %[temp2], %[temp4] \n\t"713"shra_r.ph %[temp3], %[temp3], 2 \n\t"714"shra_r.ph %[temp2], %[temp2], 2 \n\t"715"replv.qb %[temp0], %[temp3] \n\t"716"replv.qb %[temp1], %[temp2] \n\t"717"srl %[temp3], %[temp3], 16 \n\t"718"srl %[temp2], %[temp2], 16 \n\t"719"replv.qb %[temp3], %[temp3] \n\t"720"replv.qb %[temp2], %[temp2] \n\t"721"usw %[temp3], 0*" XSTR(BPS) "(%[dst]) \n\t"722"usw %[temp0], 1*" XSTR(BPS) "(%[dst]) \n\t"723"usw %[temp2], 2*" XSTR(BPS) "(%[dst]) \n\t"724"usw %[temp1], 3*" XSTR(BPS) "(%[dst]) \n\t"725: [temp0]"=&r"(temp0), [temp1]"=&r"(temp1), [temp2]"=&r"(temp2),726[temp3]"=&r"(temp3), [temp4]"=&r"(temp4), [temp5]"=&r"(temp5),727[temp6]"=&r"(temp6)728: [top]"r"(top), [dst]"r"(dst)729: "memory"730);731}732733static void RD4(uint8_t* dst, const uint8_t* top) {734int temp0, temp1, temp2, temp3, temp4, temp5;735int temp6, temp7, temp8, temp9, temp10, temp11;736__asm__ volatile(737"ulw %[temp0], -5(%[top]) \n\t"738"ulw %[temp1], -1(%[top]) \n\t"739"preceu.ph.qbl %[temp2], %[temp0] \n\t"740"preceu.ph.qbr %[temp3], %[temp0] \n\t"741"preceu.ph.qbr %[temp4], %[temp1] \n\t"742"preceu.ph.qbl %[temp5], %[temp1] \n\t"743"packrl.ph %[temp6], %[temp2], %[temp3] \n\t"744"packrl.ph %[temp7], %[temp4], %[temp2] \n\t"745"packrl.ph %[temp8], %[temp5], %[temp4] \n\t"746"shll.ph %[temp6], %[temp6], 1 \n\t"747"addq.ph %[temp9], %[temp2], %[temp6] \n\t"748"shll.ph %[temp7], %[temp7], 1 \n\t"749"addq.ph %[temp9], %[temp9], %[temp3] \n\t"750"shll.ph %[temp8], %[temp8], 1 \n\t"751"shra_r.ph %[temp9], %[temp9], 2 \n\t"752"addq.ph %[temp10], %[temp4], %[temp7] \n\t"753"addq.ph %[temp11], %[temp5], %[temp8] \n\t"754"addq.ph %[temp10], %[temp10], %[temp2] \n\t"755"addq.ph %[temp11], %[temp11], %[temp4] \n\t"756"shra_r.ph %[temp10], %[temp10], 2 \n\t"757"shra_r.ph %[temp11], %[temp11], 2 \n\t"758"lbu %[temp0], 3(%[top]) \n\t"759"lbu %[temp1], 2(%[top]) \n\t"760"lbu %[temp2], 1(%[top]) \n\t"761"sll %[temp1], %[temp1], 1 \n\t"762"addu %[temp0], %[temp0], %[temp1] \n\t"763"addu %[temp0], %[temp0], %[temp2] \n\t"764"precr.qb.ph %[temp9], %[temp10], %[temp9] \n\t"765"shra_r.w %[temp0], %[temp0], 2 \n\t"766"precr.qb.ph %[temp10], %[temp11], %[temp10] \n\t"767"usw %[temp9], 3*" XSTR(BPS) "(%[dst]) \n\t"768"usw %[temp10], 1*" XSTR(BPS) "(%[dst]) \n\t"769"prepend %[temp9], %[temp11], 8 \n\t"770"prepend %[temp10], %[temp0], 8 \n\t"771"usw %[temp9], 2*" XSTR(BPS) "(%[dst]) \n\t"772"usw %[temp10], 0*" XSTR(BPS) "(%[dst]) \n\t"773: [temp0]"=&r"(temp0), [temp1]"=&r"(temp1), [temp2]"=&r"(temp2),774[temp3]"=&r"(temp3), [temp4]"=&r"(temp4), [temp5]"=&r"(temp5),775[temp6]"=&r"(temp6), [temp7]"=&r"(temp7), [temp8]"=&r"(temp8),776[temp9]"=&r"(temp9), [temp10]"=&r"(temp10), [temp11]"=&r"(temp11)777: [top]"r"(top), [dst]"r"(dst)778: "memory"779);780}781782static void VR4(uint8_t* dst, const uint8_t* top) {783int temp0, temp1, temp2, temp3, temp4;784int temp5, temp6, temp7, temp8, temp9;785__asm__ volatile (786"ulw %[temp0], -4(%[top]) \n\t"787"ulw %[temp1], 0(%[top]) \n\t"788"preceu.ph.qbl %[temp2], %[temp0] \n\t"789"preceu.ph.qbr %[temp0], %[temp0] \n\t"790"preceu.ph.qbla %[temp3], %[temp1] \n\t"791"preceu.ph.qbra %[temp1], %[temp1] \n\t"792"packrl.ph %[temp7], %[temp3], %[temp2] \n\t"793"addqh_r.ph %[temp4], %[temp1], %[temp3] \n\t"794"move %[temp6], %[temp1] \n\t"795"append %[temp1], %[temp2], 16 \n\t"796"shll.ph %[temp9], %[temp6], 1 \n\t"797"addqh_r.ph %[temp5], %[temp7], %[temp6] \n\t"798"shll.ph %[temp8], %[temp7], 1 \n\t"799"addu.ph %[temp3], %[temp7], %[temp3] \n\t"800"addu.ph %[temp1], %[temp1], %[temp6] \n\t"801"packrl.ph %[temp7], %[temp2], %[temp0] \n\t"802"addu.ph %[temp6], %[temp0], %[temp2] \n\t"803"addu.ph %[temp3], %[temp3], %[temp9] \n\t"804"addu.ph %[temp1], %[temp1], %[temp8] \n\t"805"shll.ph %[temp7], %[temp7], 1 \n\t"806"shra_r.ph %[temp3], %[temp3], 2 \n\t"807"shra_r.ph %[temp1], %[temp1], 2 \n\t"808"addu.ph %[temp6], %[temp6], %[temp7] \n\t"809"shra_r.ph %[temp6], %[temp6], 2 \n\t"810"precrq.ph.w %[temp8], %[temp4], %[temp5] \n\t"811"append %[temp4], %[temp5], 16 \n\t"812"precrq.ph.w %[temp2], %[temp3], %[temp1] \n\t"813"append %[temp3], %[temp1], 16 \n\t"814"precr.qb.ph %[temp8], %[temp8], %[temp4] \n\t"815"precr.qb.ph %[temp3], %[temp2], %[temp3] \n\t"816"usw %[temp8], 0*" XSTR(BPS) "(%[dst]) \n\t"817"usw %[temp3], 1*" XSTR(BPS) "(%[dst]) \n\t"818"append %[temp3], %[temp6], 8 \n\t"819"srl %[temp6], %[temp6], 16 \n\t"820"append %[temp8], %[temp6], 8 \n\t"821"usw %[temp3], 3*" XSTR(BPS) "(%[dst]) \n\t"822"usw %[temp8], 2*" XSTR(BPS) "(%[dst]) \n\t"823: [temp0]"=&r"(temp0), [temp1]"=&r"(temp1), [temp2]"=&r"(temp2),824[temp3]"=&r"(temp3), [temp4]"=&r"(temp4), [temp5]"=&r"(temp5),825[temp6]"=&r"(temp6), [temp7]"=&r"(temp7), [temp8]"=&r"(temp8),826[temp9]"=&r"(temp9)827: [top]"r"(top), [dst]"r"(dst)828: "memory"829);830}831832static void LD4(uint8_t* dst, const uint8_t* top) {833int temp0, temp1, temp2, temp3, temp4, temp5;834int temp6, temp7, temp8, temp9, temp10, temp11;835__asm__ volatile(836"ulw %[temp0], 0(%[top]) \n\t"837"ulw %[temp1], 4(%[top]) \n\t"838"preceu.ph.qbl %[temp2], %[temp0] \n\t"839"preceu.ph.qbr %[temp3], %[temp0] \n\t"840"preceu.ph.qbr %[temp4], %[temp1] \n\t"841"preceu.ph.qbl %[temp5], %[temp1] \n\t"842"packrl.ph %[temp6], %[temp2], %[temp3] \n\t"843"packrl.ph %[temp7], %[temp4], %[temp2] \n\t"844"packrl.ph %[temp8], %[temp5], %[temp4] \n\t"845"shll.ph %[temp6], %[temp6], 1 \n\t"846"addq.ph %[temp9], %[temp2], %[temp6] \n\t"847"shll.ph %[temp7], %[temp7], 1 \n\t"848"addq.ph %[temp9], %[temp9], %[temp3] \n\t"849"shll.ph %[temp8], %[temp8], 1 \n\t"850"shra_r.ph %[temp9], %[temp9], 2 \n\t"851"addq.ph %[temp10], %[temp4], %[temp7] \n\t"852"addq.ph %[temp11], %[temp5], %[temp8] \n\t"853"addq.ph %[temp10], %[temp10], %[temp2] \n\t"854"addq.ph %[temp11], %[temp11], %[temp4] \n\t"855"shra_r.ph %[temp10], %[temp10], 2 \n\t"856"shra_r.ph %[temp11], %[temp11], 2 \n\t"857"srl %[temp1], %[temp1], 24 \n\t"858"sll %[temp1], %[temp1], 1 \n\t"859"raddu.w.qb %[temp5], %[temp5] \n\t"860"precr.qb.ph %[temp9], %[temp10], %[temp9] \n\t"861"precr.qb.ph %[temp10], %[temp11], %[temp10] \n\t"862"addu %[temp1], %[temp1], %[temp5] \n\t"863"shra_r.w %[temp1], %[temp1], 2 \n\t"864"usw %[temp9], 0*" XSTR(BPS) "(%[dst]) \n\t"865"usw %[temp10], 2*" XSTR(BPS) "(%[dst]) \n\t"866"prepend %[temp9], %[temp11], 8 \n\t"867"prepend %[temp10], %[temp1], 8 \n\t"868"usw %[temp9], 1*" XSTR(BPS) "(%[dst]) \n\t"869"usw %[temp10], 3*" XSTR(BPS) "(%[dst]) \n\t"870: [temp0]"=&r"(temp0), [temp1]"=&r"(temp1), [temp2]"=&r"(temp2),871[temp3]"=&r"(temp3), [temp4]"=&r"(temp4), [temp5]"=&r"(temp5),872[temp6]"=&r"(temp6), [temp7]"=&r"(temp7), [temp8]"=&r"(temp8),873[temp9]"=&r"(temp9), [temp10]"=&r"(temp10), [temp11]"=&r"(temp11)874: [top]"r"(top), [dst]"r"(dst)875: "memory"876);877}878879static void VL4(uint8_t* dst, const uint8_t* top) {880int temp0, temp1, temp2, temp3, temp4;881int temp5, temp6, temp7, temp8, temp9;882__asm__ volatile (883"ulw %[temp0], 0(%[top]) \n\t"884"ulw %[temp1], 4(%[top]) \n\t"885"preceu.ph.qbla %[temp2], %[temp0] \n\t"886"preceu.ph.qbra %[temp0], %[temp0] \n\t"887"preceu.ph.qbl %[temp3], %[temp1] \n\t"888"preceu.ph.qbr %[temp1], %[temp1] \n\t"889"addqh_r.ph %[temp4], %[temp0], %[temp2] \n\t"890"packrl.ph %[temp7], %[temp1], %[temp0] \n\t"891"precrq.ph.w %[temp6], %[temp1], %[temp2] \n\t"892"shll.ph %[temp9], %[temp2], 1 \n\t"893"addqh_r.ph %[temp5], %[temp7], %[temp2] \n\t"894"shll.ph %[temp8], %[temp7], 1 \n\t"895"addu.ph %[temp2], %[temp2], %[temp6] \n\t"896"addu.ph %[temp0], %[temp0], %[temp7] \n\t"897"packrl.ph %[temp7], %[temp3], %[temp1] \n\t"898"addu.ph %[temp6], %[temp1], %[temp3] \n\t"899"addu.ph %[temp2], %[temp2], %[temp8] \n\t"900"addu.ph %[temp0], %[temp0], %[temp9] \n\t"901"shll.ph %[temp7], %[temp7], 1 \n\t"902"shra_r.ph %[temp2], %[temp2], 2 \n\t"903"shra_r.ph %[temp0], %[temp0], 2 \n\t"904"addu.ph %[temp6], %[temp6], %[temp7] \n\t"905"shra_r.ph %[temp6], %[temp6], 2 \n\t"906"precrq.ph.w %[temp8], %[temp5], %[temp4] \n\t"907"append %[temp5], %[temp4], 16 \n\t"908"precrq.ph.w %[temp3], %[temp2], %[temp0] \n\t"909"append %[temp2], %[temp0], 16 \n\t"910"precr.qb.ph %[temp8], %[temp8], %[temp5] \n\t"911"precr.qb.ph %[temp3], %[temp3], %[temp2] \n\t"912"usw %[temp8], 0*" XSTR(BPS) "(%[dst]) \n\t"913"prepend %[temp8], %[temp6], 8 \n\t"914"usw %[temp3], 1*" XSTR(BPS) "(%[dst]) \n\t"915"srl %[temp6], %[temp6], 16 \n\t"916"prepend %[temp3], %[temp6], 8 \n\t"917"usw %[temp8], 2*" XSTR(BPS) "(%[dst]) \n\t"918"usw %[temp3], 3*" XSTR(BPS) "(%[dst]) \n\t"919: [temp0]"=&r"(temp0), [temp1]"=&r"(temp1), [temp2]"=&r"(temp2),920[temp3]"=&r"(temp3), [temp4]"=&r"(temp4), [temp5]"=&r"(temp5),921[temp6]"=&r"(temp6), [temp7]"=&r"(temp7), [temp8]"=&r"(temp8),922[temp9]"=&r"(temp9)923: [top]"r"(top), [dst]"r"(dst)924: "memory"925);926}927928static void HD4(uint8_t* dst, const uint8_t* top) {929int temp0, temp1, temp2, temp3, temp4;930int temp5, temp6, temp7, temp8, temp9;931__asm__ volatile (932"ulw %[temp0], -5(%[top]) \n\t"933"ulw %[temp1], -1(%[top]) \n\t"934"preceu.ph.qbla %[temp2], %[temp0] \n\t"935"preceu.ph.qbra %[temp0], %[temp0] \n\t"936"preceu.ph.qbl %[temp3], %[temp1] \n\t"937"preceu.ph.qbr %[temp1], %[temp1] \n\t"938"addqh_r.ph %[temp4], %[temp0], %[temp2] \n\t"939"packrl.ph %[temp7], %[temp1], %[temp0] \n\t"940"precrq.ph.w %[temp6], %[temp1], %[temp2] \n\t"941"shll.ph %[temp9], %[temp2], 1 \n\t"942"addqh_r.ph %[temp5], %[temp7], %[temp2] \n\t"943"shll.ph %[temp8], %[temp7], 1 \n\t"944"addu.ph %[temp2], %[temp2], %[temp6] \n\t"945"addu.ph %[temp0], %[temp0], %[temp7] \n\t"946"packrl.ph %[temp7], %[temp3], %[temp1] \n\t"947"addu.ph %[temp6], %[temp1], %[temp3] \n\t"948"addu.ph %[temp2], %[temp2], %[temp8] \n\t"949"addu.ph %[temp0], %[temp0], %[temp9] \n\t"950"shll.ph %[temp7], %[temp7], 1 \n\t"951"shra_r.ph %[temp2], %[temp2], 2 \n\t"952"shra_r.ph %[temp0], %[temp0], 2 \n\t"953"addu.ph %[temp6], %[temp6], %[temp7] \n\t"954"shra_r.ph %[temp6], %[temp6], 2 \n\t"955"precrq.ph.w %[temp1], %[temp2], %[temp5] \n\t"956"precrq.ph.w %[temp3], %[temp0], %[temp4] \n\t"957"precr.qb.ph %[temp7], %[temp6], %[temp1] \n\t"958"precr.qb.ph %[temp6], %[temp1], %[temp3] \n\t"959"usw %[temp7], 0*" XSTR(BPS) "(%[dst]) \n\t"960"usw %[temp6], 1*" XSTR(BPS) "(%[dst]) \n\t"961"append %[temp2], %[temp5], 16 \n\t"962"append %[temp0], %[temp4], 16 \n\t"963"precr.qb.ph %[temp5], %[temp3], %[temp2] \n\t"964"precr.qb.ph %[temp4], %[temp2], %[temp0] \n\t"965"usw %[temp5], 2*" XSTR(BPS) "(%[dst]) \n\t"966"usw %[temp4], 3*" XSTR(BPS) "(%[dst]) \n\t"967: [temp0]"=&r"(temp0), [temp1]"=&r"(temp1), [temp2]"=&r"(temp2),968[temp3]"=&r"(temp3), [temp4]"=&r"(temp4), [temp5]"=&r"(temp5),969[temp6]"=&r"(temp6), [temp7]"=&r"(temp7), [temp8]"=&r"(temp8),970[temp9]"=&r"(temp9)971: [top]"r"(top), [dst]"r"(dst)972: "memory"973);974}975976static void HU4(uint8_t* dst, const uint8_t* top) {977int temp0, temp1, temp2, temp3, temp4, temp5, temp6, temp7;978__asm__ volatile (979"ulw %[temp0], -5(%[top]) \n\t"980"preceu.ph.qbl %[temp1], %[temp0] \n\t"981"preceu.ph.qbr %[temp2], %[temp0] \n\t"982"packrl.ph %[temp3], %[temp1], %[temp2] \n\t"983"replv.qb %[temp7], %[temp2] \n\t"984"addqh_r.ph %[temp4], %[temp1], %[temp3] \n\t"985"addqh_r.ph %[temp5], %[temp3], %[temp2] \n\t"986"shll.ph %[temp6], %[temp3], 1 \n\t"987"addu.ph %[temp3], %[temp2], %[temp3] \n\t"988"addu.ph %[temp6], %[temp1], %[temp6] \n\t"989"shll.ph %[temp0], %[temp2], 1 \n\t"990"addu.ph %[temp6], %[temp6], %[temp2] \n\t"991"addu.ph %[temp0], %[temp3], %[temp0] \n\t"992"shra_r.ph %[temp6], %[temp6], 2 \n\t"993"shra_r.ph %[temp0], %[temp0], 2 \n\t"994"packrl.ph %[temp3], %[temp6], %[temp5] \n\t"995"precrq.ph.w %[temp2], %[temp6], %[temp4] \n\t"996"append %[temp0], %[temp5], 16 \n\t"997"precr.qb.ph %[temp3], %[temp3], %[temp2] \n\t"998"usw %[temp3], 0*" XSTR(BPS) "(%[dst]) \n\t"999"precr.qb.ph %[temp1], %[temp7], %[temp0] \n\t"1000"usw %[temp7], 3*" XSTR(BPS) "(%[dst]) \n\t"1001"packrl.ph %[temp2], %[temp1], %[temp3] \n\t"1002"usw %[temp1], 2*" XSTR(BPS) "(%[dst]) \n\t"1003"usw %[temp2], 1*" XSTR(BPS) "(%[dst]) \n\t"1004: [temp0]"=&r"(temp0), [temp1]"=&r"(temp1), [temp2]"=&r"(temp2),1005[temp3]"=&r"(temp3), [temp4]"=&r"(temp4), [temp5]"=&r"(temp5),1006[temp6]"=&r"(temp6), [temp7]"=&r"(temp7)1007: [top]"r"(top), [dst]"r"(dst)1008: "memory"1009);1010}10111012//------------------------------------------------------------------------------1013// Chroma 8x8 prediction (paragraph 12.2)10141015static void IntraChromaPreds_MIPSdspR2(uint8_t* dst, const uint8_t* left,1016const uint8_t* top) {1017// U block1018DCMode8(C8DC8 + dst, left, top);1019VerticalPred8(C8VE8 + dst, top);1020HorizontalPred8(C8HE8 + dst, left);1021TrueMotion8(C8TM8 + dst, left, top);1022// V block1023dst += 8;1024if (top) top += 8;1025if (left) left += 16;1026DCMode8(C8DC8 + dst, left, top);1027VerticalPred8(C8VE8 + dst, top);1028HorizontalPred8(C8HE8 + dst, left);1029TrueMotion8(C8TM8 + dst, left, top);1030}10311032//------------------------------------------------------------------------------1033// luma 16x16 prediction (paragraph 12.3)10341035static void Intra16Preds_MIPSdspR2(uint8_t* dst,1036const uint8_t* left, const uint8_t* top) {1037DCMode16(I16DC16 + dst, left, top);1038VerticalPred16(I16VE16 + dst, top);1039HorizontalPred16(I16HE16 + dst, left);1040TrueMotion16(I16TM16 + dst, left, top);1041}10421043// Left samples are top[-5 .. -2], top_left is top[-1], top are1044// located at top[0..3], and top right is top[4..7]1045static void Intra4Preds_MIPSdspR2(uint8_t* dst, const uint8_t* top) {1046DC4(I4DC4 + dst, top);1047TM4(I4TM4 + dst, top);1048VE4(I4VE4 + dst, top);1049HE4(I4HE4 + dst, top);1050RD4(I4RD4 + dst, top);1051VR4(I4VR4 + dst, top);1052LD4(I4LD4 + dst, top);1053VL4(I4VL4 + dst, top);1054HD4(I4HD4 + dst, top);1055HU4(I4HU4 + dst, top);1056}10571058//------------------------------------------------------------------------------1059// Metric10601061#if !defined(WORK_AROUND_GCC)10621063#define GET_SSE_INNER(A) \1064"lw %[temp0], " #A "(%[a]) \n\t" \1065"lw %[temp1], " #A "(%[b]) \n\t" \1066"preceu.ph.qbr %[temp2], %[temp0] \n\t" \1067"preceu.ph.qbl %[temp0], %[temp0] \n\t" \1068"preceu.ph.qbr %[temp3], %[temp1] \n\t" \1069"preceu.ph.qbl %[temp1], %[temp1] \n\t" \1070"subq.ph %[temp2], %[temp2], %[temp3] \n\t" \1071"subq.ph %[temp0], %[temp0], %[temp1] \n\t" \1072"dpa.w.ph $ac0, %[temp2], %[temp2] \n\t" \1073"dpa.w.ph $ac0, %[temp0], %[temp0] \n\t"10741075#define GET_SSE(A, B, C, D) \1076GET_SSE_INNER(A) \1077GET_SSE_INNER(B) \1078GET_SSE_INNER(C) \1079GET_SSE_INNER(D)10801081static int SSE16x16_MIPSdspR2(const uint8_t* a, const uint8_t* b) {1082int count;1083int temp0, temp1, temp2, temp3;1084__asm__ volatile (1085"mult $zero, $zero \n\t"1086GET_SSE( 0 * BPS, 4 + 0 * BPS, 8 + 0 * BPS, 12 + 0 * BPS)1087GET_SSE( 1 * BPS, 4 + 1 * BPS, 8 + 1 * BPS, 12 + 1 * BPS)1088GET_SSE( 2 * BPS, 4 + 2 * BPS, 8 + 2 * BPS, 12 + 2 * BPS)1089GET_SSE( 3 * BPS, 4 + 3 * BPS, 8 + 3 * BPS, 12 + 3 * BPS)1090GET_SSE( 4 * BPS, 4 + 4 * BPS, 8 + 4 * BPS, 12 + 4 * BPS)1091GET_SSE( 5 * BPS, 4 + 5 * BPS, 8 + 5 * BPS, 12 + 5 * BPS)1092GET_SSE( 6 * BPS, 4 + 6 * BPS, 8 + 6 * BPS, 12 + 6 * BPS)1093GET_SSE( 7 * BPS, 4 + 7 * BPS, 8 + 7 * BPS, 12 + 7 * BPS)1094GET_SSE( 8 * BPS, 4 + 8 * BPS, 8 + 8 * BPS, 12 + 8 * BPS)1095GET_SSE( 9 * BPS, 4 + 9 * BPS, 8 + 9 * BPS, 12 + 9 * BPS)1096GET_SSE(10 * BPS, 4 + 10 * BPS, 8 + 10 * BPS, 12 + 10 * BPS)1097GET_SSE(11 * BPS, 4 + 11 * BPS, 8 + 11 * BPS, 12 + 11 * BPS)1098GET_SSE(12 * BPS, 4 + 12 * BPS, 8 + 12 * BPS, 12 + 12 * BPS)1099GET_SSE(13 * BPS, 4 + 13 * BPS, 8 + 13 * BPS, 12 + 13 * BPS)1100GET_SSE(14 * BPS, 4 + 14 * BPS, 8 + 14 * BPS, 12 + 14 * BPS)1101GET_SSE(15 * BPS, 4 + 15 * BPS, 8 + 15 * BPS, 12 + 15 * BPS)1102"mflo %[count] \n\t"1103: [temp0]"=&r"(temp0), [temp1]"=&r"(temp1), [temp2]"=&r"(temp2),1104[temp3]"=&r"(temp3), [count]"=&r"(count)1105: [a]"r"(a), [b]"r"(b)1106: "memory", "hi", "lo"1107);1108return count;1109}11101111static int SSE16x8_MIPSdspR2(const uint8_t* a, const uint8_t* b) {1112int count;1113int temp0, temp1, temp2, temp3;1114__asm__ volatile (1115"mult $zero, $zero \n\t"1116GET_SSE( 0 * BPS, 4 + 0 * BPS, 8 + 0 * BPS, 12 + 0 * BPS)1117GET_SSE( 1 * BPS, 4 + 1 * BPS, 8 + 1 * BPS, 12 + 1 * BPS)1118GET_SSE( 2 * BPS, 4 + 2 * BPS, 8 + 2 * BPS, 12 + 2 * BPS)1119GET_SSE( 3 * BPS, 4 + 3 * BPS, 8 + 3 * BPS, 12 + 3 * BPS)1120GET_SSE( 4 * BPS, 4 + 4 * BPS, 8 + 4 * BPS, 12 + 4 * BPS)1121GET_SSE( 5 * BPS, 4 + 5 * BPS, 8 + 5 * BPS, 12 + 5 * BPS)1122GET_SSE( 6 * BPS, 4 + 6 * BPS, 8 + 6 * BPS, 12 + 6 * BPS)1123GET_SSE( 7 * BPS, 4 + 7 * BPS, 8 + 7 * BPS, 12 + 7 * BPS)1124"mflo %[count] \n\t"1125: [temp0]"=&r"(temp0), [temp1]"=&r"(temp1), [temp2]"=&r"(temp2),1126[temp3]"=&r"(temp3), [count]"=&r"(count)1127: [a]"r"(a), [b]"r"(b)1128: "memory", "hi", "lo"1129);1130return count;1131}11321133static int SSE8x8_MIPSdspR2(const uint8_t* a, const uint8_t* b) {1134int count;1135int temp0, temp1, temp2, temp3;1136__asm__ volatile (1137"mult $zero, $zero \n\t"1138GET_SSE(0 * BPS, 4 + 0 * BPS, 1 * BPS, 4 + 1 * BPS)1139GET_SSE(2 * BPS, 4 + 2 * BPS, 3 * BPS, 4 + 3 * BPS)1140GET_SSE(4 * BPS, 4 + 4 * BPS, 5 * BPS, 4 + 5 * BPS)1141GET_SSE(6 * BPS, 4 + 6 * BPS, 7 * BPS, 4 + 7 * BPS)1142"mflo %[count] \n\t"1143: [temp0]"=&r"(temp0), [temp1]"=&r"(temp1), [temp2]"=&r"(temp2),1144[temp3]"=&r"(temp3), [count]"=&r"(count)1145: [a]"r"(a), [b]"r"(b)1146: "memory", "hi", "lo"1147);1148return count;1149}11501151static int SSE4x4_MIPSdspR2(const uint8_t* a, const uint8_t* b) {1152int count;1153int temp0, temp1, temp2, temp3;1154__asm__ volatile (1155"mult $zero, $zero \n\t"1156GET_SSE(0 * BPS, 1 * BPS, 2 * BPS, 3 * BPS)1157"mflo %[count] \n\t"1158: [temp0]"=&r"(temp0), [temp1]"=&r"(temp1), [temp2]"=&r"(temp2),1159[temp3]"=&r"(temp3), [count]"=&r"(count)1160: [a]"r"(a), [b]"r"(b)1161: "memory", "hi", "lo"1162);1163return count;1164}11651166#undef GET_SSE1167#undef GET_SSE_INNER11681169#endif // !WORK_AROUND_GCC11701171#undef FILL_8_OR_161172#undef FILL_PART1173#undef OUTPUT_EARLY_CLOBBER_REGS_171174#undef MUL_HALF1175#undef ABS_X81176#undef ADD_SUB_HALVES_X411771178//------------------------------------------------------------------------------1179// Quantization1180//11811182// macro for one pass through for loop in QuantizeBlock reading 2 values at time1183// QUANTDIV macro inlined1184// J - offset in bytes (kZigzag[n] * 2)1185// K - offset in bytes (kZigzag[n] * 4)1186// N - offset in bytes (n * 2)1187// N1 - offset in bytes ((n + 1) * 2)1188#define QUANTIZE_ONE(J, K, N, N1) \1189"ulw %[temp1], " #J "(%[ppin]) \n\t" \1190"ulw %[temp2], " #J "(%[ppsharpen]) \n\t" \1191"lhu %[temp3], " #K "(%[ppzthresh]) \n\t" \1192"lhu %[temp6], " #K "+4(%[ppzthresh]) \n\t" \1193"absq_s.ph %[temp4], %[temp1] \n\t" \1194"ins %[temp3], %[temp6], 16, 16 \n\t" \1195"addu.ph %[coeff], %[temp4], %[temp2] \n\t" \1196"shra.ph %[sign], %[temp1], 15 \n\t" \1197"li %[level], 0x10001 \n\t" \1198"cmp.lt.ph %[temp3], %[coeff] \n\t" \1199"lhu %[temp1], " #J "(%[ppiq]) \n\t" \1200"pick.ph %[temp5], %[level], $0 \n\t" \1201"lw %[temp2], " #K "(%[ppbias]) \n\t" \1202"beqz %[temp5], 0f \n\t" \1203"lhu %[temp3], " #J "(%[ppq]) \n\t" \1204"beq %[temp5], %[level], 1f \n\t" \1205"andi %[temp5], %[temp5], 0x1 \n\t" \1206"andi %[temp4], %[coeff], 0xffff \n\t" \1207"beqz %[temp5], 2f \n\t" \1208"mul %[level], %[temp4], %[temp1] \n\t" \1209"sh $0, " #J "+2(%[ppin]) \n\t" \1210"sh $0, " #N1 "(%[pout]) \n\t" \1211"addu %[level], %[level], %[temp2] \n\t" \1212"sra %[level], %[level], 17 \n\t" \1213"slt %[temp4], %[max_level], %[level] \n\t" \1214"movn %[level], %[max_level], %[temp4] \n\t" \1215"andi %[temp6], %[sign], 0xffff \n\t" \1216"xor %[level], %[level], %[temp6] \n\t" \1217"subu %[level], %[level], %[temp6] \n\t" \1218"mul %[temp5], %[level], %[temp3] \n\t" \1219"or %[ret], %[ret], %[level] \n\t" \1220"sh %[level], " #N "(%[pout]) \n\t" \1221"sh %[temp5], " #J "(%[ppin]) \n\t" \1222"j 3f \n\t" \1223"2: \n\t" \1224"lhu %[temp1], " #J "+2(%[ppiq]) \n\t" \1225"srl %[temp5], %[coeff], 16 \n\t" \1226"mul %[level], %[temp5], %[temp1] \n\t" \1227"lw %[temp2], " #K "+4(%[ppbias]) \n\t" \1228"lhu %[temp3], " #J "+2(%[ppq]) \n\t" \1229"addu %[level], %[level], %[temp2] \n\t" \1230"sra %[level], %[level], 17 \n\t" \1231"srl %[temp6], %[sign], 16 \n\t" \1232"slt %[temp4], %[max_level], %[level] \n\t" \1233"movn %[level], %[max_level], %[temp4] \n\t" \1234"xor %[level], %[level], %[temp6] \n\t" \1235"subu %[level], %[level], %[temp6] \n\t" \1236"mul %[temp5], %[level], %[temp3] \n\t" \1237"sh $0, " #J "(%[ppin]) \n\t" \1238"sh $0, " #N "(%[pout]) \n\t" \1239"or %[ret], %[ret], %[level] \n\t" \1240"sh %[temp5], " #J "+2(%[ppin]) \n\t" \1241"sh %[level], " #N1 "(%[pout]) \n\t" \1242"j 3f \n\t" \1243"1: \n\t" \1244"lhu %[temp1], " #J "(%[ppiq]) \n\t" \1245"lw %[temp2], " #K "(%[ppbias]) \n\t" \1246"ulw %[temp3], " #J "(%[ppq]) \n\t" \1247"andi %[temp5], %[coeff], 0xffff \n\t" \1248"srl %[temp0], %[coeff], 16 \n\t" \1249"lhu %[temp6], " #J "+2(%[ppiq]) \n\t" \1250"lw %[coeff], " #K "+4(%[ppbias]) \n\t" \1251"mul %[level], %[temp5], %[temp1] \n\t" \1252"mul %[temp4], %[temp0], %[temp6] \n\t" \1253"addu %[level], %[level], %[temp2] \n\t" \1254"addu %[temp4], %[temp4], %[coeff] \n\t" \1255"precrq.ph.w %[level], %[temp4], %[level] \n\t" \1256"shra.ph %[level], %[level], 1 \n\t" \1257"cmp.lt.ph %[max_level1],%[level] \n\t" \1258"pick.ph %[level], %[max_level], %[level] \n\t" \1259"xor %[level], %[level], %[sign] \n\t" \1260"subu.ph %[level], %[level], %[sign] \n\t" \1261"mul.ph %[temp3], %[level], %[temp3] \n\t" \1262"or %[ret], %[ret], %[level] \n\t" \1263"sh %[level], " #N "(%[pout]) \n\t" \1264"srl %[level], %[level], 16 \n\t" \1265"sh %[level], " #N1 "(%[pout]) \n\t" \1266"usw %[temp3], " #J "(%[ppin]) \n\t" \1267"j 3f \n\t" \1268"0: \n\t" \1269"sh $0, " #N "(%[pout]) \n\t" \1270"sh $0, " #N1 "(%[pout]) \n\t" \1271"usw $0, " #J "(%[ppin]) \n\t" \1272"3: \n\t"12731274static int QuantizeBlock_MIPSdspR2(int16_t in[16], int16_t out[16],1275const VP8Matrix* const mtx) {1276int temp0, temp1, temp2, temp3, temp4, temp5,temp6;1277int sign, coeff, level;1278int max_level = MAX_LEVEL;1279int max_level1 = max_level << 16 | max_level;1280int ret = 0;12811282int16_t* ppin = &in[0];1283int16_t* pout = &out[0];1284const uint16_t* ppsharpen = &mtx->sharpen_[0];1285const uint32_t* ppzthresh = &mtx->zthresh_[0];1286const uint16_t* ppq = &mtx->q_[0];1287const uint16_t* ppiq = &mtx->iq_[0];1288const uint32_t* ppbias = &mtx->bias_[0];12891290__asm__ volatile (1291QUANTIZE_ONE( 0, 0, 0, 2)1292QUANTIZE_ONE( 4, 8, 10, 12)1293QUANTIZE_ONE( 8, 16, 4, 8)1294QUANTIZE_ONE(12, 24, 14, 24)1295QUANTIZE_ONE(16, 32, 6, 16)1296QUANTIZE_ONE(20, 40, 22, 26)1297QUANTIZE_ONE(24, 48, 18, 20)1298QUANTIZE_ONE(28, 56, 28, 30)12991300: [temp0]"=&r"(temp0), [temp1]"=&r"(temp1),1301[temp2]"=&r"(temp2), [temp3]"=&r"(temp3),1302[temp4]"=&r"(temp4), [temp5]"=&r"(temp5),1303[sign]"=&r"(sign), [coeff]"=&r"(coeff),1304[level]"=&r"(level), [temp6]"=&r"(temp6), [ret]"+&r"(ret)1305: [ppin]"r"(ppin), [pout]"r"(pout), [max_level1]"r"(max_level1),1306[ppiq]"r"(ppiq), [max_level]"r"(max_level),1307[ppbias]"r"(ppbias), [ppzthresh]"r"(ppzthresh),1308[ppsharpen]"r"(ppsharpen), [ppq]"r"(ppq)1309: "memory", "hi", "lo"1310);13111312return (ret != 0);1313}13141315static int Quantize2Blocks_MIPSdspR2(int16_t in[32], int16_t out[32],1316const VP8Matrix* const mtx) {1317int nz;1318nz = QuantizeBlock_MIPSdspR2(in + 0 * 16, out + 0 * 16, mtx) << 0;1319nz |= QuantizeBlock_MIPSdspR2(in + 1 * 16, out + 1 * 16, mtx) << 1;1320return nz;1321}13221323#undef QUANTIZE_ONE13241325// macro for one horizontal pass in FTransformWHT1326// temp0..temp7 holds tmp[0]..tmp[15]1327// A, B, C, D - offset in bytes to load from in buffer1328// TEMP0, TEMP1 - registers for corresponding tmp elements1329#define HORIZONTAL_PASS_WHT(A, B, C, D, TEMP0, TEMP1) \1330"lh %[" #TEMP0 "], " #A "(%[in]) \n\t" \1331"lh %[" #TEMP1 "], " #B "(%[in]) \n\t" \1332"lh %[temp8], " #C "(%[in]) \n\t" \1333"lh %[temp9], " #D "(%[in]) \n\t" \1334"ins %[" #TEMP1 "], %[" #TEMP0 "], 16, 16 \n\t" \1335"ins %[temp9], %[temp8], 16, 16 \n\t" \1336"subq.ph %[temp8], %[" #TEMP1 "], %[temp9] \n\t" \1337"addq.ph %[temp9], %[" #TEMP1 "], %[temp9] \n\t" \1338"precrq.ph.w %[" #TEMP0 "], %[temp8], %[temp9] \n\t" \1339"append %[temp8], %[temp9], 16 \n\t" \1340"subq.ph %[" #TEMP1 "], %[" #TEMP0 "], %[temp8] \n\t" \1341"addq.ph %[" #TEMP0 "], %[" #TEMP0 "], %[temp8] \n\t" \1342"rotr %[" #TEMP1 "], %[" #TEMP1 "], 16 \n\t"13431344// macro for one vertical pass in FTransformWHT1345// temp0..temp7 holds tmp[0]..tmp[15]1346// A, B, C, D - offsets in bytes to store to out buffer1347// TEMP0, TEMP2, TEMP4 and TEMP6 - registers for corresponding tmp elements1348#define VERTICAL_PASS_WHT(A, B, C, D, TEMP0, TEMP2, TEMP4, TEMP6) \1349"addq.ph %[temp8], %[" #TEMP0 "], %[" #TEMP4 "] \n\t" \1350"addq.ph %[temp9], %[" #TEMP2 "], %[" #TEMP6 "] \n\t" \1351"subq.ph %[" #TEMP2 "], %[" #TEMP2 "], %[" #TEMP6 "] \n\t" \1352"subq.ph %[" #TEMP6 "], %[" #TEMP0 "], %[" #TEMP4 "] \n\t" \1353"addqh.ph %[" #TEMP0 "], %[temp8], %[temp9] \n\t" \1354"subqh.ph %[" #TEMP4 "], %[" #TEMP6 "], %[" #TEMP2 "] \n\t" \1355"addqh.ph %[" #TEMP2 "], %[" #TEMP2 "], %[" #TEMP6 "] \n\t" \1356"subqh.ph %[" #TEMP6 "], %[temp8], %[temp9] \n\t" \1357"usw %[" #TEMP0 "], " #A "(%[out]) \n\t" \1358"usw %[" #TEMP2 "], " #B "(%[out]) \n\t" \1359"usw %[" #TEMP4 "], " #C "(%[out]) \n\t" \1360"usw %[" #TEMP6 "], " #D "(%[out]) \n\t"13611362static void FTransformWHT_MIPSdspR2(const int16_t* in, int16_t* out) {1363int temp0, temp1, temp2, temp3, temp4;1364int temp5, temp6, temp7, temp8, temp9;13651366__asm__ volatile (1367HORIZONTAL_PASS_WHT( 0, 32, 64, 96, temp0, temp1)1368HORIZONTAL_PASS_WHT(128, 160, 192, 224, temp2, temp3)1369HORIZONTAL_PASS_WHT(256, 288, 320, 352, temp4, temp5)1370HORIZONTAL_PASS_WHT(384, 416, 448, 480, temp6, temp7)1371VERTICAL_PASS_WHT(0, 8, 16, 24, temp0, temp2, temp4, temp6)1372VERTICAL_PASS_WHT(4, 12, 20, 28, temp1, temp3, temp5, temp7)1373: [temp0]"=&r"(temp0), [temp1]"=&r"(temp1), [temp2]"=&r"(temp2),1374[temp3]"=&r"(temp3), [temp4]"=&r"(temp4), [temp5]"=&r"(temp5),1375[temp6]"=&r"(temp6), [temp7]"=&r"(temp7), [temp8]"=&r"(temp8),1376[temp9]"=&r"(temp9)1377: [in]"r"(in), [out]"r"(out)1378: "memory"1379);1380}13811382#undef VERTICAL_PASS_WHT1383#undef HORIZONTAL_PASS_WHT13841385// macro for converting coefficients to bin1386// convert 8 coeffs at time1387// A, B, C, D - offsets in bytes to load from out buffer1388#define CONVERT_COEFFS_TO_BIN(A, B, C, D) \1389"ulw %[temp0], " #A "(%[out]) \n\t" \1390"ulw %[temp1], " #B "(%[out]) \n\t" \1391"ulw %[temp2], " #C "(%[out]) \n\t" \1392"ulw %[temp3], " #D "(%[out]) \n\t" \1393"absq_s.ph %[temp0], %[temp0] \n\t" \1394"absq_s.ph %[temp1], %[temp1] \n\t" \1395"absq_s.ph %[temp2], %[temp2] \n\t" \1396"absq_s.ph %[temp3], %[temp3] \n\t" \1397"shra.ph %[temp0], %[temp0], 3 \n\t" \1398"shra.ph %[temp1], %[temp1], 3 \n\t" \1399"shra.ph %[temp2], %[temp2], 3 \n\t" \1400"shra.ph %[temp3], %[temp3], 3 \n\t" \1401"shll_s.ph %[temp0], %[temp0], 10 \n\t" \1402"shll_s.ph %[temp1], %[temp1], 10 \n\t" \1403"shll_s.ph %[temp2], %[temp2], 10 \n\t" \1404"shll_s.ph %[temp3], %[temp3], 10 \n\t" \1405"shrl.ph %[temp0], %[temp0], 10 \n\t" \1406"shrl.ph %[temp1], %[temp1], 10 \n\t" \1407"shrl.ph %[temp2], %[temp2], 10 \n\t" \1408"shrl.ph %[temp3], %[temp3], 10 \n\t" \1409"shll.ph %[temp0], %[temp0], 2 \n\t" \1410"shll.ph %[temp1], %[temp1], 2 \n\t" \1411"shll.ph %[temp2], %[temp2], 2 \n\t" \1412"shll.ph %[temp3], %[temp3], 2 \n\t" \1413"ext %[temp4], %[temp0], 0, 16 \n\t" \1414"ext %[temp0], %[temp0], 16, 16 \n\t" \1415"addu %[temp4], %[temp4], %[dist] \n\t" \1416"addu %[temp0], %[temp0], %[dist] \n\t" \1417"ext %[temp5], %[temp1], 0, 16 \n\t" \1418"lw %[temp8], 0(%[temp4]) \n\t" \1419"ext %[temp1], %[temp1], 16, 16 \n\t" \1420"addu %[temp5], %[temp5], %[dist] \n\t" \1421"addiu %[temp8], %[temp8], 1 \n\t" \1422"sw %[temp8], 0(%[temp4]) \n\t" \1423"lw %[temp8], 0(%[temp0]) \n\t" \1424"addu %[temp1], %[temp1], %[dist] \n\t" \1425"ext %[temp6], %[temp2], 0, 16 \n\t" \1426"addiu %[temp8], %[temp8], 1 \n\t" \1427"sw %[temp8], 0(%[temp0]) \n\t" \1428"lw %[temp8], 0(%[temp5]) \n\t" \1429"ext %[temp2], %[temp2], 16, 16 \n\t" \1430"addu %[temp6], %[temp6], %[dist] \n\t" \1431"addiu %[temp8], %[temp8], 1 \n\t" \1432"sw %[temp8], 0(%[temp5]) \n\t" \1433"lw %[temp8], 0(%[temp1]) \n\t" \1434"addu %[temp2], %[temp2], %[dist] \n\t" \1435"ext %[temp7], %[temp3], 0, 16 \n\t" \1436"addiu %[temp8], %[temp8], 1 \n\t" \1437"sw %[temp8], 0(%[temp1]) \n\t" \1438"lw %[temp8], 0(%[temp6]) \n\t" \1439"ext %[temp3], %[temp3], 16, 16 \n\t" \1440"addu %[temp7], %[temp7], %[dist] \n\t" \1441"addiu %[temp8], %[temp8], 1 \n\t" \1442"sw %[temp8], 0(%[temp6]) \n\t" \1443"lw %[temp8], 0(%[temp2]) \n\t" \1444"addu %[temp3], %[temp3], %[dist] \n\t" \1445"addiu %[temp8], %[temp8], 1 \n\t" \1446"sw %[temp8], 0(%[temp2]) \n\t" \1447"lw %[temp8], 0(%[temp7]) \n\t" \1448"addiu %[temp8], %[temp8], 1 \n\t" \1449"sw %[temp8], 0(%[temp7]) \n\t" \1450"lw %[temp8], 0(%[temp3]) \n\t" \1451"addiu %[temp8], %[temp8], 1 \n\t" \1452"sw %[temp8], 0(%[temp3]) \n\t"14531454static void CollectHistogram_MIPSdspR2(const uint8_t* ref, const uint8_t* pred,1455int start_block, int end_block,1456VP8Histogram* const histo) {1457int j;1458int distribution[MAX_COEFF_THRESH + 1] = { 0 };1459const int max_coeff = (MAX_COEFF_THRESH << 16) + MAX_COEFF_THRESH;1460for (j = start_block; j < end_block; ++j) {1461int16_t out[16];1462int temp0, temp1, temp2, temp3, temp4, temp5, temp6, temp7, temp8;14631464VP8FTransform(ref + VP8DspScan[j], pred + VP8DspScan[j], out);14651466// Convert coefficients to bin.1467__asm__ volatile (1468CONVERT_COEFFS_TO_BIN( 0, 4, 8, 12)1469CONVERT_COEFFS_TO_BIN(16, 20, 24, 28)1470: [temp0]"=&r"(temp0), [temp1]"=&r"(temp1), [temp2]"=&r"(temp2),1471[temp3]"=&r"(temp3), [temp4]"=&r"(temp4), [temp5]"=&r"(temp5),1472[temp6]"=&r"(temp6), [temp7]"=&r"(temp7), [temp8]"=&r"(temp8)1473: [dist]"r"(distribution), [out]"r"(out), [max_coeff]"r"(max_coeff)1474: "memory"1475);1476}1477VP8SetHistogramData(distribution, histo);1478}14791480#undef CONVERT_COEFFS_TO_BIN14811482//------------------------------------------------------------------------------1483// Entry point14841485extern void VP8EncDspInitMIPSdspR2(void);14861487WEBP_TSAN_IGNORE_FUNCTION void VP8EncDspInitMIPSdspR2(void) {1488VP8FTransform = FTransform_MIPSdspR2;1489VP8FTransformWHT = FTransformWHT_MIPSdspR2;1490VP8ITransform = ITransform_MIPSdspR2;14911492VP8TDisto4x4 = Disto4x4_MIPSdspR2;1493VP8TDisto16x16 = Disto16x16_MIPSdspR2;14941495VP8EncPredLuma16 = Intra16Preds_MIPSdspR2;1496VP8EncPredChroma8 = IntraChromaPreds_MIPSdspR2;1497VP8EncPredLuma4 = Intra4Preds_MIPSdspR2;14981499#if !defined(WORK_AROUND_GCC)1500VP8SSE16x16 = SSE16x16_MIPSdspR2;1501VP8SSE8x8 = SSE8x8_MIPSdspR2;1502VP8SSE16x8 = SSE16x8_MIPSdspR2;1503VP8SSE4x4 = SSE4x4_MIPSdspR2;1504#endif15051506VP8EncQuantizeBlock = QuantizeBlock_MIPSdspR2;1507VP8EncQuantize2Blocks = Quantize2Blocks_MIPSdspR2;15081509VP8CollectHistogram = CollectHistogram_MIPSdspR2;1510}15111512#else // !WEBP_USE_MIPS_DSP_R215131514WEBP_DSP_INIT_STUB(VP8EncDspInitMIPSdspR2)15151516#endif // WEBP_USE_MIPS_DSP_R2151715181519