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awilliam
GitHub Repository: awilliam/linux-vfio
 Path: blob/master/arch/alpha/include/asm/core_polaris.h
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#ifndef __ALPHA_POLARIS__H__

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#define __ALPHA_POLARIS__H__

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#include <linux/types.h>

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#include <asm/compiler.h>

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/*

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 * POLARIS is the internal name for a core logic chipset which provides

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 * memory controller and PCI access for the 21164PC chip based systems.

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 *

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 * This file is based on:

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 *

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 * Polaris System Controller

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 * Device Functional Specification

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 * 22-Jan-98

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 * Rev. 4.2

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 *

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 */

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/* Polaris memory regions */

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#define POLARIS_SPARSE_MEM_BASE		(IDENT_ADDR + 0xf800000000UL)

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#define POLARIS_DENSE_MEM_BASE		(IDENT_ADDR + 0xf900000000UL)

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#define POLARIS_SPARSE_IO_BASE		(IDENT_ADDR + 0xf980000000UL)

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#define POLARIS_SPARSE_CONFIG_BASE	(IDENT_ADDR + 0xf9c0000000UL)

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#define POLARIS_IACK_BASE		(IDENT_ADDR + 0xf9f8000000UL)

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#define POLARIS_DENSE_IO_BASE		(IDENT_ADDR + 0xf9fc000000UL)

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#define POLARIS_DENSE_CONFIG_BASE	(IDENT_ADDR + 0xf9fe000000UL)

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#define POLARIS_IACK_SC			POLARIS_IACK_BASE

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/* The Polaris command/status registers live in PCI Config space for

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 * bus 0/device 0.  As such, they may be bytes, words, or doublewords.

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 */

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#define POLARIS_W_VENID		(POLARIS_DENSE_CONFIG_BASE)

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#define POLARIS_W_DEVID		(POLARIS_DENSE_CONFIG_BASE+2)

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#define POLARIS_W_CMD		(POLARIS_DENSE_CONFIG_BASE+4)

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#define POLARIS_W_STATUS	(POLARIS_DENSE_CONFIG_BASE+6)

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/*

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 * Data structure for handling POLARIS machine checks:

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 */

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struct el_POLARIS_sysdata_mcheck {

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    u_long      psc_status;

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    u_long	psc_pcictl0;

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    u_long	psc_pcictl1;

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    u_long	psc_pcictl2;

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};

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#ifdef __KERNEL__

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#ifndef __EXTERN_INLINE

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#define __EXTERN_INLINE extern inline

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#define __IO_EXTERN_INLINE

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#endif

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/*

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 * I/O functions:

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 *

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 * POLARIS, the PCI/memory support chipset for the PCA56 (21164PC)

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 * processors, can use either a sparse address  mapping scheme, or the 

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 * so-called byte-word PCI address space, to get at PCI memory and I/O.

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 *

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 * However, we will support only the BWX form.

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 */

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/*

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 * Memory functions.  Polaris allows all accesses (byte/word

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 * as well as long/quad) to be done through dense space.

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 *

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 * We will only support DENSE access via BWX insns.

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 */

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__EXTERN_INLINE void __iomem *polaris_ioportmap(unsigned long addr)

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{

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	return (void __iomem *)(addr + POLARIS_DENSE_IO_BASE);

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}

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__EXTERN_INLINE void __iomem *polaris_ioremap(unsigned long addr,

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					      unsigned long size)

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{

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	return (void __iomem *)(addr + POLARIS_DENSE_MEM_BASE);

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}

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__EXTERN_INLINE int polaris_is_ioaddr(unsigned long addr)

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{

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	return addr >= POLARIS_SPARSE_MEM_BASE;

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}

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__EXTERN_INLINE int polaris_is_mmio(const volatile void __iomem *addr)

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{

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	return (unsigned long)addr < POLARIS_SPARSE_IO_BASE;

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}

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#undef __IO_PREFIX

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#define __IO_PREFIX		polaris

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#define polaris_trivial_rw_bw	1

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#define polaris_trivial_rw_lq	1

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#define polaris_trivial_io_bw	1

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#define polaris_trivial_io_lq	1

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#define polaris_trivial_iounmap	1

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#include <asm/io_trivial.h>

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#ifdef __IO_EXTERN_INLINE

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#undef __EXTERN_INLINE

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#undef __IO_EXTERN_INLINE

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#endif

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#endif /* __KERNEL__ */

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#endif /* __ALPHA_POLARIS__H__ */

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