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awilliam
GitHub Repository: awilliam/linux-vfio
 Path: blob/master/arch/alpha/kernel/irq_pyxis.c
10817 views
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/*

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 *	linux/arch/alpha/kernel/irq_pyxis.c

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 *

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 * Based on code written by David A Rusling ([email protected]).

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 *

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 * IRQ Code common to all PYXIS core logic chips.

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 */

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#include <linux/init.h>

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#include <linux/sched.h>

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#include <linux/irq.h>

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#include <asm/io.h>

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#include <asm/core_cia.h>

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#include "proto.h"

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#include "irq_impl.h"

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/* Note mask bit is true for ENABLED irqs.  */

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static unsigned long cached_irq_mask;

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static inline void

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pyxis_update_irq_hw(unsigned long mask)

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{

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	*(vulp)PYXIS_INT_MASK = mask;

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	mb();

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	*(vulp)PYXIS_INT_MASK;

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}

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static inline void

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pyxis_enable_irq(struct irq_data *d)

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{

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	pyxis_update_irq_hw(cached_irq_mask |= 1UL << (d->irq - 16));

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}

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static void

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pyxis_disable_irq(struct irq_data *d)

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{

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	pyxis_update_irq_hw(cached_irq_mask &= ~(1UL << (d->irq - 16)));

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}

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static void

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pyxis_mask_and_ack_irq(struct irq_data *d)

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{

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	unsigned long bit = 1UL << (d->irq - 16);

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	unsigned long mask = cached_irq_mask &= ~bit;

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	/* Disable the interrupt.  */

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	*(vulp)PYXIS_INT_MASK = mask;

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	wmb();

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	/* Ack PYXIS PCI interrupt.  */

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	*(vulp)PYXIS_INT_REQ = bit;

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	mb();

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	/* Re-read to force both writes.  */

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	*(vulp)PYXIS_INT_MASK;

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}

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static struct irq_chip pyxis_irq_type = {

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	.name		= "PYXIS",

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	.irq_mask_ack	= pyxis_mask_and_ack_irq,

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	.irq_mask	= pyxis_disable_irq,

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	.irq_unmask	= pyxis_enable_irq,

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};

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void 

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pyxis_device_interrupt(unsigned long vector)

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{

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	unsigned long pld;

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	unsigned int i;

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	/* Read the interrupt summary register of PYXIS */

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	pld = *(vulp)PYXIS_INT_REQ;

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	pld &= cached_irq_mask;

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	/*

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	 * Now for every possible bit set, work through them and call

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	 * the appropriate interrupt handler.

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	 */

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	while (pld) {

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		i = ffz(~pld);

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		pld &= pld - 1; /* clear least bit set */

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		if (i == 7)

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			isa_device_interrupt(vector);

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		else

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			handle_irq(16+i);

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	}

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}

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void __init

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init_pyxis_irqs(unsigned long ignore_mask)

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{

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	long i;

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	*(vulp)PYXIS_INT_MASK = 0;		/* disable all */

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	*(vulp)PYXIS_INT_REQ  = -1;		/* flush all */

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	mb();

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	/* Send -INTA pulses to clear any pending interrupts ...*/

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	*(vuip) CIA_IACK_SC;

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	for (i = 16; i < 48; ++i) {

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		if ((ignore_mask >> i) & 1)

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			continue;

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		irq_set_chip_and_handler(i, &pyxis_irq_type, handle_level_irq);

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		irq_set_status_flags(i, IRQ_LEVEL);

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	}

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	setup_irq(16+7, &isa_cascade_irqaction);

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}

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