Path: blob/master/arch/arm/boot/compressed/mmcif-sh7372.c
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/*1* sh7372 MMCIF loader2*3* Copyright (C) 2010 Magnus Damm4* Copyright (C) 2010 Simon Horman5*6* This file is subject to the terms and conditions of the GNU General Public7* License. See the file "COPYING" in the main directory of this archive8* for more details.9*/1011#include <linux/mmc/sh_mmcif.h>12#include <linux/mmc/boot.h>13#include <mach/mmc.h>1415#define MMCIF_BASE (void __iomem *)0xe6bd00001617#define PORT84CR (void __iomem *)0xe605005418#define PORT85CR (void __iomem *)0xe605005519#define PORT86CR (void __iomem *)0xe605005620#define PORT87CR (void __iomem *)0xe605005721#define PORT88CR (void __iomem *)0xe605005822#define PORT89CR (void __iomem *)0xe605005923#define PORT90CR (void __iomem *)0xe605005a24#define PORT91CR (void __iomem *)0xe605005b25#define PORT92CR (void __iomem *)0xe605005c26#define PORT99CR (void __iomem *)0xe60500632728#define SMSTPCR3 (void __iomem *)0xe615013c2930/* SH7372 specific MMCIF loader31*32* loads the zImage from an MMC card starting from block 1.33*34* The image must be start with a vrl4 header and35* the zImage must start at offset 512 of the image. That is,36* at block 2 (=byte 1024) on the media37*38* Use the following line to write the vrl4 formated zImage39* to an MMC card40* # dd if=vrl4.out of=/dev/sdx bs=512 seek=141*/42asmlinkage void mmcif_loader(unsigned char *buf, unsigned long len)43{44mmc_init_progress();45mmc_update_progress(MMC_PROGRESS_ENTER);4647/* Initialise MMC48* registers: PORT84CR-PORT92CR49* (MMCD0_0-MMCD0_7,MMCCMD0 Control)50* value: 0x04 - select function 451*/52__raw_writeb(0x04, PORT84CR);53__raw_writeb(0x04, PORT85CR);54__raw_writeb(0x04, PORT86CR);55__raw_writeb(0x04, PORT87CR);56__raw_writeb(0x04, PORT88CR);57__raw_writeb(0x04, PORT89CR);58__raw_writeb(0x04, PORT90CR);59__raw_writeb(0x04, PORT91CR);60__raw_writeb(0x04, PORT92CR);6162/* Initialise MMC63* registers: PORT99CR (MMCCLK0 Control)64* value: 0x10 | 0x04 - enable output | select function 465*/66__raw_writeb(0x14, PORT99CR);6768/* Enable clock to MMC hardware block */69__raw_writel(__raw_readl(SMSTPCR3) & ~(1 << 12), SMSTPCR3);7071mmc_update_progress(MMC_PROGRESS_INIT);7273/* setup MMCIF hardware */74sh_mmcif_boot_init(MMCIF_BASE);7576mmc_update_progress(MMC_PROGRESS_LOAD);7778/* load kernel via MMCIF interface */79sh_mmcif_boot_do_read(MMCIF_BASE, 2, /* Kernel is at block 2 */80(len + SH_MMCIF_BBS - 1) / SH_MMCIF_BBS, buf);818283/* Disable clock to MMC hardware block */84__raw_writel(__raw_readl(SMSTPCR3) & (1 << 12), SMSTPCR3);8586mmc_update_progress(MMC_PROGRESS_DONE);87}888990