/*****************************************************************************1* Copyright 2001 - 2009 Broadcom Corporation. All rights reserved.2*3* Unless you and Broadcom execute a separate written software license4* agreement governing use of this software, this software is licensed to you5* under the terms of the GNU General Public License version 2, available at6* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").7*8* Notwithstanding the above, under no circumstances may you combine this9* software in any way with any other Broadcom software provided under a10* license other than the GPL, without Broadcom's express prior written11* consent.12*****************************************************************************/13#include <mach/csp/chipcHw_def.h>1415#define CLK_TYPE_PRIMARY 1 /* primary clock must NOT have a parent */16#define CLK_TYPE_PLL1 2 /* PPL1 */17#define CLK_TYPE_PLL2 4 /* PPL2 */18#define CLK_TYPE_PROGRAMMABLE 8 /* programmable clock rate */19#define CLK_TYPE_BYPASSABLE 16 /* parent can be changed */2021#define CLK_MODE_XTAL 1 /* clock source is from crystal */2223struct clk {24const char *name; /* clock name */25unsigned int type; /* clock type */26unsigned int mode; /* current mode */27volatile int use_bypass; /* indicate if it's in bypass mode */28chipcHw_CLOCK_e csp_id; /* clock ID for CSP CHIPC */29unsigned long rate_hz; /* clock rate in Hz */30unsigned int use_cnt; /* usage count */31struct clk *parent; /* parent clock */32};333435