CoCalc -- dma_device.c

GitHub Repository: awilliam/linux-vfio
Path: blob/master/arch/arm/mach-bcmring/dma_device.c
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/*****************************************************************************
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* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
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*
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* Unless you and Broadcom execute a separate written software license
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* agreement governing use of this software, this software is licensed to you
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* under the terms of the GNU General Public License version 2, available at
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* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
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*
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* Notwithstanding the above, under no circumstances may you combine this
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* software in any way with any other Broadcom software provided under a
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* license other than the GPL, without Broadcom's express prior written
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* consent.
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*****************************************************************************/
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/****************************************************************************/
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/**
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*   @file   dma_device.c
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*
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*   @brief  private array of DMA_DeviceAttribute_t
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*/
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/****************************************************************************/
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DMA_DeviceAttribute_t DMA_gDeviceAttribute[DMA_NUM_DEVICE_ENTRIES] = {
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	[DMA_DEVICE_MEM_TO_MEM] =	/* MEM 2 MEM */
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	{
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	 .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
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	 .name = "mem-to-mem",
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	 .config = {
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		    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
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		    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
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		    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_MEM,
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		    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
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		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
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		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
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		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
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		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
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		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
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		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
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		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
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		    },
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	 },
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	[DMA_DEVICE_VPM_MEM_TO_MEM] =	/* VPM */
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	{
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	 .flags = DMA_DEVICE_FLAG_IS_DEDICATED | DMA_DEVICE_FLAG_NO_ISR,
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	 .name = "vpm",
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	 .dedicatedController = 0,
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	 .dedicatedChannel = 0,
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	 /* reserve DMA0:0 for VPM */
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	 },
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	[DMA_DEVICE_NAND_MEM_TO_MEM] =	/* NAND */
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	{
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	 .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
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	 .name = "nand",
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	 .config = {
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		    .srcPeripheralPort = 0,
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		    .dstPeripheralPort = 0,
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		    .srcStatusRegisterAddress = 0x00000000,
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		    .dstStatusRegisterAddress = 0x00000000,
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		    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_MEM,
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		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
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		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
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		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
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		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
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		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
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		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
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		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
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		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
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		    .channelPriority = dmacHw_CHANNEL_PRIORITY_6,
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		    },
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	 },
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	[DMA_DEVICE_PIF_MEM_TO_DEV] =	/* PIF TX */
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	{
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	 .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1
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	 | DMA_DEVICE_FLAG_ALLOW_LARGE_FIFO
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	 | DMA_DEVICE_FLAG_ALLOC_DMA1_FIRST | DMA_DEVICE_FLAG_PORT_PER_DMAC,
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	 .name = "pif_tx",
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	 .dmacPort = {14, 5},
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	 .config = {
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		    .srcPeripheralPort = 0,	/* SRC: memory */
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		    /* dstPeripheralPort          = 5 or 14 */
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		    .srcStatusRegisterAddress = 0x00000000,
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		    .dstStatusRegisterAddress = 0x00000000,
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		    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
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		    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
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		    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
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		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
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		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
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		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
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		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
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		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
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		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
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		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
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		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
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		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
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		    .maxDataPerBlock = 16256,
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		    },
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	 },
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	[DMA_DEVICE_PIF_DEV_TO_MEM] =	/* PIF RX */
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	{
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	 .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1
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	 | DMA_DEVICE_FLAG_ALLOW_LARGE_FIFO
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	 /* DMA_DEVICE_FLAG_ALLOC_DMA1_FIRST */
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	 | DMA_DEVICE_FLAG_PORT_PER_DMAC,
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	 .name = "pif_rx",
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	 .dmacPort = {14, 5},
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	 .config = {
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		    /* srcPeripheralPort          = 5 or 14 */
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		    .dstPeripheralPort = 0,	/* DST: memory */
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		    .srcStatusRegisterAddress = 0x00000000,
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		    .dstStatusRegisterAddress = 0x00000000,
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		    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
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		    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
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		    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
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		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
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		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
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		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
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		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
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		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
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		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
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		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
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		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
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		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
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		    .maxDataPerBlock = 16256,
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		    },
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	 },
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	[DMA_DEVICE_I2S0_DEV_TO_MEM] =	/* I2S RX */
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	{
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	 .flags = DMA_DEVICE_FLAG_ON_DMA0,
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	 .name = "i2s0_rx",
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	 .config = {
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		    .srcPeripheralPort = 0,	/* SRC: I2S0 */
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		    .dstPeripheralPort = 0,	/* DST: memory */
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		    .srcStatusRegisterAddress = 0,
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		    .dstStatusRegisterAddress = 0,
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		    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
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		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
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		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
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		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_16,
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		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
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		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
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		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_0,
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		    .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
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		    .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
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		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
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		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
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		    .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
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		    },
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	 },
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	[DMA_DEVICE_I2S0_MEM_TO_DEV] =	/* I2S TX */
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	{
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	 .flags = DMA_DEVICE_FLAG_ON_DMA0,
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	 .name = "i2s0_tx",
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	 .config = {
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		    .srcPeripheralPort = 0,	/* SRC: memory */
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		    .dstPeripheralPort = 1,	/* DST: I2S0 */
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		    .srcStatusRegisterAddress = 0,
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		    .dstStatusRegisterAddress = 0,
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		    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
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		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
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		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
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		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
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		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_16,
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		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_0,
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		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
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		    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
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		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
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		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
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		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
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		    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
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		    },
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	 },
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	[DMA_DEVICE_I2S1_DEV_TO_MEM] =	/* I2S1 RX */
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	{
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	 .flags = DMA_DEVICE_FLAG_ON_DMA1,
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	 .name = "i2s1_rx",
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	 .config = {
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		    .srcPeripheralPort = 2,	/* SRC: I2S1 */
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		    .dstPeripheralPort = 0,	/* DST: memory */
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		    .srcStatusRegisterAddress = 0,
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		    .dstStatusRegisterAddress = 0,
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		    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
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		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
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		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
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		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_16,
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		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
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		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
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		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_0,
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		    .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
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		    .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
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		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
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		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
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		    .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
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		    },
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	 },
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	[DMA_DEVICE_I2S1_MEM_TO_DEV] =	/* I2S1 TX */
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	{
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	 .flags = DMA_DEVICE_FLAG_ON_DMA1,
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	 .name = "i2s1_tx",
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	 .config = {
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		    .srcPeripheralPort = 0,	/* SRC: memory */
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		    .dstPeripheralPort = 3,	/* DST: I2S1 */
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		    .srcStatusRegisterAddress = 0,
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		    .dstStatusRegisterAddress = 0,
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		    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
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		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
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		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
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		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
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		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_16,
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		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_0,
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		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
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		    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
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		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
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		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
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		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
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		    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
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		    },
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	 },
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	[DMA_DEVICE_ESW_MEM_TO_DEV] =	/* ESW TX */
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	{
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	 .name = "esw_tx",
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	 .flags = DMA_DEVICE_FLAG_IS_DEDICATED,
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	 .dedicatedController = 1,
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	 .dedicatedChannel = 3,
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	 .config = {
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		    .srcPeripheralPort = 0,	/* SRC: memory */
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		    .dstPeripheralPort = 1,	/* DST: ESW (MTP) */
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		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
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		    .errorInterrupt = dmacHw_INTERRUPT_DISABLE,
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		    /* DMAx_AHB_SSTATARy */
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		    .srcStatusRegisterAddress = 0x00000000,
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		    /* DMAx_AHB_DSTATARy */
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		    .dstStatusRegisterAddress = 0x30490010,
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		    /* DMAx_AHB_CFGy */
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		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
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		    /* DMAx_AHB_CTLy */
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		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
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		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
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		    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
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		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_0,
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		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
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		    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
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		    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
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		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
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		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
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		    },
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	 },
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	[DMA_DEVICE_ESW_DEV_TO_MEM] =	/* ESW RX */
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	{
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	 .name = "esw_rx",
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	 .flags = DMA_DEVICE_FLAG_IS_DEDICATED,
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	 .dedicatedController = 1,
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	 .dedicatedChannel = 2,
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	 .config = {
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		    .srcPeripheralPort = 0,	/* SRC: ESW (PTM) */
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		    .dstPeripheralPort = 0,	/* DST: memory */
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		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
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		    .errorInterrupt = dmacHw_INTERRUPT_DISABLE,
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		    /* DMAx_AHB_SSTATARy */
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		    .srcStatusRegisterAddress = 0x30480010,
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		    /* DMAx_AHB_DSTATARy */
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		    .dstStatusRegisterAddress = 0x00000000,
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		    /* DMAx_AHB_CFGy */
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		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
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		    /* DMAx_AHB_CTLy */
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		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
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		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
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		    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
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		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
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		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_0,
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		    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
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		    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
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		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
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		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
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		    },
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	 },
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	[DMA_DEVICE_APM_CODEC_A_DEV_TO_MEM] =	/* APM Codec A Ingress */
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	{
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	 .flags = DMA_DEVICE_FLAG_ON_DMA0,
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	 .name = "apm_a_rx",
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	 .config = {
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		    .srcPeripheralPort = 2,	/* SRC: Codec A Ingress FIFO */
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		    .dstPeripheralPort = 0,	/* DST: memory */
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		    .srcStatusRegisterAddress = 0x00000000,
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		    .dstStatusRegisterAddress = 0x00000000,
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		    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
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		    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
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		    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
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		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
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		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
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		    .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
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		    .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
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		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
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		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
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		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
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		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
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		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
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		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
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		    .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
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		    },
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	 },
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	[DMA_DEVICE_APM_CODEC_A_MEM_TO_DEV] =	/* APM Codec A Egress */
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	{
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	 .flags = DMA_DEVICE_FLAG_ON_DMA0,
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	 .name = "apm_a_tx",
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	 .config = {
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		    .srcPeripheralPort = 0,	/* SRC: memory */
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		    .dstPeripheralPort = 3,	/* DST: Codec A Egress FIFO */
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		    .srcStatusRegisterAddress = 0x00000000,
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		    .dstStatusRegisterAddress = 0x00000000,
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		    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
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		    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
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		    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
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		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
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		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
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		    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
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		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
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		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
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		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
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		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
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		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
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		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
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		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
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		    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
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		    },
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	 },
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	[DMA_DEVICE_APM_CODEC_B_DEV_TO_MEM] =	/* APM Codec B Ingress */
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	{
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	 .flags = DMA_DEVICE_FLAG_ON_DMA0,
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	 .name = "apm_b_rx",
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	 .config = {
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		    .srcPeripheralPort = 4,	/* SRC: Codec B Ingress FIFO */
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		    .dstPeripheralPort = 0,	/* DST: memory */
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		    .srcStatusRegisterAddress = 0x00000000,
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		    .dstStatusRegisterAddress = 0x00000000,
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		    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
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		    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
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		    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
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		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
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		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
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		    .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
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		    .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
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		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
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		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
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		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
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		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
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		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
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		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
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		    .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
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		    },
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	 },
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	[DMA_DEVICE_APM_CODEC_B_MEM_TO_DEV] =	/* APM Codec B Egress */
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	{
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	 .flags = DMA_DEVICE_FLAG_ON_DMA0,
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	 .name = "apm_b_tx",
356
	 .config = {
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		    .srcPeripheralPort = 0,	/* SRC: memory */
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		    .dstPeripheralPort = 5,	/* DST: Codec B Egress FIFO */
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		    .srcStatusRegisterAddress = 0x00000000,
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		    .dstStatusRegisterAddress = 0x00000000,
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		    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
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		    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
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		    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
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		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
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		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
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		    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
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		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
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		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
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		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
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		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
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		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
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		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
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		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
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		    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
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		    },
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	 },
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	[DMA_DEVICE_APM_CODEC_C_DEV_TO_MEM] =	/* APM Codec C Ingress */
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	{
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	 .flags = DMA_DEVICE_FLAG_ON_DMA1,
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	 .name = "apm_c_rx",
381
	 .config = {
382
		    .srcPeripheralPort = 4,	/* SRC: Codec C Ingress FIFO */
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		    .dstPeripheralPort = 0,	/* DST: memory */
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		    .srcStatusRegisterAddress = 0x00000000,
385
		    .dstStatusRegisterAddress = 0x00000000,
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		    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
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		    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
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		    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
389
		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
390
		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
391
		    .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
392
		    .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
393
		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
394
		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
395
		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
396
		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
397
		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
398
		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
399
		    .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
400
		    },
401
	 },
402
	[DMA_DEVICE_APM_PCM0_DEV_TO_MEM] =	/* PCM0 RX */
403
	{
404
	 .flags = DMA_DEVICE_FLAG_ON_DMA0,
405
	 .name = "pcm0_rx",
406
	 .config = {
407
		    .srcPeripheralPort = 12,	/* SRC: PCM0 */
408
		    .dstPeripheralPort = 0,	/* DST: memory */
409
		    .srcStatusRegisterAddress = 0,
410
		    .dstStatusRegisterAddress = 0,
411
		    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
412
		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
413
		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
414
		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
415
		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
416
		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
417
		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
418
		    .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
419
		    .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
420
		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
421
		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
422
		    .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
423
		    },
424
	 },
425
	[DMA_DEVICE_APM_PCM0_MEM_TO_DEV] =	/* PCM0 TX */
426
	{
427
	 .flags = DMA_DEVICE_FLAG_ON_DMA0,
428
	 .name = "pcm0_tx",
429
	 .config = {
430
		    .srcPeripheralPort = 0,	/* SRC: memory */
431
		    .dstPeripheralPort = 13,	/* DST: PCM0 */
432
		    .srcStatusRegisterAddress = 0,
433
		    .dstStatusRegisterAddress = 0,
434
		    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
435
		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
436
		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
437
		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
438
		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
439
		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
440
		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
441
		    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
442
		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
443
		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
444
		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
445
		    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
446
		    },
447
	 },
448
	[DMA_DEVICE_APM_PCM1_DEV_TO_MEM] =	/* PCM1 RX */
449
	{
450
	 .flags = DMA_DEVICE_FLAG_ON_DMA1,
451
	 .name = "pcm1_rx",
452
	 .config = {
453
		    .srcPeripheralPort = 14,	/* SRC: PCM1 */
454
		    .dstPeripheralPort = 0,	/* DST: memory */
455
		    .srcStatusRegisterAddress = 0,
456
		    .dstStatusRegisterAddress = 0,
457
		    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
458
		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
459
		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
460
		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
461
		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
462
		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
463
		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
464
		    .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
465
		    .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
466
		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
467
		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
468
		    .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
469
		    },
470
	 },
471
	[DMA_DEVICE_APM_PCM1_MEM_TO_DEV] =	/* PCM1 TX */
472
	{
473
	 .flags = DMA_DEVICE_FLAG_ON_DMA1,
474
	 .name = "pcm1_tx",
475
	 .config = {
476
		    .srcPeripheralPort = 0,	/* SRC: memory */
477
		    .dstPeripheralPort = 15,	/* DST: PCM1 */
478
		    .srcStatusRegisterAddress = 0,
479
		    .dstStatusRegisterAddress = 0,
480
		    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
481
		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
482
		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
483
		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
484
		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
485
		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
486
		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
487
		    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
488
		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
489
		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
490
		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
491
		    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
492
		    },
493
	 },
494
	[DMA_DEVICE_SPUM_DEV_TO_MEM] =	/* SPUM RX */
495
	{
496
	 .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
497
	 .name = "spum_rx",
498
	 .config = {
499
		    .srcPeripheralPort = 6,	/* SRC: Codec A Ingress FIFO */
500
		    .dstPeripheralPort = 0,	/* DST: memory */
501
		    .srcStatusRegisterAddress = 0x00000000,
502
		    .dstStatusRegisterAddress = 0x00000000,
503
		    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
504
		    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
505
		    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
506
		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
507
		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
508
		    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
509
		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
510
		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
511
		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
512
		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
513
		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
514
		    /* Busrt size **MUST** be 16 for SPUM to work */
515
		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_16,
516
		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_16,
517
		    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
518
		    /* on the RX side, SPU needs to be the flow controller */
519
		    .flowControler = dmacHw_FLOW_CONTROL_PERIPHERAL,
520
		    },
521
	 },
522
	[DMA_DEVICE_SPUM_MEM_TO_DEV] =	/* SPUM TX */
523
	{
524
	 .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
525
	 .name = "spum_tx",
526
	 .config = {
527
		    .srcPeripheralPort = 0,	/* SRC: memory */
528
		    .dstPeripheralPort = 7,	/* DST: SPUM */
529
		    .srcStatusRegisterAddress = 0x00000000,
530
		    .dstStatusRegisterAddress = 0x00000000,
531
		    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
532
		    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
533
		    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
534
		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
535
		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
536
		    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
537
		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
538
		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
539
		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
540
		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
541
		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
542
		    /* Busrt size **MUST** be 16 for SPUM to work */
543
		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_16,
544
		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_16,
545
		    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
546
		    },
547
	 },
548
	[DMA_DEVICE_MEM_TO_VRAM] =	/* MEM 2 VRAM */
549
	{
550
	 .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
551
	 .name = "mem-to-vram",
552
	 .config = {
553
		    .srcPeripheralPort = 0,	/* SRC: memory */
554
		    .srcStatusRegisterAddress = 0x00000000,
555
		    .dstStatusRegisterAddress = 0x00000000,
556
		    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
557
		    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
558
		    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_MEM,
559
		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
560
		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
561
		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
562
		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
563
		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
564
		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
565
		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
566
		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
567
		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
568
		    },
569
	 },
570
	[DMA_DEVICE_VRAM_TO_MEM] =	/* VRAM 2 MEM */
571
	{
572
	 .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
573
	 .name = "vram-to-mem",
574
	 .config = {
575
		    .dstPeripheralPort = 0,	/* DST: memory */
576
		    .srcStatusRegisterAddress = 0x00000000,
577
		    .dstStatusRegisterAddress = 0x00000000,
578
		    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
579
		    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
580
		    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_MEM,
581
		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
582
		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
583
		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
584
		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
585
		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
586
		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
587
		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
588
		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
589
		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
590
		    },
591
	 },
592
};
593
EXPORT_SYMBOL(DMA_gDeviceAttribute);	/* primarily for dma-test.c */
594

595
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