Path: blob/master/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h
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/*****************************************************************************1* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved.2*3* Unless you and Broadcom execute a separate written software license4* agreement governing use of this software, this software is licensed to you5* under the terms of the GNU General Public License version 2, available at6* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").7*8* Notwithstanding the above, under no circumstances may you combine this9* software in any way with any other Broadcom software provided under a10* license other than the GPL, without Broadcom's express prior written11* consent.12*****************************************************************************/1314/****************************************************************************/15/**16* @file chipcHw_reg.h17*18* @brief Definitions for low level chip control registers19*20*/21/****************************************************************************/22#ifndef CHIPCHW_REG_H23#define CHIPCHW_REG_H2425#include <mach/csp/mm_io.h>26#include <csp/reg.h>27#include <mach/csp/ddrcReg.h>2829#define chipcHw_BASE_ADDRESS MM_IO_BASE_CHIPC3031typedef struct {32uint32_t ChipId; /* Chip ID */33uint32_t DDRClock; /* PLL1 Channel 1 for DDR clock */34uint32_t ARMClock; /* PLL1 Channel 2 for ARM clock */35uint32_t ESWClock; /* PLL1 Channel 3 for ESW system clock */36uint32_t VPMClock; /* PLL1 Channel 4 for VPM clock */37uint32_t ESW125Clock; /* PLL1 Channel 5 for ESW 125MHz clock */38uint32_t UARTClock; /* PLL1 Channel 6 for UART clock */39uint32_t SDIO0Clock; /* PLL1 Channel 7 for SDIO 0 clock */40uint32_t SDIO1Clock; /* PLL1 Channel 8 for SDIO 1 clock */41uint32_t SPIClock; /* PLL1 Channel 9 for SPI master Clock */42uint32_t ETMClock; /* PLL1 Channel 10 for ARM ETM Clock */4344uint32_t ACLKClock; /* ACLK Clock (Divider) */45uint32_t OTPClock; /* OTP Clock (Divider) */46uint32_t I2CClock; /* I2C Clock (CK_13m) (Divider) */47uint32_t I2S0Clock; /* I2S0 Clock (Divider) */48uint32_t RTBUSClock; /* RTBUS (DDR PHY Config.) Clock (Divider) */49uint32_t pad1;50uint32_t APM100Clock; /* APM 100MHz CLK Clock (Divider) */51uint32_t TSCClock; /* TSC Clock (Divider) */52uint32_t LEDClock; /* LED Clock (Divider) */5354uint32_t USBClock; /* PLL2 Channel 1 for USB clock */55uint32_t LCDClock; /* PLL2 Channel 2 for LCD clock */56uint32_t APMClock; /* PLL2 Channel 3 for APM 200 MHz clock */5758uint32_t BusIntfClock; /* Bus interface clock */5960uint32_t PLLStatus; /* PLL status register (PLL1) */61uint32_t PLLConfig; /* PLL configuration register (PLL1) */62uint32_t PLLPreDivider; /* PLL pre-divider control register (PLL1) */63uint32_t PLLDivider; /* PLL divider control register (PLL1) */64uint32_t PLLControl1; /* PLL analog control register #1 (PLL1) */65uint32_t PLLControl2; /* PLL analog control register #2 (PLL1) */6667uint32_t I2S1Clock; /* I2S1 Clock */68uint32_t AudioEnable; /* Enable/ disable audio channel */69uint32_t SoftReset1; /* Reset blocks */70uint32_t SoftReset2; /* Reset blocks */71uint32_t Spare1; /* Phase align interrupts */72uint32_t Sticky; /* Sticky bits */73uint32_t MiscCtrl; /* Misc. control */74uint32_t pad3[3];7576uint32_t PLLStatus2; /* PLL status register (PLL2) */77uint32_t PLLConfig2; /* PLL configuration register (PLL2) */78uint32_t PLLPreDivider2; /* PLL pre-divider control register (PLL2) */79uint32_t PLLDivider2; /* PLL divider control register (PLL2) */80uint32_t PLLControl12; /* PLL analog control register #1 (PLL2) */81uint32_t PLLControl22; /* PLL analog control register #2 (PLL2) */8283uint32_t DDRPhaseCtrl1; /* DDR Clock Phase Alignment control1 */84uint32_t VPMPhaseCtrl1; /* VPM Clock Phase Alignment control1 */85uint32_t PhaseAlignStatus; /* DDR/VPM Clock Phase Alignment Status */86uint32_t PhaseCtrlStatus; /* DDR/VPM Clock HW DDR/VPM ph_ctrl and load_ch Status */87uint32_t DDRPhaseCtrl2; /* DDR Clock Phase Alignment control2 */88uint32_t VPMPhaseCtrl2; /* VPM Clock Phase Alignment control2 */89uint32_t pad4[9];9091uint32_t SoftOTP1; /* Software OTP control */92uint32_t SoftOTP2; /* Software OTP control */93uint32_t SoftStraps; /* Software strap */94uint32_t PinStraps; /* Pin Straps */95uint32_t DiffOscCtrl; /* Diff oscillator control */96uint32_t DiagsCtrl; /* Diagnostic control */97uint32_t DiagsOutputCtrl; /* Diagnostic output enable */98uint32_t DiagsReadBackCtrl; /* Diagnostic read back control */99100uint32_t LcdPifMode; /* LCD/PIF Pin Sharing MUX Mode */101102uint32_t GpioMux_0_7; /* Pin Sharing MUX0 Control */103uint32_t GpioMux_8_15; /* Pin Sharing MUX1 Control */104uint32_t GpioMux_16_23; /* Pin Sharing MUX2 Control */105uint32_t GpioMux_24_31; /* Pin Sharing MUX3 Control */106uint32_t GpioMux_32_39; /* Pin Sharing MUX4 Control */107uint32_t GpioMux_40_47; /* Pin Sharing MUX5 Control */108uint32_t GpioMux_48_55; /* Pin Sharing MUX6 Control */109uint32_t GpioMux_56_63; /* Pin Sharing MUX7 Control */110111uint32_t GpioSR_0_7; /* Slew rate for GPIO 0 - 7 */112uint32_t GpioSR_8_15; /* Slew rate for GPIO 8 - 15 */113uint32_t GpioSR_16_23; /* Slew rate for GPIO 16 - 23 */114uint32_t GpioSR_24_31; /* Slew rate for GPIO 24 - 31 */115uint32_t GpioSR_32_39; /* Slew rate for GPIO 32 - 39 */116uint32_t GpioSR_40_47; /* Slew rate for GPIO 40 - 47 */117uint32_t GpioSR_48_55; /* Slew rate for GPIO 48 - 55 */118uint32_t GpioSR_56_63; /* Slew rate for GPIO 56 - 63 */119uint32_t MiscSR_0_7; /* Slew rate for MISC 0 - 7 */120uint32_t MiscSR_8_15; /* Slew rate for MISC 8 - 15 */121122uint32_t GpioPull_0_15; /* Pull up registers for GPIO 0 - 15 */123uint32_t GpioPull_16_31; /* Pull up registers for GPIO 16 - 31 */124uint32_t GpioPull_32_47; /* Pull up registers for GPIO 32 - 47 */125uint32_t GpioPull_48_63; /* Pull up registers for GPIO 48 - 63 */126uint32_t MiscPull_0_15; /* Pull up registers for MISC 0 - 15 */127128uint32_t GpioInput_0_31; /* Input type for GPIO 0 - 31 */129uint32_t GpioInput_32_63; /* Input type for GPIO 32 - 63 */130uint32_t MiscInput_0_15; /* Input type for MISC 0 - 16 */131} chipcHw_REG_t;132133#define pChipcHw ((volatile chipcHw_REG_t *) chipcHw_BASE_ADDRESS)134#define pChipcPhysical ((volatile chipcHw_REG_t *) MM_ADDR_IO_CHIPC)135136#define chipcHw_REG_CHIPID_BASE_MASK 0xFFFFF000137#define chipcHw_REG_CHIPID_BASE_SHIFT 12138#define chipcHw_REG_CHIPID_REV_MASK 0x00000FFF139#define chipcHw_REG_REV_A0 0xA00140#define chipcHw_REG_REV_B0 0x0B0141142#define chipcHw_REG_PLL_STATUS_CONTROL_ENABLE 0x80000000 /* Allow controlling PLL registers */143#define chipcHw_REG_PLL_STATUS_LOCKED 0x00000001 /* PLL is settled */144#define chipcHw_REG_PLL_CONFIG_D_RESET 0x00000008 /* Digital reset */145#define chipcHw_REG_PLL_CONFIG_A_RESET 0x00000004 /* Analog reset */146#define chipcHw_REG_PLL_CONFIG_BYPASS_ENABLE 0x00000020 /* Bypass enable */147#define chipcHw_REG_PLL_CONFIG_OUTPUT_ENABLE 0x00000010 /* Output enable */148#define chipcHw_REG_PLL_CONFIG_POWER_DOWN 0x00000001 /* Power down */149#define chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ 1600000000 /* 1.6GHz VCO split frequency */150#define chipcHw_REG_PLL_CONFIG_VCO_800_1600 0x00000000 /* VCO range 800-1600 MHz */151#define chipcHw_REG_PLL_CONFIG_VCO_1601_3200 0x00000080 /* VCO range 1601-3200 MHz */152#define chipcHw_REG_PLL_CONFIG_TEST_ENABLE 0x00010000 /* PLL test output enable */153#define chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK 0x003E0000 /* Mask to set test values */154#define chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT 17155156#define chipcHw_REG_PLL_CLOCK_PHASE_COMP 0x00800000 /* Phase comparator output */157#define chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK 0x00300000 /* Clock to bus ratio mask */158#define chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT 20 /* Number of bits to be shifted */159#define chipcHw_REG_PLL_CLOCK_POWER_DOWN 0x00080000 /* PLL channel power down */160#define chipcHw_REG_PLL_CLOCK_SOURCE_GPIO 0x00040000 /* Use GPIO as source */161#define chipcHw_REG_PLL_CLOCK_BYPASS_SELECT 0x00020000 /* Select bypass clock */162#define chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE 0x00010000 /* Clock gated ON */163#define chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE 0x00008000 /* Clock phase update enable */164#define chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT 8 /* Number of bits to be shifted */165#define chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK 0x00003F00 /* Phase control mask */166#define chipcHw_REG_PLL_CLOCK_MDIV_MASK 0x000000FF /* Clock post divider mask16716800000000 = divide-by-25616900000001 = divide-by-117000000010 = divide-by-217100000011 = divide-by-317200000100 = divide-by-417300000101 = divide-by-517400000110 = divide-by-6175.176.17711111011 = divide-by-25117811111100 = divide-by-25217911111101 = divide-by-25318011111110 = divide-by-254181*/182183#define chipcHw_REG_DIV_CLOCK_SOURCE_OTHER 0x00040000 /* NON-PLL clock source select */184#define chipcHw_REG_DIV_CLOCK_BYPASS_SELECT 0x00020000 /* NON-PLL clock bypass enable */185#define chipcHw_REG_DIV_CLOCK_OUTPUT_ENABLE 0x00010000 /* NON-PLL clock output enable */186#define chipcHw_REG_DIV_CLOCK_DIV_MASK 0x000000FF /* NON-PLL clock post-divide mask */187#define chipcHw_REG_DIV_CLOCK_DIV_256 0x00000000 /* NON-PLL clock post-divide by 256 */188189#define chipcHw_REG_PLL_PREDIVIDER_P1_SHIFT 0190#define chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT 4191#define chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT 8192#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK 0x0001FF00193#define chipcHw_REG_PLL_PREDIVIDER_POWER_DOWN 0x02000000194#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK 0x00700000 /* Divider mask */195#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER 0x00000000 /* Integer-N Mode */196#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASH_UNIT 0x00100000 /* MASH Sigma-Delta Modulator Unit Mode */197#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MFB_UNIT 0x00200000 /* MFB Sigma-Delta Modulator Unit Mode */198#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASH_1_8 0x00300000 /* MASH Sigma-Delta Modulator 1/8 Mode */199#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MFB_1_8 0x00400000 /* MFB Sigma-Delta Modulator 1/8 Mode */200201#define chipcHw_REG_PLL_PREDIVIDER_NDIV_i(vco) ((vco) / chipcHw_XTAL_FREQ_Hz)202#define chipcHw_REG_PLL_PREDIVIDER_P1 1203#define chipcHw_REG_PLL_PREDIVIDER_P2 1204205#define chipcHw_REG_PLL_DIVIDER_M1DIV 0x03000000206#define chipcHw_REG_PLL_DIVIDER_FRAC 0x00FFFFFF /* Fractional divider */207208#define chipcHw_REG_PLL_DIVIDER_NDIV_f_SS (0x00FFFFFF) /* To attain spread with max frequency */209210#define chipcHw_REG_PLL_DIVIDER_NDIV_f 0 /* ndiv_frac = chipcHw_REG_PLL_DIVIDER_NDIV_f /211chipcHw_REG_PLL_DIVIDER_FRAC212= 0, when SS is disable213*/214215#define chipcHw_REG_PLL_DIVIDER_MDIV(vco, Hz) ((chipcHw_divide((vco), (Hz)) > 255) ? 0 : chipcHw_divide((vco), (Hz)))216217#define chipcHw_REG_ACLKClock_CLK_DIV_MASK 0x3218219/* System booting strap options */220#define chipcHw_STRAPS_SOFT_OVERRIDE 0x00000001 /* Software Strap Override */221222#define chipcHw_STRAPS_BOOT_DEVICE_NAND_FLASH_8 0x00000000 /* 8 bit NAND FLASH Boot */223#define chipcHw_STRAPS_BOOT_DEVICE_NOR_FLASH_16 0x00000002 /* 16 bit NOR FLASH Boot */224#define chipcHw_STRAPS_BOOT_DEVICE_SERIAL_FLASH 0x00000004 /* Serial FLASH Boot */225#define chipcHw_STRAPS_BOOT_DEVICE_NAND_FLASH_16 0x00000006 /* 16 bit NAND FLASH Boot */226#define chipcHw_STRAPS_BOOT_DEVICE_UART 0x00000008 /* UART Boot */227#define chipcHw_STRAPS_BOOT_DEVICE_MASK 0x0000000E /* Mask */228229/* System boot option */230#define chipcHw_STRAPS_BOOT_OPTION_BROM 0x00000000 /* Boot from Boot ROM */231#define chipcHw_STRAPS_BOOT_OPTION_ARAM 0x00000020 /* Boot from ARAM */232#define chipcHw_STRAPS_BOOT_OPTION_NOR 0x00000030 /* Boot from NOR flash */233234/* NAND Flash page size strap options */235#define chipcHw_STRAPS_NAND_PAGESIZE_512 0x00000000 /* NAND FLASH page size of 512 bytes */236#define chipcHw_STRAPS_NAND_PAGESIZE_2048 0x00000040 /* NAND FLASH page size of 2048 bytes */237#define chipcHw_STRAPS_NAND_PAGESIZE_4096 0x00000080 /* NAND FLASH page size of 4096 bytes */238#define chipcHw_STRAPS_NAND_PAGESIZE_EXT 0x000000C0 /* NAND FLASH page of extened size */239#define chipcHw_STRAPS_NAND_PAGESIZE_MASK 0x000000C0 /* Mask */240241#define chipcHw_STRAPS_NAND_EXTRA_CYCLE 0x00000400 /* NAND FLASH address cycle configuration */242#define chipcHw_STRAPS_REBOOT_TO_UART 0x00000800 /* Reboot to UART on error */243244/* Secure boot mode strap options */245#define chipcHw_STRAPS_BOOT_MODE_NORMAL 0x00000000 /* Normal Boot */246#define chipcHw_STRAPS_BOOT_MODE_DBG_SW 0x00000100 /* Software debugging Boot */247#define chipcHw_STRAPS_BOOT_MODE_DBG_BOOT 0x00000200 /* Boot rom debugging Boot */248#define chipcHw_STRAPS_BOOT_MODE_NORMAL_QUIET 0x00000300 /* Normal Boot (Quiet BootRom) */249#define chipcHw_STRAPS_BOOT_MODE_MASK 0x00000300 /* Mask */250251/* Slave Mode straps */252#define chipcHw_STRAPS_I2CS 0x02000000 /* I2C Slave */253#define chipcHw_STRAPS_SPIS 0x01000000 /* SPI Slave */254255/* Strap pin options */256#define chipcHw_REG_SW_STRAPS ((pChipcHw->PinStraps & 0x0000FC00) >> 10)257258/* PIF/LCD pin sharing defines */259#define chipcHw_REG_LCD_PIN_ENABLE 0x00000001 /* LCD Controller is used and the pins have LCD functions */260#define chipcHw_REG_PIF_PIN_ENABLE 0x00000002 /* LCD pins are used to perform PIF functions */261262#define chipcHw_GPIO_COUNT 61 /* Number of GPIO pin accessible thorugh CHIPC */263264/* NOTE: Any changes to these constants will require a corresponding change to chipcHw_str.c */265#define chipcHw_REG_GPIO_MUX_KEYPAD 0x00000001 /* GPIO mux for Keypad */266#define chipcHw_REG_GPIO_MUX_I2CH 0x00000002 /* GPIO mux for I2CH */267#define chipcHw_REG_GPIO_MUX_SPI 0x00000003 /* GPIO mux for SPI */268#define chipcHw_REG_GPIO_MUX_UART 0x00000004 /* GPIO mux for UART */269#define chipcHw_REG_GPIO_MUX_LEDMTXP 0x00000005 /* GPIO mux for LEDMTXP */270#define chipcHw_REG_GPIO_MUX_LEDMTXS 0x00000006 /* GPIO mux for LEDMTXS */271#define chipcHw_REG_GPIO_MUX_SDIO0 0x00000007 /* GPIO mux for SDIO0 */272#define chipcHw_REG_GPIO_MUX_SDIO1 0x00000008 /* GPIO mux for SDIO1 */273#define chipcHw_REG_GPIO_MUX_PCM 0x00000009 /* GPIO mux for PCM */274#define chipcHw_REG_GPIO_MUX_I2S 0x0000000A /* GPIO mux for I2S */275#define chipcHw_REG_GPIO_MUX_ETM 0x0000000B /* GPIO mux for ETM */276#define chipcHw_REG_GPIO_MUX_DEBUG 0x0000000C /* GPIO mux for DEBUG */277#define chipcHw_REG_GPIO_MUX_MISC 0x0000000D /* GPIO mux for MISC */278#define chipcHw_REG_GPIO_MUX_GPIO 0x00000000 /* GPIO mux for GPIO */279#define chipcHw_REG_GPIO_MUX(pin) (&pChipcHw->GpioMux_0_7 + ((pin) >> 3))280#define chipcHw_REG_GPIO_MUX_POSITION(pin) (((pin) & 0x00000007) << 2)281#define chipcHw_REG_GPIO_MUX_MASK 0x0000000F /* Mask */282283#define chipcHw_REG_SLEW_RATE_HIGH 0x00000000 /* High speed slew rate */284#define chipcHw_REG_SLEW_RATE_NORMAL 0x00000008 /* Normal slew rate */285/* Pins beyond 42 are defined by skipping 8 bits within the register */286#define chipcHw_REG_SLEW_RATE(pin) (((pin) > 42) ? (&pChipcHw->GpioSR_0_7 + (((pin) + 2) >> 3)) : (&pChipcHw->GpioSR_0_7 + ((pin) >> 3)))287#define chipcHw_REG_SLEW_RATE_POSITION(pin) (((pin) > 42) ? ((((pin) + 2) & 0x00000007) << 2) : (((pin) & 0x00000007) << 2))288#define chipcHw_REG_SLEW_RATE_MASK 0x00000008 /* Mask */289290#define chipcHw_REG_CURRENT_STRENGTH_2mA 0x00000001 /* Current driving strength 2 milli ampere */291#define chipcHw_REG_CURRENT_STRENGTH_4mA 0x00000002 /* Current driving strength 4 milli ampere */292#define chipcHw_REG_CURRENT_STRENGTH_6mA 0x00000004 /* Current driving strength 6 milli ampere */293#define chipcHw_REG_CURRENT_STRENGTH_8mA 0x00000005 /* Current driving strength 8 milli ampere */294#define chipcHw_REG_CURRENT_STRENGTH_10mA 0x00000006 /* Current driving strength 10 milli ampere */295#define chipcHw_REG_CURRENT_STRENGTH_12mA 0x00000007 /* Current driving strength 12 milli ampere */296#define chipcHw_REG_CURRENT_MASK 0x00000007 /* Mask */297/* Pins beyond 42 are defined by skipping 8 bits */298#define chipcHw_REG_CURRENT(pin) (((pin) > 42) ? (&pChipcHw->GpioSR_0_7 + (((pin) + 2) >> 3)) : (&pChipcHw->GpioSR_0_7 + ((pin) >> 3)))299#define chipcHw_REG_CURRENT_POSITION(pin) (((pin) > 42) ? ((((pin) + 2) & 0x00000007) << 2) : (((pin) & 0x00000007) << 2))300301#define chipcHw_REG_PULL_NONE 0x00000000 /* No pull up register */302#define chipcHw_REG_PULL_UP 0x00000001 /* Pull up register enable */303#define chipcHw_REG_PULL_DOWN 0x00000002 /* Pull down register enable */304#define chipcHw_REG_PULLUP_MASK 0x00000003 /* Mask */305/* Pins beyond 42 are defined by skipping 4 bits */306#define chipcHw_REG_PULLUP(pin) (((pin) > 42) ? (&pChipcHw->GpioPull_0_15 + (((pin) + 2) >> 4)) : (&pChipcHw->GpioPull_0_15 + ((pin) >> 4)))307#define chipcHw_REG_PULLUP_POSITION(pin) (((pin) > 42) ? ((((pin) + 2) & 0x0000000F) << 1) : (((pin) & 0x0000000F) << 1))308309#define chipcHw_REG_INPUTTYPE_CMOS 0x00000000 /* Normal CMOS logic */310#define chipcHw_REG_INPUTTYPE_ST 0x00000001 /* High speed Schmitt Trigger */311#define chipcHw_REG_INPUTTYPE_MASK 0x00000001 /* Mask */312/* Pins beyond 42 are defined by skipping 2 bits */313#define chipcHw_REG_INPUTTYPE(pin) (((pin) > 42) ? (&pChipcHw->GpioInput_0_31 + (((pin) + 2) >> 5)) : (&pChipcHw->GpioInput_0_31 + ((pin) >> 5)))314#define chipcHw_REG_INPUTTYPE_POSITION(pin) (((pin) > 42) ? ((((pin) + 2) & 0x0000001F)) : (((pin) & 0x0000001F)))315316/* Device connected to the bus clock */317#define chipcHw_REG_BUS_CLOCK_ARM 0x00000001 /* Bus interface clock for ARM */318#define chipcHw_REG_BUS_CLOCK_VDEC 0x00000002 /* Bus interface clock for VDEC */319#define chipcHw_REG_BUS_CLOCK_ARAM 0x00000004 /* Bus interface clock for ARAM */320#define chipcHw_REG_BUS_CLOCK_HPM 0x00000008 /* Bus interface clock for HPM */321#define chipcHw_REG_BUS_CLOCK_DDRC 0x00000010 /* Bus interface clock for DDRC */322#define chipcHw_REG_BUS_CLOCK_DMAC0 0x00000020 /* Bus interface clock for DMAC0 */323#define chipcHw_REG_BUS_CLOCK_DMAC1 0x00000040 /* Bus interface clock for DMAC1 */324#define chipcHw_REG_BUS_CLOCK_NVI 0x00000080 /* Bus interface clock for NVI */325#define chipcHw_REG_BUS_CLOCK_ESW 0x00000100 /* Bus interface clock for ESW */326#define chipcHw_REG_BUS_CLOCK_GE 0x00000200 /* Bus interface clock for GE */327#define chipcHw_REG_BUS_CLOCK_I2CH 0x00000400 /* Bus interface clock for I2CH */328#define chipcHw_REG_BUS_CLOCK_I2S0 0x00000800 /* Bus interface clock for I2S0 */329#define chipcHw_REG_BUS_CLOCK_I2S1 0x00001000 /* Bus interface clock for I2S1 */330#define chipcHw_REG_BUS_CLOCK_VRAM 0x00002000 /* Bus interface clock for VRAM */331#define chipcHw_REG_BUS_CLOCK_CLCD 0x00004000 /* Bus interface clock for CLCD */332#define chipcHw_REG_BUS_CLOCK_LDK 0x00008000 /* Bus interface clock for LDK */333#define chipcHw_REG_BUS_CLOCK_LED 0x00010000 /* Bus interface clock for LED */334#define chipcHw_REG_BUS_CLOCK_OTP 0x00020000 /* Bus interface clock for OTP */335#define chipcHw_REG_BUS_CLOCK_PIF 0x00040000 /* Bus interface clock for PIF */336#define chipcHw_REG_BUS_CLOCK_SPU 0x00080000 /* Bus interface clock for SPU */337#define chipcHw_REG_BUS_CLOCK_SDIO0 0x00100000 /* Bus interface clock for SDIO0 */338#define chipcHw_REG_BUS_CLOCK_SDIO1 0x00200000 /* Bus interface clock for SDIO1 */339#define chipcHw_REG_BUS_CLOCK_SPIH 0x00400000 /* Bus interface clock for SPIH */340#define chipcHw_REG_BUS_CLOCK_SPIS 0x00800000 /* Bus interface clock for SPIS */341#define chipcHw_REG_BUS_CLOCK_UART0 0x01000000 /* Bus interface clock for UART0 */342#define chipcHw_REG_BUS_CLOCK_UART1 0x02000000 /* Bus interface clock for UART1 */343#define chipcHw_REG_BUS_CLOCK_BBL 0x04000000 /* Bus interface clock for BBL */344#define chipcHw_REG_BUS_CLOCK_I2CS 0x08000000 /* Bus interface clock for I2CS */345#define chipcHw_REG_BUS_CLOCK_USBH 0x10000000 /* Bus interface clock for USB Host */346#define chipcHw_REG_BUS_CLOCK_USBD 0x20000000 /* Bus interface clock for USB Device */347#define chipcHw_REG_BUS_CLOCK_BROM 0x40000000 /* Bus interface clock for Boot ROM */348#define chipcHw_REG_BUS_CLOCK_TSC 0x80000000 /* Bus interface clock for Touch screen */349350/* Software resets defines */351#define chipcHw_REG_SOFT_RESET_VPM_GLOBAL_HOLD 0x0000000080000000ULL /* Reset Global VPM and hold */352#define chipcHw_REG_SOFT_RESET_VPM_HOLD 0x0000000040000000ULL /* Reset VPM and hold */353#define chipcHw_REG_SOFT_RESET_VPM_GLOBAL 0x0000000020000000ULL /* Reset Global VPM */354#define chipcHw_REG_SOFT_RESET_VPM 0x0000000010000000ULL /* Reset VPM */355#define chipcHw_REG_SOFT_RESET_KEYPAD 0x0000000008000000ULL /* Reset Key pad */356#define chipcHw_REG_SOFT_RESET_LED 0x0000000004000000ULL /* Reset LED */357#define chipcHw_REG_SOFT_RESET_SPU 0x0000000002000000ULL /* Reset SPU */358#define chipcHw_REG_SOFT_RESET_RNG 0x0000000001000000ULL /* Reset RNG */359#define chipcHw_REG_SOFT_RESET_PKA 0x0000000000800000ULL /* Reset PKA */360#define chipcHw_REG_SOFT_RESET_LCD 0x0000000000400000ULL /* Reset LCD */361#define chipcHw_REG_SOFT_RESET_PIF 0x0000000000200000ULL /* Reset PIF */362#define chipcHw_REG_SOFT_RESET_I2CS 0x0000000000100000ULL /* Reset I2C Slave */363#define chipcHw_REG_SOFT_RESET_I2CH 0x0000000000080000ULL /* Reset I2C Host */364#define chipcHw_REG_SOFT_RESET_SDIO1 0x0000000000040000ULL /* Reset SDIO 1 */365#define chipcHw_REG_SOFT_RESET_SDIO0 0x0000000000020000ULL /* Reset SDIO 0 */366#define chipcHw_REG_SOFT_RESET_BBL 0x0000000000010000ULL /* Reset BBL */367#define chipcHw_REG_SOFT_RESET_I2S1 0x0000000000008000ULL /* Reset I2S1 */368#define chipcHw_REG_SOFT_RESET_I2S0 0x0000000000004000ULL /* Reset I2S0 */369#define chipcHw_REG_SOFT_RESET_SPIS 0x0000000000002000ULL /* Reset SPI Slave */370#define chipcHw_REG_SOFT_RESET_SPIH 0x0000000000001000ULL /* Reset SPI Host */371#define chipcHw_REG_SOFT_RESET_GPIO1 0x0000000000000800ULL /* Reset GPIO block 1 */372#define chipcHw_REG_SOFT_RESET_GPIO0 0x0000000000000400ULL /* Reset GPIO block 0 */373#define chipcHw_REG_SOFT_RESET_UART1 0x0000000000000200ULL /* Reset UART 1 */374#define chipcHw_REG_SOFT_RESET_UART0 0x0000000000000100ULL /* Reset UART 0 */375#define chipcHw_REG_SOFT_RESET_NVI 0x0000000000000080ULL /* Reset NVI */376#define chipcHw_REG_SOFT_RESET_WDOG 0x0000000000000040ULL /* Reset Watch dog */377#define chipcHw_REG_SOFT_RESET_TMR 0x0000000000000020ULL /* Reset Timer */378#define chipcHw_REG_SOFT_RESET_ETM 0x0000000000000010ULL /* Reset ETM */379#define chipcHw_REG_SOFT_RESET_ARM_HOLD 0x0000000000000008ULL /* Reset ARM and HOLD */380#define chipcHw_REG_SOFT_RESET_ARM 0x0000000000000004ULL /* Reset ARM */381#define chipcHw_REG_SOFT_RESET_CHIP_WARM 0x0000000000000002ULL /* Chip warm reset */382#define chipcHw_REG_SOFT_RESET_CHIP_SOFT 0x0000000000000001ULL /* Chip soft reset */383#define chipcHw_REG_SOFT_RESET_VDEC 0x0000100000000000ULL /* Video decoder */384#define chipcHw_REG_SOFT_RESET_GE 0x0000080000000000ULL /* Graphics engine */385#define chipcHw_REG_SOFT_RESET_OTP 0x0000040000000000ULL /* Reset OTP */386#define chipcHw_REG_SOFT_RESET_USB2 0x0000020000000000ULL /* Reset USB2 */387#define chipcHw_REG_SOFT_RESET_USB1 0x0000010000000000ULL /* Reset USB 1 */388#define chipcHw_REG_SOFT_RESET_USB 0x0000008000000000ULL /* Reset USB 1 and USB2 soft reset */389#define chipcHw_REG_SOFT_RESET_ESW 0x0000004000000000ULL /* Reset Ethernet switch */390#define chipcHw_REG_SOFT_RESET_ESWCLK 0x0000002000000000ULL /* Reset Ethernet switch clock */391#define chipcHw_REG_SOFT_RESET_DDRPHY 0x0000001000000000ULL /* Reset DDR Physical */392#define chipcHw_REG_SOFT_RESET_DDR 0x0000000800000000ULL /* Reset DDR Controller */393#define chipcHw_REG_SOFT_RESET_TSC 0x0000000400000000ULL /* Reset Touch screen */394#define chipcHw_REG_SOFT_RESET_PCM 0x0000000200000000ULL /* Reset PCM device */395#define chipcHw_REG_SOFT_RESET_APM 0x0000200100000000ULL /* Reset APM device */396397#define chipcHw_REG_SOFT_RESET_VPM_GLOBAL_UNHOLD 0x8000000000000000ULL /* Unhold Global VPM */398#define chipcHw_REG_SOFT_RESET_VPM_UNHOLD 0x4000000000000000ULL /* Unhold VPM */399#define chipcHw_REG_SOFT_RESET_ARM_UNHOLD 0x2000000000000000ULL /* Unhold ARM reset */400#define chipcHw_REG_SOFT_RESET_UNHOLD_MASK 0xF000000000000000ULL /* Mask to handle unhold request */401402/* Audio channel control defines */403#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_ALL 0x00000001 /* Enable all audio channel */404#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_A 0x00000002 /* Enable channel A */405#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_B 0x00000004 /* Enable channel B */406#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_C 0x00000008 /* Enable channel C */407#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_NTP_CLOCK 0x00000010 /* Enable NTP clock */408#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_PCM0_CLOCK 0x00000020 /* Enable PCM0 clock */409#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_PCM1_CLOCK 0x00000040 /* Enable PCM1 clock */410#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_APM_CLOCK 0x00000080 /* Enable APM clock */411412/* Misc. chip control defines */413#define chipcHw_REG_MISC_CTRL_GE_SEL 0x00040000 /* Select GE2/GE3 */414#define chipcHw_REG_MISC_CTRL_I2S1_CLOCK_ONCHIP 0x00000000 /* Use on chip clock for I2S1 */415#define chipcHw_REG_MISC_CTRL_I2S1_CLOCK_GPIO 0x00020000 /* Use external clock via GPIO pin 26 for I2S1 */416#define chipcHw_REG_MISC_CTRL_I2S0_CLOCK_ONCHIP 0x00000000 /* Use on chip clock for I2S0 */417#define chipcHw_REG_MISC_CTRL_I2S0_CLOCK_GPIO 0x00010000 /* Use external clock via GPIO pin 45 for I2S0 */418#define chipcHw_REG_MISC_CTRL_ARM_CP15_DISABLE 0x00008000 /* Disable ARM CP15 bit */419#define chipcHw_REG_MISC_CTRL_RTC_DISABLE 0x00000008 /* Disable RTC registers */420#define chipcHw_REG_MISC_CTRL_BBRAM_DISABLE 0x00000004 /* Disable Battery Backed RAM */421#define chipcHw_REG_MISC_CTRL_USB_MODE_HOST 0x00000002 /* Set USB as host */422#define chipcHw_REG_MISC_CTRL_USB_MODE_DEVICE 0xFFFFFFFD /* Set USB as device */423#define chipcHw_REG_MISC_CTRL_USB_POWERON 0xFFFFFFFE /* Power up USB */424#define chipcHw_REG_MISC_CTRL_USB_POWEROFF 0x00000001 /* Power down USB */425426/* OTP configuration defines */427#define chipcHw_REG_OTP_SECURITY_OFF 0x0000020000000000ULL /* Security support is OFF */428#define chipcHw_REG_OTP_SPU_SLOW 0x0000010000000000ULL /* Limited SPU throughput */429#define chipcHw_REG_OTP_LCD_SPEED 0x0000000600000000ULL /* Set VPM speed one */430#define chipcHw_REG_OTP_VPM_SPEED_1 0x0000000100000000ULL /* Set VPM speed one */431#define chipcHw_REG_OTP_VPM_SPEED_0 0x0000000080000000ULL /* Set VPM speed zero */432#define chipcHw_REG_OTP_AXI_SPEED 0x0000000060000000ULL /* Set maximum AXI bus speed */433#define chipcHw_REG_OTP_APM_DISABLE 0x000000001F000000ULL /* Disable APM */434#define chipcHw_REG_OTP_PIF_DISABLE 0x0000000000200000ULL /* Disable PIF */435#define chipcHw_REG_OTP_VDEC_DISABLE 0x0000000000100000ULL /* Disable Video decoder */436#define chipcHw_REG_OTP_BBL_DISABLE 0x0000000000080000ULL /* Disable RTC and BBRAM */437#define chipcHw_REG_OTP_LED_DISABLE 0x0000000000040000ULL /* Disable LED */438#define chipcHw_REG_OTP_GE_DISABLE 0x0000000000020000ULL /* Disable Graphics Engine */439#define chipcHw_REG_OTP_LCD_DISABLE 0x0000000000010000ULL /* Disable LCD */440#define chipcHw_REG_OTP_KEYPAD_DISABLE 0x0000000000008000ULL /* Disable keypad */441#define chipcHw_REG_OTP_UART_DISABLE 0x0000000000004000ULL /* Disable UART */442#define chipcHw_REG_OTP_SDIOH_DISABLE 0x0000000000003000ULL /* Disable SDIO host */443#define chipcHw_REG_OTP_HSS_DISABLE 0x0000000000000C00ULL /* Disable HSS */444#define chipcHw_REG_OTP_TSC_DISABLE 0x0000000000000200ULL /* Disable touch screen */445#define chipcHw_REG_OTP_USB_DISABLE 0x0000000000000180ULL /* Disable USB */446#define chipcHw_REG_OTP_SGMII_DISABLE 0x0000000000000060ULL /* Disable SGMII */447#define chipcHw_REG_OTP_ETH_DISABLE 0x0000000000000018ULL /* Disable gigabit ethernet */448#define chipcHw_REG_OTP_ETH_PHY_DISABLE 0x0000000000000006ULL /* Disable ethernet PHY */449#define chipcHw_REG_OTP_VPM_DISABLE 0x0000000000000001ULL /* Disable VPM */450451/* Sticky bit defines */452#define chipcHw_REG_STICKY_BOOT_DONE 0x00000001 /* Boot done */453#define chipcHw_REG_STICKY_SOFT_RESET 0x00000002 /* ARM soft reset */454#define chipcHw_REG_STICKY_GENERAL_1 0x00000004 /* General purpose bit 1 */455#define chipcHw_REG_STICKY_GENERAL_2 0x00000008 /* General purpose bit 2 */456#define chipcHw_REG_STICKY_GENERAL_3 0x00000010 /* General purpose bit 3 */457#define chipcHw_REG_STICKY_GENERAL_4 0x00000020 /* General purpose bit 4 */458#define chipcHw_REG_STICKY_GENERAL_5 0x00000040 /* General purpose bit 5 */459#define chipcHw_REG_STICKY_POR_BROM 0x00000080 /* Special sticky bit for security - set in BROM to avoid other modes being entered */460#define chipcHw_REG_STICKY_ARM_RESET 0x00000100 /* ARM reset */461#define chipcHw_REG_STICKY_CHIP_SOFT_RESET 0x00000200 /* Chip soft reset */462#define chipcHw_REG_STICKY_CHIP_WARM_RESET 0x00000400 /* Chip warm reset */463#define chipcHw_REG_STICKY_WDOG_RESET 0x00000800 /* Watchdog reset */464#define chipcHw_REG_STICKY_OTP_RESET 0x00001000 /* OTP reset */465466/* HW phase alignment defines *//* Spare1 register definitions */467#define chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE 0x80000000 /* Enable DDR phase align panic interrupt */468#define chipcHw_REG_SPARE1_VPM_PHASE_INTR_ENABLE 0x40000000 /* Enable VPM phase align panic interrupt */469#define chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE 0x00000002 /* Enable access to VPM using system BUS */470#define chipcHw_REG_SPARE1_DDR_BUS_ACCESS_ENABLE 0x00000001 /* Enable access to DDR using system BUS */471/* DDRPhaseCtrl1 register definitions */472#define chipcHw_REG_DDR_SW_PHASE_CTRL_ENABLE 0x80000000 /* Enable DDR SW phase alignment */473#define chipcHw_REG_DDR_HW_PHASE_CTRL_ENABLE 0x40000000 /* Enable DDR HW phase alignment */474#define chipcHw_REG_DDR_PHASE_VALUE_GE_MASK 0x0000007F /* DDR lower threshold for phase alignment */475#define chipcHw_REG_DDR_PHASE_VALUE_GE_SHIFT 23476#define chipcHw_REG_DDR_PHASE_VALUE_LE_MASK 0x0000007F /* DDR upper threshold for phase alignment */477#define chipcHw_REG_DDR_PHASE_VALUE_LE_SHIFT 16478#define chipcHw_REG_DDR_PHASE_ALIGN_WAIT_CYCLE_MASK 0x0000FFFF /* BUS Cycle to wait to run next DDR phase alignment */479#define chipcHw_REG_DDR_PHASE_ALIGN_WAIT_CYCLE_SHIFT 0480/* VPMPhaseCtrl1 register definitions */481#define chipcHw_REG_VPM_SW_PHASE_CTRL_ENABLE 0x80000000 /* Enable VPM SW phase alignment */482#define chipcHw_REG_VPM_HW_PHASE_CTRL_ENABLE 0x40000000 /* Enable VPM HW phase alignment */483#define chipcHw_REG_VPM_PHASE_VALUE_GE_MASK 0x0000007F /* VPM lower threshold for phase alignment */484#define chipcHw_REG_VPM_PHASE_VALUE_GE_SHIFT 23485#define chipcHw_REG_VPM_PHASE_VALUE_LE_MASK 0x0000007F /* VPM upper threshold for phase alignment */486#define chipcHw_REG_VPM_PHASE_VALUE_LE_SHIFT 16487#define chipcHw_REG_VPM_PHASE_ALIGN_WAIT_CYCLE_MASK 0x0000FFFF /* BUS Cycle to wait to complete the VPM phase alignment */488#define chipcHw_REG_VPM_PHASE_ALIGN_WAIT_CYCLE_SHIFT 0489/* PhaseAlignStatus register definitions */490#define chipcHw_REG_DDR_TIMEOUT_INTR_STATUS 0x80000000 /* DDR time out interrupt status */491#define chipcHw_REG_DDR_PHASE_STATUS_MASK 0x0000007F /* DDR phase status value */492#define chipcHw_REG_DDR_PHASE_STATUS_SHIFT 24493#define chipcHw_REG_DDR_PHASE_ALIGNED 0x00800000 /* DDR Phase aligned status */494#define chipcHw_REG_DDR_LOAD 0x00400000 /* Load DDR phase status */495#define chipcHw_REG_DDR_PHASE_CTRL_MASK 0x0000003F /* DDR phase control value */496#define chipcHw_REG_DDR_PHASE_CTRL_SHIFT 16497#define chipcHw_REG_VPM_TIMEOUT_INTR_STATUS 0x80000000 /* VPM time out interrupt status */498#define chipcHw_REG_VPM_PHASE_STATUS_MASK 0x0000007F /* VPM phase status value */499#define chipcHw_REG_VPM_PHASE_STATUS_SHIFT 8500#define chipcHw_REG_VPM_PHASE_ALIGNED 0x00000080 /* VPM Phase aligned status */501#define chipcHw_REG_VPM_LOAD 0x00000040 /* Load VPM phase status */502#define chipcHw_REG_VPM_PHASE_CTRL_MASK 0x0000003F /* VPM phase control value */503#define chipcHw_REG_VPM_PHASE_CTRL_SHIFT 0504/* DDRPhaseCtrl2 register definitions */505#define chipcHw_REG_DDR_INTR_SERVICED 0x02000000 /* Acknowledge that interrupt was serviced */506#define chipcHw_REG_DDR_TIMEOUT_INTR_ENABLE 0x01000000 /* Enable time out interrupt */507#define chipcHw_REG_DDR_LOAD_COUNT_PHASE_CTRL_MASK 0x0000000F /* Wait before toggling load_ch */508#define chipcHw_REG_DDR_LOAD_COUNT_PHASE_CTRL_SHIFT 20509#define chipcHw_REG_DDR_TOTAL_LOAD_COUNT_CTRL_MASK 0x0000000F /* Total wait to settle ph_ctrl and load_ch */510#define chipcHw_REG_DDR_TOTAL_LOAD_COUNT_CTRL_SHIFT 16511#define chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_MASK 0x0000FFFF /* Time out value for DDR HW phase alignment */512#define chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_SHIFT 0513/* VPMPhaseCtrl2 register definitions */514#define chipcHw_REG_VPM_INTR_SELECT_MASK 0x00000003 /* Interrupt select */515#define chipcHw_REG_VPM_INTR_SELECT_SHIFT 26516#define chipcHw_REG_VPM_INTR_DISABLE 0x00000000517#define chipcHw_REG_VPM_INTR_FAST (0x1 << chipcHw_REG_VPM_INTR_SELECT_SHIFT)518#define chipcHw_REG_VPM_INTR_MEDIUM (0x2 << chipcHw_REG_VPM_INTR_SELECT_SHIFT)519#define chipcHw_REG_VPM_INTR_SLOW (0x3 << chipcHw_REG_VPM_INTR_SELECT_SHIFT)520#define chipcHw_REG_VPM_INTR_SERVICED 0x02000000 /* Acknowledge that interrupt was serviced */521#define chipcHw_REG_VPM_TIMEOUT_INTR_ENABLE 0x01000000 /* Enable time out interrupt */522#define chipcHw_REG_VPM_LOAD_COUNT_PHASE_CTRL_MASK 0x0000000F /* Wait before toggling load_ch */523#define chipcHw_REG_VPM_LOAD_COUNT_PHASE_CTRL_SHIFT 20524#define chipcHw_REG_VPM_TOTAL_LOAD_COUNT_CTRL_MASK 0x0000000F /* Total wait cycle to settle ph_ctrl and load_ch */525#define chipcHw_REG_VPM_TOTAL_LOAD_COUNT_CTRL_SHIFT 16526#define chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_MASK 0x0000FFFF /* Time out value for VPM HW phase alignment */527#define chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_SHIFT 0528529#endif /* CHIPCHW_REG_H */530531532