Path: blob/master/arch/arm/mach-bcmring/include/mach/csp/secHw_def.h
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/*****************************************************************************1* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.2*3* Unless you and Broadcom execute a separate written software license4* agreement governing use of this software, this software is licensed to you5* under the terms of the GNU General Public License version 2, available at6* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").7*8* Notwithstanding the above, under no circumstances may you combine this9* software in any way with any other Broadcom software provided under a10* license other than the GPL, without Broadcom's express prior written11* consent.12*****************************************************************************/1314/****************************************************************************/15/**16* @file secHw_def.h17*18* @brief Definitions for configuring/testing secure blocks19*20* @note21* None22*/23/****************************************************************************/2425#ifndef SECHW_DEF_H26#define SECHW_DEF_H2728#include <mach/csp/mm_io.h>2930/* Bit mask for various secure device */31#define secHw_BLK_MASK_CHIP_CONTROL 0x0000000132#define secHw_BLK_MASK_KEY_SCAN 0x0000000233#define secHw_BLK_MASK_TOUCH_SCREEN 0x0000000434#define secHw_BLK_MASK_UART0 0x0000000835#define secHw_BLK_MASK_UART1 0x0000001036#define secHw_BLK_MASK_WATCHDOG 0x0000002037#define secHw_BLK_MASK_SPUM 0x0000004038#define secHw_BLK_MASK_DDR2 0x0000008039#define secHw_BLK_MASK_EXT_MEM 0x0000010040#define secHw_BLK_MASK_ESW 0x0000020041#define secHw_BLK_MASK_SPU 0x0001000042#define secHw_BLK_MASK_PKA 0x0002000043#define secHw_BLK_MASK_RNG 0x0004000044#define secHw_BLK_MASK_RTC 0x0008000045#define secHw_BLK_MASK_OTP 0x0010000046#define secHw_BLK_MASK_BOOT 0x0020000047#define secHw_BLK_MASK_MPU 0x0040000048#define secHw_BLK_MASK_TZCTRL 0x0080000049#define secHw_BLK_MASK_INTR 0x010000005051/* Trustzone register set */52typedef struct {53volatile uint32_t status; /* read only - reflects status of writes of 2 write registers */54volatile uint32_t setUnsecure; /* write only. reads back as 0 */55volatile uint32_t setSecure; /* write only. reads back as 0 */56} secHw_TZREG_t;5758/* There are 2 register sets. The first is for the lower 16 bits, the 2nd */59/* is for the higher 16 bits. */6061typedef enum {62secHw_IDX_LS = 0,63secHw_IDX_MS = 1,64secHw_IDX_NUM65} secHw_IDX_e;6667typedef struct {68volatile secHw_TZREG_t reg[secHw_IDX_NUM];69} secHw_REGS_t;7071/****************************************************************************/72/**73* @brief Configures a device as a secure device74*75*/76/****************************************************************************/77static inline void secHw_setSecure(uint32_t mask /* mask of type secHw_BLK_MASK_XXXXXX */78);7980/****************************************************************************/81/**82* @brief Configures a device as a non-secure device83*84*/85/****************************************************************************/86static inline void secHw_setUnsecure(uint32_t mask /* mask of type secHw_BLK_MASK_XXXXXX */87);8889/****************************************************************************/90/**91* @brief Get the trustzone status for all components. 1 = non-secure, 0 = secure92*93*/94/****************************************************************************/95static inline uint32_t secHw_getStatus(void);9697#include <mach/csp/secHw_inline.h>9899#endif /* SECHW_DEF_H */100101102