CoCalc -- da850.c

GitHub Repository: awilliam/linux-vfio
Path: blob/master/arch/arm/mach-davinci/da850.c
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/*
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 * TI DA850/OMAP-L138 chip specific setup
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 *
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 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
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 *
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 * Derived from: arch/arm/mach-davinci/da830.c
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 * Original Copyrights follow:
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 *
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 * 2009 (c) MontaVista Software, Inc. This file is licensed under
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 * the terms of the GNU General Public License version 2. This program
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 * is licensed "as is" without any warranty of any kind, whether express
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 * or implied.
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 */
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#include <linux/init.h>
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#include <linux/clk.h>
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#include <linux/platform_device.h>
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#include <linux/cpufreq.h>
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#include <linux/regulator/consumer.h>
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#include <asm/mach/map.h>
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#include <mach/psc.h>
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#include <mach/irqs.h>
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#include <mach/cputype.h>
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#include <mach/common.h>
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#include <mach/time.h>
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#include <mach/da8xx.h>
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#include <mach/cpufreq.h>
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#include <mach/pm.h>
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#include <mach/gpio.h>
31

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#include "clock.h"
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#include "mux.h"
34

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/* SoC specific clock flags */
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#define DA850_CLK_ASYNC3	BIT(16)
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#define DA850_PLL1_BASE		0x01e1a000
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#define DA850_TIMER64P2_BASE	0x01f0c000
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#define DA850_TIMER64P3_BASE	0x01f0d000
41

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#define DA850_REF_FREQ		24000000
43

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#define CFGCHIP3_ASYNC3_CLKSRC	BIT(4)
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#define CFGCHIP3_PLL1_MASTER_LOCK	BIT(5)
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#define CFGCHIP0_PLL_MASTER_LOCK	BIT(4)
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static int da850_set_armrate(struct clk *clk, unsigned long rate);
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static int da850_round_armrate(struct clk *clk, unsigned long rate);
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static int da850_set_pll0rate(struct clk *clk, unsigned long armrate);
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static struct pll_data pll0_data = {
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	.num		= 1,
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	.phys_base	= DA8XX_PLL0_BASE,
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	.flags		= PLL_HAS_PREDIV | PLL_HAS_POSTDIV,
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};
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static struct clk ref_clk = {
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	.name		= "ref_clk",
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	.rate		= DA850_REF_FREQ,
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};
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static struct clk pll0_clk = {
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	.name		= "pll0",
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	.parent		= &ref_clk,
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	.pll_data	= &pll0_data,
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	.flags		= CLK_PLL,
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	.set_rate	= da850_set_pll0rate,
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};
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static struct clk pll0_aux_clk = {
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	.name		= "pll0_aux_clk",
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	.parent		= &pll0_clk,
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	.flags		= CLK_PLL | PRE_PLL,
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};
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static struct clk pll0_sysclk2 = {
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	.name		= "pll0_sysclk2",
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	.parent		= &pll0_clk,
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	.flags		= CLK_PLL,
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	.div_reg	= PLLDIV2,
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};
83

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static struct clk pll0_sysclk3 = {
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	.name		= "pll0_sysclk3",
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	.parent		= &pll0_clk,
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	.flags		= CLK_PLL,
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	.div_reg	= PLLDIV3,
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	.set_rate	= davinci_set_sysclk_rate,
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	.maxrate	= 100000000,
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};
92

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static struct clk pll0_sysclk4 = {
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	.name		= "pll0_sysclk4",
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	.parent		= &pll0_clk,
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	.flags		= CLK_PLL,
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	.div_reg	= PLLDIV4,
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};
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static struct clk pll0_sysclk5 = {
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	.name		= "pll0_sysclk5",
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	.parent		= &pll0_clk,
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	.flags		= CLK_PLL,
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	.div_reg	= PLLDIV5,
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};
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static struct clk pll0_sysclk6 = {
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	.name		= "pll0_sysclk6",
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	.parent		= &pll0_clk,
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	.flags		= CLK_PLL,
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	.div_reg	= PLLDIV6,
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};
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static struct clk pll0_sysclk7 = {
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	.name		= "pll0_sysclk7",
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	.parent		= &pll0_clk,
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	.flags		= CLK_PLL,
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	.div_reg	= PLLDIV7,
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};
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static struct pll_data pll1_data = {
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	.num		= 2,
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	.phys_base	= DA850_PLL1_BASE,
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	.flags		= PLL_HAS_POSTDIV,
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};
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static struct clk pll1_clk = {
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	.name		= "pll1",
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	.parent		= &ref_clk,
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	.pll_data	= &pll1_data,
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	.flags		= CLK_PLL,
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};
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static struct clk pll1_aux_clk = {
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	.name		= "pll1_aux_clk",
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	.parent		= &pll1_clk,
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	.flags		= CLK_PLL | PRE_PLL,
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};
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static struct clk pll1_sysclk2 = {
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	.name		= "pll1_sysclk2",
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	.parent		= &pll1_clk,
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	.flags		= CLK_PLL,
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	.div_reg	= PLLDIV2,
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};
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static struct clk pll1_sysclk3 = {
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	.name		= "pll1_sysclk3",
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	.parent		= &pll1_clk,
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	.flags		= CLK_PLL,
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	.div_reg	= PLLDIV3,
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};
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static struct clk pll1_sysclk4 = {
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	.name		= "pll1_sysclk4",
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	.parent		= &pll1_clk,
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	.flags		= CLK_PLL,
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	.div_reg	= PLLDIV4,
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};
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static struct clk pll1_sysclk5 = {
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	.name		= "pll1_sysclk5",
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	.parent		= &pll1_clk,
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	.flags		= CLK_PLL,
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	.div_reg	= PLLDIV5,
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};
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static struct clk pll1_sysclk6 = {
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	.name		= "pll0_sysclk6",
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	.parent		= &pll0_clk,
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	.flags		= CLK_PLL,
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	.div_reg	= PLLDIV6,
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};
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static struct clk pll1_sysclk7 = {
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	.name		= "pll1_sysclk7",
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	.parent		= &pll1_clk,
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	.flags		= CLK_PLL,
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	.div_reg	= PLLDIV7,
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};
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static struct clk i2c0_clk = {
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	.name		= "i2c0",
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	.parent		= &pll0_aux_clk,
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};
186

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static struct clk timerp64_0_clk = {
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	.name		= "timer0",
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	.parent		= &pll0_aux_clk,
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};
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static struct clk timerp64_1_clk = {
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	.name		= "timer1",
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	.parent		= &pll0_aux_clk,
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};
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static struct clk arm_rom_clk = {
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	.name		= "arm_rom",
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	.parent		= &pll0_sysclk2,
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	.lpsc		= DA8XX_LPSC0_ARM_RAM_ROM,
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	.flags		= ALWAYS_ENABLED,
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};
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static struct clk tpcc0_clk = {
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	.name		= "tpcc0",
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	.parent		= &pll0_sysclk2,
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	.lpsc		= DA8XX_LPSC0_TPCC,
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	.flags		= ALWAYS_ENABLED | CLK_PSC,
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};
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static struct clk tptc0_clk = {
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	.name		= "tptc0",
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	.parent		= &pll0_sysclk2,
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	.lpsc		= DA8XX_LPSC0_TPTC0,
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	.flags		= ALWAYS_ENABLED,
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};
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static struct clk tptc1_clk = {
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	.name		= "tptc1",
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	.parent		= &pll0_sysclk2,
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	.lpsc		= DA8XX_LPSC0_TPTC1,
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	.flags		= ALWAYS_ENABLED,
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};
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static struct clk tpcc1_clk = {
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	.name		= "tpcc1",
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	.parent		= &pll0_sysclk2,
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	.lpsc		= DA850_LPSC1_TPCC1,
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	.gpsc		= 1,
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	.flags		= CLK_PSC | ALWAYS_ENABLED,
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};
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static struct clk tptc2_clk = {
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	.name		= "tptc2",
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	.parent		= &pll0_sysclk2,
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	.lpsc		= DA850_LPSC1_TPTC2,
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	.gpsc		= 1,
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	.flags		= ALWAYS_ENABLED,
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};
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static struct clk uart0_clk = {
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	.name		= "uart0",
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	.parent		= &pll0_sysclk2,
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	.lpsc		= DA8XX_LPSC0_UART0,
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};
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static struct clk uart1_clk = {
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	.name		= "uart1",
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	.parent		= &pll0_sysclk2,
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	.lpsc		= DA8XX_LPSC1_UART1,
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	.gpsc		= 1,
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	.flags		= DA850_CLK_ASYNC3,
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};
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static struct clk uart2_clk = {
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	.name		= "uart2",
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	.parent		= &pll0_sysclk2,
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	.lpsc		= DA8XX_LPSC1_UART2,
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	.gpsc		= 1,
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	.flags		= DA850_CLK_ASYNC3,
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};
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static struct clk aintc_clk = {
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	.name		= "aintc",
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	.parent		= &pll0_sysclk4,
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	.lpsc		= DA8XX_LPSC0_AINTC,
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	.flags		= ALWAYS_ENABLED,
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};
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static struct clk gpio_clk = {
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	.name		= "gpio",
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	.parent		= &pll0_sysclk4,
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	.lpsc		= DA8XX_LPSC1_GPIO,
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	.gpsc		= 1,
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};
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static struct clk i2c1_clk = {
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	.name		= "i2c1",
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	.parent		= &pll0_sysclk4,
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	.lpsc		= DA8XX_LPSC1_I2C,
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	.gpsc		= 1,
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};
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static struct clk emif3_clk = {
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	.name		= "emif3",
286
	.parent		= &pll0_sysclk5,
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	.lpsc		= DA8XX_LPSC1_EMIF3C,
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	.gpsc		= 1,
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	.flags		= ALWAYS_ENABLED,
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};
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static struct clk arm_clk = {
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	.name		= "arm",
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	.parent		= &pll0_sysclk6,
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	.lpsc		= DA8XX_LPSC0_ARM,
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	.flags		= ALWAYS_ENABLED,
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	.set_rate	= da850_set_armrate,
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	.round_rate	= da850_round_armrate,
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};
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static struct clk rmii_clk = {
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	.name		= "rmii",
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	.parent		= &pll0_sysclk7,
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};
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static struct clk emac_clk = {
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	.name		= "emac",
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	.parent		= &pll0_sysclk4,
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	.lpsc		= DA8XX_LPSC1_CPGMAC,
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	.gpsc		= 1,
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};
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static struct clk mcasp_clk = {
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	.name		= "mcasp",
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	.parent		= &pll0_sysclk2,
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	.lpsc		= DA8XX_LPSC1_McASP0,
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	.gpsc		= 1,
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	.flags		= DA850_CLK_ASYNC3,
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};
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static struct clk lcdc_clk = {
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	.name		= "lcdc",
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	.parent		= &pll0_sysclk2,
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	.lpsc		= DA8XX_LPSC1_LCDC,
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	.gpsc		= 1,
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};
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static struct clk mmcsd0_clk = {
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	.name		= "mmcsd0",
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	.parent		= &pll0_sysclk2,
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	.lpsc		= DA8XX_LPSC0_MMC_SD,
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};
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static struct clk mmcsd1_clk = {
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	.name		= "mmcsd1",
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	.parent		= &pll0_sysclk2,
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	.lpsc		= DA850_LPSC1_MMC_SD1,
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	.gpsc		= 1,
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};
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static struct clk aemif_clk = {
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	.name		= "aemif",
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	.parent		= &pll0_sysclk3,
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	.lpsc		= DA8XX_LPSC0_EMIF25,
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	.flags		= ALWAYS_ENABLED,
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};
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static struct clk usb11_clk = {
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	.name		= "usb11",
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	.parent		= &pll0_sysclk4,
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	.lpsc		= DA8XX_LPSC1_USB11,
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	.gpsc		= 1,
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};
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static struct clk usb20_clk = {
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	.name		= "usb20",
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	.parent		= &pll0_sysclk2,
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	.lpsc		= DA8XX_LPSC1_USB20,
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	.gpsc		= 1,
360
};
361

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static struct clk spi0_clk = {
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	.name		= "spi0",
364
	.parent		= &pll0_sysclk2,
365
	.lpsc		= DA8XX_LPSC0_SPI0,
366
};
367

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static struct clk spi1_clk = {
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	.name		= "spi1",
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	.parent		= &pll0_sysclk2,
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	.lpsc		= DA8XX_LPSC1_SPI1,
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	.gpsc		= 1,
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	.flags		= DA850_CLK_ASYNC3,
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};
375

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static struct clk_lookup da850_clks[] = {
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	CLK(NULL,		"ref",		&ref_clk),
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	CLK(NULL,		"pll0",		&pll0_clk),
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	CLK(NULL,		"pll0_aux",	&pll0_aux_clk),
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	CLK(NULL,		"pll0_sysclk2",	&pll0_sysclk2),
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	CLK(NULL,		"pll0_sysclk3",	&pll0_sysclk3),
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	CLK(NULL,		"pll0_sysclk4",	&pll0_sysclk4),
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	CLK(NULL,		"pll0_sysclk5",	&pll0_sysclk5),
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	CLK(NULL,		"pll0_sysclk6",	&pll0_sysclk6),
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	CLK(NULL,		"pll0_sysclk7",	&pll0_sysclk7),
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	CLK(NULL,		"pll1",		&pll1_clk),
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	CLK(NULL,		"pll1_aux",	&pll1_aux_clk),
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	CLK(NULL,		"pll1_sysclk2",	&pll1_sysclk2),
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	CLK(NULL,		"pll1_sysclk3",	&pll1_sysclk3),
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	CLK(NULL,		"pll1_sysclk4",	&pll1_sysclk4),
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	CLK(NULL,		"pll1_sysclk5",	&pll1_sysclk5),
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	CLK(NULL,		"pll1_sysclk6",	&pll1_sysclk6),
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	CLK(NULL,		"pll1_sysclk7",	&pll1_sysclk7),
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	CLK("i2c_davinci.1",	NULL,		&i2c0_clk),
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	CLK(NULL,		"timer0",	&timerp64_0_clk),
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	CLK("watchdog",		NULL,		&timerp64_1_clk),
397
	CLK(NULL,		"arm_rom",	&arm_rom_clk),
398
	CLK(NULL,		"tpcc0",	&tpcc0_clk),
399
	CLK(NULL,		"tptc0",	&tptc0_clk),
400
	CLK(NULL,		"tptc1",	&tptc1_clk),
401
	CLK(NULL,		"tpcc1",	&tpcc1_clk),
402
	CLK(NULL,		"tptc2",	&tptc2_clk),
403
	CLK(NULL,		"uart0",	&uart0_clk),
404
	CLK(NULL,		"uart1",	&uart1_clk),
405
	CLK(NULL,		"uart2",	&uart2_clk),
406
	CLK(NULL,		"aintc",	&aintc_clk),
407
	CLK(NULL,		"gpio",		&gpio_clk),
408
	CLK("i2c_davinci.2",	NULL,		&i2c1_clk),
409
	CLK(NULL,		"emif3",	&emif3_clk),
410
	CLK(NULL,		"arm",		&arm_clk),
411
	CLK(NULL,		"rmii",		&rmii_clk),
412
	CLK("davinci_emac.1",	NULL,		&emac_clk),
413
	CLK("davinci-mcasp.0",	NULL,		&mcasp_clk),
414
	CLK("da8xx_lcdc.0",	NULL,		&lcdc_clk),
415
	CLK("davinci_mmc.0",	NULL,		&mmcsd0_clk),
416
	CLK("davinci_mmc.1",	NULL,		&mmcsd1_clk),
417
	CLK(NULL,		"aemif",	&aemif_clk),
418
	CLK(NULL,		"usb11",	&usb11_clk),
419
	CLK(NULL,		"usb20",	&usb20_clk),
420
	CLK("spi_davinci.0",	NULL,		&spi0_clk),
421
	CLK("spi_davinci.1",	NULL,		&spi1_clk),
422
	CLK(NULL,		NULL,		NULL),
423
};
424

425
/*
426
 * Device specific mux setup
427
 *
428
 *		soc	description	mux	mode	mode	mux	dbg
429
 *					reg	offset	mask	mode
430
 */
431
static const struct mux_config da850_pins[] = {
432
#ifdef CONFIG_DAVINCI_MUX
433
	/* UART0 function */
434
	MUX_CFG(DA850, NUART0_CTS,	3,	24,	15,	2,	false)
435
	MUX_CFG(DA850, NUART0_RTS,	3,	28,	15,	2,	false)
436
	MUX_CFG(DA850, UART0_RXD,	3,	16,	15,	2,	false)
437
	MUX_CFG(DA850, UART0_TXD,	3,	20,	15,	2,	false)
438
	/* UART1 function */
439
	MUX_CFG(DA850, UART1_RXD,	4,	24,	15,	2,	false)
440
	MUX_CFG(DA850, UART1_TXD,	4,	28,	15,	2,	false)
441
	/* UART2 function */
442
	MUX_CFG(DA850, UART2_RXD,	4,	16,	15,	2,	false)
443
	MUX_CFG(DA850, UART2_TXD,	4,	20,	15,	2,	false)
444
	/* I2C1 function */
445
	MUX_CFG(DA850, I2C1_SCL,	4,	16,	15,	4,	false)
446
	MUX_CFG(DA850, I2C1_SDA,	4,	20,	15,	4,	false)
447
	/* I2C0 function */
448
	MUX_CFG(DA850, I2C0_SDA,	4,	12,	15,	2,	false)
449
	MUX_CFG(DA850, I2C0_SCL,	4,	8,	15,	2,	false)
450
	/* EMAC function */
451
	MUX_CFG(DA850, MII_TXEN,	2,	4,	15,	8,	false)
452
	MUX_CFG(DA850, MII_TXCLK,	2,	8,	15,	8,	false)
453
	MUX_CFG(DA850, MII_COL,		2,	12,	15,	8,	false)
454
	MUX_CFG(DA850, MII_TXD_3,	2,	16,	15,	8,	false)
455
	MUX_CFG(DA850, MII_TXD_2,	2,	20,	15,	8,	false)
456
	MUX_CFG(DA850, MII_TXD_1,	2,	24,	15,	8,	false)
457
	MUX_CFG(DA850, MII_TXD_0,	2,	28,	15,	8,	false)
458
	MUX_CFG(DA850, MII_RXCLK,	3,	0,	15,	8,	false)
459
	MUX_CFG(DA850, MII_RXDV,	3,	4,	15,	8,	false)
460
	MUX_CFG(DA850, MII_RXER,	3,	8,	15,	8,	false)
461
	MUX_CFG(DA850, MII_CRS,		3,	12,	15,	8,	false)
462
	MUX_CFG(DA850, MII_RXD_3,	3,	16,	15,	8,	false)
463
	MUX_CFG(DA850, MII_RXD_2,	3,	20,	15,	8,	false)
464
	MUX_CFG(DA850, MII_RXD_1,	3,	24,	15,	8,	false)
465
	MUX_CFG(DA850, MII_RXD_0,	3,	28,	15,	8,	false)
466
	MUX_CFG(DA850, MDIO_CLK,	4,	0,	15,	8,	false)
467
	MUX_CFG(DA850, MDIO_D,		4,	4,	15,	8,	false)
468
	MUX_CFG(DA850, RMII_TXD_0,	14,	12,	15,	8,	false)
469
	MUX_CFG(DA850, RMII_TXD_1,	14,	8,	15,	8,	false)
470
	MUX_CFG(DA850, RMII_TXEN,	14,	16,	15,	8,	false)
471
	MUX_CFG(DA850, RMII_CRS_DV,	15,	4,	15,	8,	false)
472
	MUX_CFG(DA850, RMII_RXD_0,	14,	24,	15,	8,	false)
473
	MUX_CFG(DA850, RMII_RXD_1,	14,	20,	15,	8,	false)
474
	MUX_CFG(DA850, RMII_RXER,	14,	28,	15,	8,	false)
475
	MUX_CFG(DA850, RMII_MHZ_50_CLK,	15,	0,	15,	0,	false)
476
	/* McASP function */
477
	MUX_CFG(DA850,	ACLKR,		0,	0,	15,	1,	false)
478
	MUX_CFG(DA850,	ACLKX,		0,	4,	15,	1,	false)
479
	MUX_CFG(DA850,	AFSR,		0,	8,	15,	1,	false)
480
	MUX_CFG(DA850,	AFSX,		0,	12,	15,	1,	false)
481
	MUX_CFG(DA850,	AHCLKR,		0,	16,	15,	1,	false)
482
	MUX_CFG(DA850,	AHCLKX,		0,	20,	15,	1,	false)
483
	MUX_CFG(DA850,	AMUTE,		0,	24,	15,	1,	false)
484
	MUX_CFG(DA850,	AXR_15,		1,	0,	15,	1,	false)
485
	MUX_CFG(DA850,	AXR_14,		1,	4,	15,	1,	false)
486
	MUX_CFG(DA850,	AXR_13,		1,	8,	15,	1,	false)
487
	MUX_CFG(DA850,	AXR_12,		1,	12,	15,	1,	false)
488
	MUX_CFG(DA850,	AXR_11,		1,	16,	15,	1,	false)
489
	MUX_CFG(DA850,	AXR_10,		1,	20,	15,	1,	false)
490
	MUX_CFG(DA850,	AXR_9,		1,	24,	15,	1,	false)
491
	MUX_CFG(DA850,	AXR_8,		1,	28,	15,	1,	false)
492
	MUX_CFG(DA850,	AXR_7,		2,	0,	15,	1,	false)
493
	MUX_CFG(DA850,	AXR_6,		2,	4,	15,	1,	false)
494
	MUX_CFG(DA850,	AXR_5,		2,	8,	15,	1,	false)
495
	MUX_CFG(DA850,	AXR_4,		2,	12,	15,	1,	false)
496
	MUX_CFG(DA850,	AXR_3,		2,	16,	15,	1,	false)
497
	MUX_CFG(DA850,	AXR_2,		2,	20,	15,	1,	false)
498
	MUX_CFG(DA850,	AXR_1,		2,	24,	15,	1,	false)
499
	MUX_CFG(DA850,	AXR_0,		2,	28,	15,	1,	false)
500
	/* LCD function */
501
	MUX_CFG(DA850, LCD_D_7,		16,	8,	15,	2,	false)
502
	MUX_CFG(DA850, LCD_D_6,		16,	12,	15,	2,	false)
503
	MUX_CFG(DA850, LCD_D_5,		16,	16,	15,	2,	false)
504
	MUX_CFG(DA850, LCD_D_4,		16,	20,	15,	2,	false)
505
	MUX_CFG(DA850, LCD_D_3,		16,	24,	15,	2,	false)
506
	MUX_CFG(DA850, LCD_D_2,		16,	28,	15,	2,	false)
507
	MUX_CFG(DA850, LCD_D_1,		17,	0,	15,	2,	false)
508
	MUX_CFG(DA850, LCD_D_0,		17,	4,	15,	2,	false)
509
	MUX_CFG(DA850, LCD_D_15,	17,	8,	15,	2,	false)
510
	MUX_CFG(DA850, LCD_D_14,	17,	12,	15,	2,	false)
511
	MUX_CFG(DA850, LCD_D_13,	17,	16,	15,	2,	false)
512
	MUX_CFG(DA850, LCD_D_12,	17,	20,	15,	2,	false)
513
	MUX_CFG(DA850, LCD_D_11,	17,	24,	15,	2,	false)
514
	MUX_CFG(DA850, LCD_D_10,	17,	28,	15,	2,	false)
515
	MUX_CFG(DA850, LCD_D_9,		18,	0,	15,	2,	false)
516
	MUX_CFG(DA850, LCD_D_8,		18,	4,	15,	2,	false)
517
	MUX_CFG(DA850, LCD_PCLK,	18,	24,	15,	2,	false)
518
	MUX_CFG(DA850, LCD_HSYNC,	19,	0,	15,	2,	false)
519
	MUX_CFG(DA850, LCD_VSYNC,	19,	4,	15,	2,	false)
520
	MUX_CFG(DA850, NLCD_AC_ENB_CS,	19,	24,	15,	2,	false)
521
	/* MMC/SD0 function */
522
	MUX_CFG(DA850, MMCSD0_DAT_0,	10,	8,	15,	2,	false)
523
	MUX_CFG(DA850, MMCSD0_DAT_1,	10,	12,	15,	2,	false)
524
	MUX_CFG(DA850, MMCSD0_DAT_2,	10,	16,	15,	2,	false)
525
	MUX_CFG(DA850, MMCSD0_DAT_3,	10,	20,	15,	2,	false)
526
	MUX_CFG(DA850, MMCSD0_CLK,	10,	0,	15,	2,	false)
527
	MUX_CFG(DA850, MMCSD0_CMD,	10,	4,	15,	2,	false)
528
	/* EMIF2.5/EMIFA function */
529
	MUX_CFG(DA850, EMA_D_7,		9,	0,	15,	1,	false)
530
	MUX_CFG(DA850, EMA_D_6,		9,	4,	15,	1,	false)
531
	MUX_CFG(DA850, EMA_D_5,		9,	8,	15,	1,	false)
532
	MUX_CFG(DA850, EMA_D_4,		9,	12,	15,	1,	false)
533
	MUX_CFG(DA850, EMA_D_3,		9,	16,	15,	1,	false)
534
	MUX_CFG(DA850, EMA_D_2,		9,	20,	15,	1,	false)
535
	MUX_CFG(DA850, EMA_D_1,		9,	24,	15,	1,	false)
536
	MUX_CFG(DA850, EMA_D_0,		9,	28,	15,	1,	false)
537
	MUX_CFG(DA850, EMA_A_1,		12,	24,	15,	1,	false)
538
	MUX_CFG(DA850, EMA_A_2,		12,	20,	15,	1,	false)
539
	MUX_CFG(DA850, NEMA_CS_3,	7,	4,	15,	1,	false)
540
	MUX_CFG(DA850, NEMA_CS_4,	7,	8,	15,	1,	false)
541
	MUX_CFG(DA850, NEMA_WE,		7,	16,	15,	1,	false)
542
	MUX_CFG(DA850, NEMA_OE,		7,	20,	15,	1,	false)
543
	MUX_CFG(DA850, EMA_A_0,		12,	28,	15,	1,	false)
544
	MUX_CFG(DA850, EMA_A_3,		12,	16,	15,	1,	false)
545
	MUX_CFG(DA850, EMA_A_4,		12,	12,	15,	1,	false)
546
	MUX_CFG(DA850, EMA_A_5,		12,	8,	15,	1,	false)
547
	MUX_CFG(DA850, EMA_A_6,		12,	4,	15,	1,	false)
548
	MUX_CFG(DA850, EMA_A_7,		12,	0,	15,	1,	false)
549
	MUX_CFG(DA850, EMA_A_8,		11,	28,	15,	1,	false)
550
	MUX_CFG(DA850, EMA_A_9,		11,	24,	15,	1,	false)
551
	MUX_CFG(DA850, EMA_A_10,	11,	20,	15,	1,	false)
552
	MUX_CFG(DA850, EMA_A_11,	11,	16,	15,	1,	false)
553
	MUX_CFG(DA850, EMA_A_12,	11,	12,	15,	1,	false)
554
	MUX_CFG(DA850, EMA_A_13,	11,	8,	15,	1,	false)
555
	MUX_CFG(DA850, EMA_A_14,	11,	4,	15,	1,	false)
556
	MUX_CFG(DA850, EMA_A_15,	11,	0,	15,	1,	false)
557
	MUX_CFG(DA850, EMA_A_16,	10,	28,	15,	1,	false)
558
	MUX_CFG(DA850, EMA_A_17,	10,	24,	15,	1,	false)
559
	MUX_CFG(DA850, EMA_A_18,	10,	20,	15,	1,	false)
560
	MUX_CFG(DA850, EMA_A_19,	10,	16,	15,	1,	false)
561
	MUX_CFG(DA850, EMA_A_20,	10,	12,	15,	1,	false)
562
	MUX_CFG(DA850, EMA_A_21,	10,	8,	15,	1,	false)
563
	MUX_CFG(DA850, EMA_A_22,	10,	4,	15,	1,	false)
564
	MUX_CFG(DA850, EMA_A_23,	10,	0,	15,	1,	false)
565
	MUX_CFG(DA850, EMA_D_8,		8,	28,	15,	1,	false)
566
	MUX_CFG(DA850, EMA_D_9,		8,	24,	15,	1,	false)
567
	MUX_CFG(DA850, EMA_D_10,	8,	20,	15,	1,	false)
568
	MUX_CFG(DA850, EMA_D_11,	8,	16,	15,	1,	false)
569
	MUX_CFG(DA850, EMA_D_12,	8,	12,	15,	1,	false)
570
	MUX_CFG(DA850, EMA_D_13,	8,	8,	15,	1,	false)
571
	MUX_CFG(DA850, EMA_D_14,	8,	4,	15,	1,	false)
572
	MUX_CFG(DA850, EMA_D_15,	8,	0,	15,	1,	false)
573
	MUX_CFG(DA850, EMA_BA_1,	5,	24,	15,	1,	false)
574
	MUX_CFG(DA850, EMA_CLK,		6,	0,	15,	1,	false)
575
	MUX_CFG(DA850, EMA_WAIT_1,	6,	24,	15,	1,	false)
576
	MUX_CFG(DA850, NEMA_CS_2,	7,	0,	15,	1,	false)
577
	/* GPIO function */
578
	MUX_CFG(DA850, GPIO2_4,		6,	12,	15,	8,	false)
579
	MUX_CFG(DA850, GPIO2_6,		6,	4,	15,	8,	false)
580
	MUX_CFG(DA850, GPIO2_8,		5,	28,	15,	8,	false)
581
	MUX_CFG(DA850, GPIO2_15,	5,	0,	15,	8,	false)
582
	MUX_CFG(DA850, GPIO3_12,	7,	12,	15,	8,	false)
583
	MUX_CFG(DA850, GPIO3_13,	7,	8,	15,	8,	false)
584
	MUX_CFG(DA850, GPIO4_0,		10,	28,	15,	8,	false)
585
	MUX_CFG(DA850, GPIO4_1,		10,	24,	15,	8,	false)
586
	MUX_CFG(DA850, GPIO6_13,	13,	8,	15,	8,	false)
587
	MUX_CFG(DA850, RTC_ALARM,	0,	28,	15,	2,	false)
588
#endif
589
};
590

591
const short da850_i2c0_pins[] __initdata = {
592
	DA850_I2C0_SDA, DA850_I2C0_SCL,
593
	-1
594
};
595

596
const short da850_i2c1_pins[] __initdata = {
597
	DA850_I2C1_SCL, DA850_I2C1_SDA,
598
	-1
599
};
600

601
const short da850_lcdcntl_pins[] __initdata = {
602
	DA850_LCD_D_0, DA850_LCD_D_1, DA850_LCD_D_2, DA850_LCD_D_3,
603
	DA850_LCD_D_4, DA850_LCD_D_5, DA850_LCD_D_6, DA850_LCD_D_7,
604
	DA850_LCD_D_8, DA850_LCD_D_9, DA850_LCD_D_10, DA850_LCD_D_11,
605
	DA850_LCD_D_12, DA850_LCD_D_13, DA850_LCD_D_14, DA850_LCD_D_15,
606
	DA850_LCD_PCLK, DA850_LCD_HSYNC, DA850_LCD_VSYNC, DA850_NLCD_AC_ENB_CS,
607
	-1
608
};
609

610
/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
611
static u8 da850_default_priorities[DA850_N_CP_INTC_IRQ] = {
612
	[IRQ_DA8XX_COMMTX]		= 7,
613
	[IRQ_DA8XX_COMMRX]		= 7,
614
	[IRQ_DA8XX_NINT]		= 7,
615
	[IRQ_DA8XX_EVTOUT0]		= 7,
616
	[IRQ_DA8XX_EVTOUT1]		= 7,
617
	[IRQ_DA8XX_EVTOUT2]		= 7,
618
	[IRQ_DA8XX_EVTOUT3]		= 7,
619
	[IRQ_DA8XX_EVTOUT4]		= 7,
620
	[IRQ_DA8XX_EVTOUT5]		= 7,
621
	[IRQ_DA8XX_EVTOUT6]		= 7,
622
	[IRQ_DA8XX_EVTOUT7]		= 7,
623
	[IRQ_DA8XX_CCINT0]		= 7,
624
	[IRQ_DA8XX_CCERRINT]		= 7,
625
	[IRQ_DA8XX_TCERRINT0]		= 7,
626
	[IRQ_DA8XX_AEMIFINT]		= 7,
627
	[IRQ_DA8XX_I2CINT0]		= 7,
628
	[IRQ_DA8XX_MMCSDINT0]		= 7,
629
	[IRQ_DA8XX_MMCSDINT1]		= 7,
630
	[IRQ_DA8XX_ALLINT0]		= 7,
631
	[IRQ_DA8XX_RTC]			= 7,
632
	[IRQ_DA8XX_SPINT0]		= 7,
633
	[IRQ_DA8XX_TINT12_0]		= 7,
634
	[IRQ_DA8XX_TINT34_0]		= 7,
635
	[IRQ_DA8XX_TINT12_1]		= 7,
636
	[IRQ_DA8XX_TINT34_1]		= 7,
637
	[IRQ_DA8XX_UARTINT0]		= 7,
638
	[IRQ_DA8XX_KEYMGRINT]		= 7,
639
	[IRQ_DA850_MPUADDRERR0]		= 7,
640
	[IRQ_DA8XX_CHIPINT0]		= 7,
641
	[IRQ_DA8XX_CHIPINT1]		= 7,
642
	[IRQ_DA8XX_CHIPINT2]		= 7,
643
	[IRQ_DA8XX_CHIPINT3]		= 7,
644
	[IRQ_DA8XX_TCERRINT1]		= 7,
645
	[IRQ_DA8XX_C0_RX_THRESH_PULSE]	= 7,
646
	[IRQ_DA8XX_C0_RX_PULSE]		= 7,
647
	[IRQ_DA8XX_C0_TX_PULSE]		= 7,
648
	[IRQ_DA8XX_C0_MISC_PULSE]	= 7,
649
	[IRQ_DA8XX_C1_RX_THRESH_PULSE]	= 7,
650
	[IRQ_DA8XX_C1_RX_PULSE]		= 7,
651
	[IRQ_DA8XX_C1_TX_PULSE]		= 7,
652
	[IRQ_DA8XX_C1_MISC_PULSE]	= 7,
653
	[IRQ_DA8XX_MEMERR]		= 7,
654
	[IRQ_DA8XX_GPIO0]		= 7,
655
	[IRQ_DA8XX_GPIO1]		= 7,
656
	[IRQ_DA8XX_GPIO2]		= 7,
657
	[IRQ_DA8XX_GPIO3]		= 7,
658
	[IRQ_DA8XX_GPIO4]		= 7,
659
	[IRQ_DA8XX_GPIO5]		= 7,
660
	[IRQ_DA8XX_GPIO6]		= 7,
661
	[IRQ_DA8XX_GPIO7]		= 7,
662
	[IRQ_DA8XX_GPIO8]		= 7,
663
	[IRQ_DA8XX_I2CINT1]		= 7,
664
	[IRQ_DA8XX_LCDINT]		= 7,
665
	[IRQ_DA8XX_UARTINT1]		= 7,
666
	[IRQ_DA8XX_MCASPINT]		= 7,
667
	[IRQ_DA8XX_ALLINT1]		= 7,
668
	[IRQ_DA8XX_SPINT1]		= 7,
669
	[IRQ_DA8XX_UHPI_INT1]		= 7,
670
	[IRQ_DA8XX_USB_INT]		= 7,
671
	[IRQ_DA8XX_IRQN]		= 7,
672
	[IRQ_DA8XX_RWAKEUP]		= 7,
673
	[IRQ_DA8XX_UARTINT2]		= 7,
674
	[IRQ_DA8XX_DFTSSINT]		= 7,
675
	[IRQ_DA8XX_EHRPWM0]		= 7,
676
	[IRQ_DA8XX_EHRPWM0TZ]		= 7,
677
	[IRQ_DA8XX_EHRPWM1]		= 7,
678
	[IRQ_DA8XX_EHRPWM1TZ]		= 7,
679
	[IRQ_DA850_SATAINT]		= 7,
680
	[IRQ_DA850_TINTALL_2]		= 7,
681
	[IRQ_DA8XX_ECAP0]		= 7,
682
	[IRQ_DA8XX_ECAP1]		= 7,
683
	[IRQ_DA8XX_ECAP2]		= 7,
684
	[IRQ_DA850_MMCSDINT0_1]		= 7,
685
	[IRQ_DA850_MMCSDINT1_1]		= 7,
686
	[IRQ_DA850_T12CMPINT0_2]	= 7,
687
	[IRQ_DA850_T12CMPINT1_2]	= 7,
688
	[IRQ_DA850_T12CMPINT2_2]	= 7,
689
	[IRQ_DA850_T12CMPINT3_2]	= 7,
690
	[IRQ_DA850_T12CMPINT4_2]	= 7,
691
	[IRQ_DA850_T12CMPINT5_2]	= 7,
692
	[IRQ_DA850_T12CMPINT6_2]	= 7,
693
	[IRQ_DA850_T12CMPINT7_2]	= 7,
694
	[IRQ_DA850_T12CMPINT0_3]	= 7,
695
	[IRQ_DA850_T12CMPINT1_3]	= 7,
696
	[IRQ_DA850_T12CMPINT2_3]	= 7,
697
	[IRQ_DA850_T12CMPINT3_3]	= 7,
698
	[IRQ_DA850_T12CMPINT4_3]	= 7,
699
	[IRQ_DA850_T12CMPINT5_3]	= 7,
700
	[IRQ_DA850_T12CMPINT6_3]	= 7,
701
	[IRQ_DA850_T12CMPINT7_3]	= 7,
702
	[IRQ_DA850_RPIINT]		= 7,
703
	[IRQ_DA850_VPIFINT]		= 7,
704
	[IRQ_DA850_CCINT1]		= 7,
705
	[IRQ_DA850_CCERRINT1]		= 7,
706
	[IRQ_DA850_TCERRINT2]		= 7,
707
	[IRQ_DA850_TINTALL_3]		= 7,
708
	[IRQ_DA850_MCBSP0RINT]		= 7,
709
	[IRQ_DA850_MCBSP0XINT]		= 7,
710
	[IRQ_DA850_MCBSP1RINT]		= 7,
711
	[IRQ_DA850_MCBSP1XINT]		= 7,
712
	[IRQ_DA8XX_ARMCLKSTOPREQ]	= 7,
713
};
714

715
static struct map_desc da850_io_desc[] = {
716
	{
717
		.virtual	= IO_VIRT,
718
		.pfn		= __phys_to_pfn(IO_PHYS),
719
		.length		= IO_SIZE,
720
		.type		= MT_DEVICE
721
	},
722
	{
723
		.virtual	= DA8XX_CP_INTC_VIRT,
724
		.pfn		= __phys_to_pfn(DA8XX_CP_INTC_BASE),
725
		.length		= DA8XX_CP_INTC_SIZE,
726
		.type		= MT_DEVICE
727
	},
728
	{
729
		.virtual	= SRAM_VIRT,
730
		.pfn		= __phys_to_pfn(DA8XX_ARM_RAM_BASE),
731
		.length		= SZ_8K,
732
		.type		= MT_DEVICE
733
	},
734
};
735

736
static u32 da850_psc_bases[] = { DA8XX_PSC0_BASE, DA8XX_PSC1_BASE };
737

738
/* Contents of JTAG ID register used to identify exact cpu type */
739
static struct davinci_id da850_ids[] = {
740
	{
741
		.variant	= 0x0,
742
		.part_no	= 0xb7d1,
743
		.manufacturer	= 0x017,	/* 0x02f >> 1 */
744
		.cpu_id		= DAVINCI_CPU_ID_DA850,
745
		.name		= "da850/omap-l138",
746
	},
747
	{
748
		.variant	= 0x1,
749
		.part_no	= 0xb7d1,
750
		.manufacturer	= 0x017,	/* 0x02f >> 1 */
751
		.cpu_id		= DAVINCI_CPU_ID_DA850,
752
		.name		= "da850/omap-l138/am18x",
753
	},
754
};
755

756
static struct davinci_timer_instance da850_timer_instance[4] = {
757
	{
758
		.base		= DA8XX_TIMER64P0_BASE,
759
		.bottom_irq	= IRQ_DA8XX_TINT12_0,
760
		.top_irq	= IRQ_DA8XX_TINT34_0,
761
	},
762
	{
763
		.base		= DA8XX_TIMER64P1_BASE,
764
		.bottom_irq	= IRQ_DA8XX_TINT12_1,
765
		.top_irq	= IRQ_DA8XX_TINT34_1,
766
	},
767
	{
768
		.base		= DA850_TIMER64P2_BASE,
769
		.bottom_irq	= IRQ_DA850_TINT12_2,
770
		.top_irq	= IRQ_DA850_TINT34_2,
771
	},
772
	{
773
		.base		= DA850_TIMER64P3_BASE,
774
		.bottom_irq	= IRQ_DA850_TINT12_3,
775
		.top_irq	= IRQ_DA850_TINT34_3,
776
	},
777
};
778

779
/*
780
 * T0_BOT: Timer 0, bottom		: Used for clock_event
781
 * T0_TOP: Timer 0, top			: Used for clocksource
782
 * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer
783
 */
784
static struct davinci_timer_info da850_timer_info = {
785
	.timers		= da850_timer_instance,
786
	.clockevent_id	= T0_BOT,
787
	.clocksource_id	= T0_TOP,
788
};
789

790
static void da850_set_async3_src(int pllnum)
791
{
792
	struct clk *clk, *newparent = pllnum ? &pll1_sysclk2 : &pll0_sysclk2;
793
	struct clk_lookup *c;
794
	unsigned int v;
795
	int ret;
796

797
	for (c = da850_clks; c->clk; c++) {
798
		clk = c->clk;
799
		if (clk->flags & DA850_CLK_ASYNC3) {
800
			ret = clk_set_parent(clk, newparent);
801
			WARN(ret, "DA850: unable to re-parent clock %s",
802
								clk->name);
803
		}
804
       }
805

806
	v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
807
	if (pllnum)
808
		v |= CFGCHIP3_ASYNC3_CLKSRC;
809
	else
810
		v &= ~CFGCHIP3_ASYNC3_CLKSRC;
811
	__raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
812
}
813

814
#ifdef CONFIG_CPU_FREQ
815
/*
816
 * Notes:
817
 * According to the TRM, minimum PLLM results in maximum power savings.
818
 * The OPP definitions below should keep the PLLM as low as possible.
819
 *
820
 * The output of the PLLM must be between 300 to 600 MHz.
821
 */
822
struct da850_opp {
823
	unsigned int	freq;	/* in KHz */
824
	unsigned int	prediv;
825
	unsigned int	mult;
826
	unsigned int	postdiv;
827
	unsigned int	cvdd_min; /* in uV */
828
	unsigned int	cvdd_max; /* in uV */
829
};
830

831
static const struct da850_opp da850_opp_456 = {
832
	.freq		= 456000,
833
	.prediv		= 1,
834
	.mult		= 19,
835
	.postdiv	= 1,
836
	.cvdd_min	= 1300000,
837
	.cvdd_max	= 1350000,
838
};
839

840
static const struct da850_opp da850_opp_408 = {
841
	.freq		= 408000,
842
	.prediv		= 1,
843
	.mult		= 17,
844
	.postdiv	= 1,
845
	.cvdd_min	= 1300000,
846
	.cvdd_max	= 1350000,
847
};
848

849
static const struct da850_opp da850_opp_372 = {
850
	.freq		= 372000,
851
	.prediv		= 2,
852
	.mult		= 31,
853
	.postdiv	= 1,
854
	.cvdd_min	= 1200000,
855
	.cvdd_max	= 1320000,
856
};
857

858
static const struct da850_opp da850_opp_300 = {
859
	.freq		= 300000,
860
	.prediv		= 1,
861
	.mult		= 25,
862
	.postdiv	= 2,
863
	.cvdd_min	= 1200000,
864
	.cvdd_max	= 1320000,
865
};
866

867
static const struct da850_opp da850_opp_200 = {
868
	.freq		= 200000,
869
	.prediv		= 1,
870
	.mult		= 25,
871
	.postdiv	= 3,
872
	.cvdd_min	= 1100000,
873
	.cvdd_max	= 1160000,
874
};
875

876
static const struct da850_opp da850_opp_96 = {
877
	.freq		= 96000,
878
	.prediv		= 1,
879
	.mult		= 20,
880
	.postdiv	= 5,
881
	.cvdd_min	= 1000000,
882
	.cvdd_max	= 1050000,
883
};
884

885
#define OPP(freq) 		\
886
	{				\
887
		.index = (unsigned int) &da850_opp_##freq,	\
888
		.frequency = freq * 1000, \
889
	}
890

891
static struct cpufreq_frequency_table da850_freq_table[] = {
892
	OPP(456),
893
	OPP(408),
894
	OPP(372),
895
	OPP(300),
896
	OPP(200),
897
	OPP(96),
898
	{
899
		.index		= 0,
900
		.frequency	= CPUFREQ_TABLE_END,
901
	},
902
};
903

904
#ifdef CONFIG_REGULATOR
905
static int da850_set_voltage(unsigned int index);
906
static int da850_regulator_init(void);
907
#endif
908

909
static struct davinci_cpufreq_config cpufreq_info = {
910
	.freq_table = da850_freq_table,
911
#ifdef CONFIG_REGULATOR
912
	.init = da850_regulator_init,
913
	.set_voltage = da850_set_voltage,
914
#endif
915
};
916

917
#ifdef CONFIG_REGULATOR
918
static struct regulator *cvdd;
919

920
static int da850_set_voltage(unsigned int index)
921
{
922
	struct da850_opp *opp;
923

924
	if (!cvdd)
925
		return -ENODEV;
926

927
	opp = (struct da850_opp *) cpufreq_info.freq_table[index].index;
928

929
	return regulator_set_voltage(cvdd, opp->cvdd_min, opp->cvdd_max);
930
}
931

932
static int da850_regulator_init(void)
933
{
934
	cvdd = regulator_get(NULL, "cvdd");
935
	if (WARN(IS_ERR(cvdd), "Unable to obtain voltage regulator for CVDD;"
936
					" voltage scaling unsupported\n")) {
937
		return PTR_ERR(cvdd);
938
	}
939

940
	return 0;
941
}
942
#endif
943

944
static struct platform_device da850_cpufreq_device = {
945
	.name			= "cpufreq-davinci",
946
	.dev = {
947
		.platform_data	= &cpufreq_info,
948
	},
949
	.id = -1,
950
};
951

952
unsigned int da850_max_speed = 300000;
953

954
int __init da850_register_cpufreq(char *async_clk)
955
{
956
	int i;
957

958
	/* cpufreq driver can help keep an "async" clock constant */
959
	if (async_clk)
960
		clk_add_alias("async", da850_cpufreq_device.name,
961
							async_clk, NULL);
962
	for (i = 0; i < ARRAY_SIZE(da850_freq_table); i++) {
963
		if (da850_freq_table[i].frequency <= da850_max_speed) {
964
			cpufreq_info.freq_table = &da850_freq_table[i];
965
			break;
966
		}
967
	}
968

969
	return platform_device_register(&da850_cpufreq_device);
970
}
971

972
static int da850_round_armrate(struct clk *clk, unsigned long rate)
973
{
974
	int i, ret = 0, diff;
975
	unsigned int best = (unsigned int) -1;
976
	struct cpufreq_frequency_table *table = cpufreq_info.freq_table;
977

978
	rate /= 1000; /* convert to kHz */
979

980
	for (i = 0; table[i].frequency != CPUFREQ_TABLE_END; i++) {
981
		diff = table[i].frequency - rate;
982
		if (diff < 0)
983
			diff = -diff;
984

985
		if (diff < best) {
986
			best = diff;
987
			ret = table[i].frequency;
988
		}
989
	}
990

991
	return ret * 1000;
992
}
993

994
static int da850_set_armrate(struct clk *clk, unsigned long index)
995
{
996
	struct clk *pllclk = &pll0_clk;
997

998
	return clk_set_rate(pllclk, index);
999
}
1000

1001
static int da850_set_pll0rate(struct clk *clk, unsigned long index)
1002
{
1003
	unsigned int prediv, mult, postdiv;
1004
	struct da850_opp *opp;
1005
	struct pll_data *pll = clk->pll_data;
1006
	int ret;
1007

1008
	opp = (struct da850_opp *) cpufreq_info.freq_table[index].index;
1009
	prediv = opp->prediv;
1010
	mult = opp->mult;
1011
	postdiv = opp->postdiv;
1012

1013
	ret = davinci_set_pllrate(pll, prediv, mult, postdiv);
1014
	if (WARN_ON(ret))
1015
		return ret;
1016

1017
	return 0;
1018
}
1019
#else
1020
int __init da850_register_cpufreq(char *async_clk)
1021
{
1022
	return 0;
1023
}
1024

1025
static int da850_set_armrate(struct clk *clk, unsigned long rate)
1026
{
1027
	return -EINVAL;
1028
}
1029

1030
static int da850_set_pll0rate(struct clk *clk, unsigned long armrate)
1031
{
1032
	return -EINVAL;
1033
}
1034

1035
static int da850_round_armrate(struct clk *clk, unsigned long rate)
1036
{
1037
	return clk->rate;
1038
}
1039
#endif
1040

1041
int da850_register_pm(struct platform_device *pdev)
1042
{
1043
	int ret;
1044
	struct davinci_pm_config *pdata = pdev->dev.platform_data;
1045

1046
	ret = davinci_cfg_reg(DA850_RTC_ALARM);
1047
	if (ret)
1048
		return ret;
1049

1050
	pdata->ddr2_ctlr_base = da8xx_get_mem_ctlr();
1051
	pdata->deepsleep_reg = DA8XX_SYSCFG1_VIRT(DA8XX_DEEPSLEEP_REG);
1052
	pdata->ddrpsc_num = DA8XX_LPSC1_EMIF3C;
1053

1054
	pdata->cpupll_reg_base = ioremap(DA8XX_PLL0_BASE, SZ_4K);
1055
	if (!pdata->cpupll_reg_base)
1056
		return -ENOMEM;
1057

1058
	pdata->ddrpll_reg_base = ioremap(DA850_PLL1_BASE, SZ_4K);
1059
	if (!pdata->ddrpll_reg_base) {
1060
		ret = -ENOMEM;
1061
		goto no_ddrpll_mem;
1062
	}
1063

1064
	pdata->ddrpsc_reg_base = ioremap(DA8XX_PSC1_BASE, SZ_4K);
1065
	if (!pdata->ddrpsc_reg_base) {
1066
		ret = -ENOMEM;
1067
		goto no_ddrpsc_mem;
1068
	}
1069

1070
	return platform_device_register(pdev);
1071

1072
no_ddrpsc_mem:
1073
	iounmap(pdata->ddrpll_reg_base);
1074
no_ddrpll_mem:
1075
	iounmap(pdata->cpupll_reg_base);
1076
	return ret;
1077
}
1078

1079
static struct davinci_soc_info davinci_soc_info_da850 = {
1080
	.io_desc		= da850_io_desc,
1081
	.io_desc_num		= ARRAY_SIZE(da850_io_desc),
1082
	.jtag_id_reg		= DA8XX_SYSCFG0_BASE + DA8XX_JTAG_ID_REG,
1083
	.ids			= da850_ids,
1084
	.ids_num		= ARRAY_SIZE(da850_ids),
1085
	.cpu_clks		= da850_clks,
1086
	.psc_bases		= da850_psc_bases,
1087
	.psc_bases_num		= ARRAY_SIZE(da850_psc_bases),
1088
	.pinmux_base		= DA8XX_SYSCFG0_BASE + 0x120,
1089
	.pinmux_pins		= da850_pins,
1090
	.pinmux_pins_num	= ARRAY_SIZE(da850_pins),
1091
	.intc_base		= DA8XX_CP_INTC_BASE,
1092
	.intc_type		= DAVINCI_INTC_TYPE_CP_INTC,
1093
	.intc_irq_prios		= da850_default_priorities,
1094
	.intc_irq_num		= DA850_N_CP_INTC_IRQ,
1095
	.timer_info		= &da850_timer_info,
1096
	.gpio_type		= GPIO_TYPE_DAVINCI,
1097
	.gpio_base		= DA8XX_GPIO_BASE,
1098
	.gpio_num		= 144,
1099
	.gpio_irq		= IRQ_DA8XX_GPIO0,
1100
	.serial_dev		= &da8xx_serial_device,
1101
	.emac_pdata		= &da8xx_emac_pdata,
1102
	.sram_dma		= DA8XX_ARM_RAM_BASE,
1103
	.sram_len		= SZ_8K,
1104
	.reset_device		= &da8xx_wdt_device,
1105
};
1106

1107
void __init da850_init(void)
1108
{
1109
	unsigned int v;
1110

1111
	davinci_common_init(&davinci_soc_info_da850);
1112

1113
	da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K);
1114
	if (WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module"))
1115
		return;
1116

1117
	da8xx_syscfg1_base = ioremap(DA8XX_SYSCFG1_BASE, SZ_4K);
1118
	if (WARN(!da8xx_syscfg1_base, "Unable to map syscfg1 module"))
1119
		return;
1120

1121
	/*
1122
	 * Move the clock source of Async3 domain to PLL1 SYSCLK2.
1123
	 * This helps keeping the peripherals on this domain insulated
1124
	 * from CPU frequency changes caused by DVFS. The firmware sets
1125
	 * both PLL0 and PLL1 to the same frequency so, there should not
1126
	 * be any noticeable change even in non-DVFS use cases.
1127
	 */
1128
	da850_set_async3_src(1);
1129

1130
	/* Unlock writing to PLL0 registers */
1131
	v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG));
1132
	v &= ~CFGCHIP0_PLL_MASTER_LOCK;
1133
	__raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG));
1134

1135
	/* Unlock writing to PLL1 registers */
1136
	v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
1137
	v &= ~CFGCHIP3_PLL1_MASTER_LOCK;
1138
	__raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
1139
}
1140

1141
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