Path: blob/master/arch/arm/mach-dove/include/mach/bridge-regs.h
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/*1* arch/arm/mach-dove/include/mach/bridge-regs.h2*3* Mbus-L to Mbus Bridge Registers4*5* This file is licensed under the terms of the GNU General Public6* License version 2. This program is licensed "as is" without any7* warranty of any kind, whether express or implied.8*/910#ifndef __ASM_ARCH_BRIDGE_REGS_H11#define __ASM_ARCH_BRIDGE_REGS_H1213#include <mach/dove.h>1415#define CPU_CONFIG (BRIDGE_VIRT_BASE | 0x0000)1617#define CPU_CONTROL (BRIDGE_VIRT_BASE | 0x0104)18#define CPU_CTRL_PCIE0_LINK 0x0000000119#define CPU_RESET 0x0000000220#define CPU_CTRL_PCIE1_LINK 0x000000082122#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108)23#define SOFT_RESET_OUT_EN 0x000000042425#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c)26#define SOFT_RESET 0x000000012728#define BRIDGE_INT_TIMER1_CLR (~0x0004)2930#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200)31#define IRQ_CAUSE_LOW_OFF 0x000032#define IRQ_MASK_LOW_OFF 0x000433#define FIQ_MASK_LOW_OFF 0x000834#define ENDPOINT_MASK_LOW_OFF 0x000c35#define IRQ_CAUSE_HIGH_OFF 0x001036#define IRQ_MASK_HIGH_OFF 0x001437#define FIQ_MASK_HIGH_OFF 0x001838#define ENDPOINT_MASK_HIGH_OFF 0x001c39#define PCIE_INTERRUPT_MASK_OFF 0x00204041#define IRQ_MASK_LOW (IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF)42#define FIQ_MASK_LOW (IRQ_VIRT_BASE + FIQ_MASK_LOW_OFF)43#define ENDPOINT_MASK_LOW (IRQ_VIRT_BASE + ENDPOINT_MASK_LOW_OFF)44#define IRQ_MASK_HIGH (IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF)45#define FIQ_MASK_HIGH (IRQ_VIRT_BASE + FIQ_MASK_HIGH_OFF)46#define ENDPOINT_MASK_HIGH (IRQ_VIRT_BASE + ENDPOINT_MASK_HIGH_OFF)47#define PCIE_INTERRUPT_MASK (IRQ_VIRT_BASE + PCIE_INTERRUPT_MASK_OFF)4849#define POWER_MANAGEMENT (BRIDGE_VIRT_BASE | 0x011c)5051#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300)5253#endif545556