Path: blob/master/arch/arm/mach-ep93xx/include/mach/hardware.h
15157 views
/*1* arch/arm/mach-ep93xx/include/mach/hardware.h2*/34#ifndef __ASM_ARCH_HARDWARE_H5#define __ASM_ARCH_HARDWARE_H67#include <mach/ep93xx-regs.h>8#include <mach/platform.h>910#define pcibios_assign_all_busses() 01112/*13* The EP93xx has two external crystal oscillators. To generate the14* required high-frequency clocks, the processor uses two phase-locked-15* loops (PLLs) to multiply the incoming external clock signal to much16* higher frequencies that are then divided down by programmable dividers17* to produce the needed clocks. The PLLs operate independently of one18* another.19*/20#define EP93XX_EXT_CLK_RATE 1474560021#define EP93XX_EXT_RTC_RATE 327682223#define EP93XX_KEYTCHCLK_DIV4 (EP93XX_EXT_CLK_RATE / 4)24#define EP93XX_KEYTCHCLK_DIV16 (EP93XX_EXT_CLK_RATE / 16)2526#endif272829