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awilliam
GitHub Repository: awilliam/linux-vfio
 Path: blob/master/arch/arm/mach-exynos4/include/mach/regs-clock.h
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/* linux/arch/arm/mach-exynos4/include/mach/regs-clock.h

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 *

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 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.

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 *		http://www.samsung.com

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 *

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 * EXYNOS4 - Clock register definitions

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 *

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 * This program is free software; you can redistribute it and/or modify

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 * it under the terms of the GNU General Public License version 2 as

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 * published by the Free Software Foundation.

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*/

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#ifndef __ASM_ARCH_REGS_CLOCK_H

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#define __ASM_ARCH_REGS_CLOCK_H __FILE__

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#include <mach/map.h>

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#define S5P_CLKREG(x)			(S5P_VA_CMU + (x))

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#define S5P_CLKDIV_LEFTBUS		S5P_CLKREG(0x04500)

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#define S5P_CLKDIV_STAT_LEFTBUS		S5P_CLKREG(0x04600)

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#define S5P_CLKGATE_IP_LEFTBUS		S5P_CLKREG(0x04800)

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#define S5P_CLKDIV_RIGHTBUS		S5P_CLKREG(0x08500)

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#define S5P_CLKDIV_STAT_RIGHTBUS	S5P_CLKREG(0x08600)

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#define S5P_CLKGATE_IP_RIGHTBUS		S5P_CLKREG(0x08800)

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#define S5P_EPLL_CON0			S5P_CLKREG(0x0C110)

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#define S5P_EPLL_CON1			S5P_CLKREG(0x0C114)

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#define S5P_VPLL_CON0			S5P_CLKREG(0x0C120)

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#define S5P_VPLL_CON1			S5P_CLKREG(0x0C124)

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#define S5P_CLKSRC_TOP0			S5P_CLKREG(0x0C210)

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#define S5P_CLKSRC_TOP1			S5P_CLKREG(0x0C214)

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#define S5P_CLKSRC_CAM			S5P_CLKREG(0x0C220)

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#define S5P_CLKSRC_MFC			S5P_CLKREG(0x0C228)

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#define S5P_CLKSRC_IMAGE		S5P_CLKREG(0x0C230)

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#define S5P_CLKSRC_LCD0			S5P_CLKREG(0x0C234)

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#define S5P_CLKSRC_LCD1			S5P_CLKREG(0x0C238)

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#define S5P_CLKSRC_MAUDIO		S5P_CLKREG(0x0C23C)

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#define S5P_CLKSRC_FSYS			S5P_CLKREG(0x0C240)

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#define S5P_CLKSRC_PERIL0		S5P_CLKREG(0x0C250)

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#define S5P_CLKSRC_PERIL1		S5P_CLKREG(0x0C254)

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#define S5P_CLKDIV_TOP			S5P_CLKREG(0x0C510)

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#define S5P_CLKDIV_CAM			S5P_CLKREG(0x0C520)

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#define S5P_CLKDIV_TV			S5P_CLKREG(0x0C524)

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#define S5P_CLKDIV_MFC			S5P_CLKREG(0x0C528)

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#define S5P_CLKDIV_G3D			S5P_CLKREG(0x0C52C)

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#define S5P_CLKDIV_IMAGE		S5P_CLKREG(0x0C530)

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#define S5P_CLKDIV_LCD0			S5P_CLKREG(0x0C534)

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#define S5P_CLKDIV_LCD1			S5P_CLKREG(0x0C538)

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#define S5P_CLKDIV_MAUDIO		S5P_CLKREG(0x0C53C)

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#define S5P_CLKDIV_FSYS0		S5P_CLKREG(0x0C540)

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#define S5P_CLKDIV_FSYS1		S5P_CLKREG(0x0C544)

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#define S5P_CLKDIV_FSYS2		S5P_CLKREG(0x0C548)

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#define S5P_CLKDIV_FSYS3		S5P_CLKREG(0x0C54C)

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#define S5P_CLKDIV_PERIL0		S5P_CLKREG(0x0C550)

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#define S5P_CLKDIV_PERIL1		S5P_CLKREG(0x0C554)

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#define S5P_CLKDIV_PERIL2		S5P_CLKREG(0x0C558)

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#define S5P_CLKDIV_PERIL3		S5P_CLKREG(0x0C55C)

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#define S5P_CLKDIV_PERIL4		S5P_CLKREG(0x0C560)

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#define S5P_CLKDIV_PERIL5		S5P_CLKREG(0x0C564)

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#define S5P_CLKSRC_MASK_TOP		S5P_CLKREG(0x0C310)

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#define S5P_CLKSRC_MASK_CAM		S5P_CLKREG(0x0C320)

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#define S5P_CLKSRC_MASK_TV		S5P_CLKREG(0x0C324)

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#define S5P_CLKSRC_MASK_LCD0		S5P_CLKREG(0x0C334)

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#define S5P_CLKSRC_MASK_LCD1		S5P_CLKREG(0x0C338)

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#define S5P_CLKSRC_MASK_MAUDIO		S5P_CLKREG(0x0C33C)

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#define S5P_CLKSRC_MASK_FSYS		S5P_CLKREG(0x0C340)

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#define S5P_CLKSRC_MASK_PERIL0		S5P_CLKREG(0x0C350)

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#define S5P_CLKSRC_MASK_PERIL1		S5P_CLKREG(0x0C354)

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#define S5P_CLKDIV_STAT_TOP		S5P_CLKREG(0x0C610)

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#define S5P_CLKGATE_SCLKCAM		S5P_CLKREG(0x0C820)

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#define S5P_CLKGATE_IP_CAM		S5P_CLKREG(0x0C920)

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#define S5P_CLKGATE_IP_TV		S5P_CLKREG(0x0C924)

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#define S5P_CLKGATE_IP_MFC		S5P_CLKREG(0x0C928)

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#define S5P_CLKGATE_IP_G3D		S5P_CLKREG(0x0C92C)

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#define S5P_CLKGATE_IP_IMAGE		S5P_CLKREG(0x0C930)

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#define S5P_CLKGATE_IP_LCD0		S5P_CLKREG(0x0C934)

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#define S5P_CLKGATE_IP_LCD1		S5P_CLKREG(0x0C938)

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#define S5P_CLKGATE_IP_FSYS		S5P_CLKREG(0x0C940)

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#define S5P_CLKGATE_IP_GPS		S5P_CLKREG(0x0C94C)

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#define S5P_CLKGATE_IP_PERIL		S5P_CLKREG(0x0C950)

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#define S5P_CLKGATE_IP_PERIR		S5P_CLKREG(0x0C960)

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#define S5P_CLKGATE_BLOCK		S5P_CLKREG(0x0C970)

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#define S5P_CLKSRC_MASK_DMC		S5P_CLKREG(0x10300)

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#define S5P_CLKSRC_DMC			S5P_CLKREG(0x10200)

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#define S5P_CLKDIV_DMC0			S5P_CLKREG(0x10500)

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#define S5P_CLKDIV_DMC1			S5P_CLKREG(0x10504)

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#define S5P_CLKDIV_STAT_DMC0		S5P_CLKREG(0x10600)

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#define S5P_CLKGATE_IP_DMC		S5P_CLKREG(0x10900)

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#define S5P_APLL_LOCK			S5P_CLKREG(0x14000)

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#define S5P_MPLL_LOCK			S5P_CLKREG(0x14004)

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#define S5P_APLL_CON0			S5P_CLKREG(0x14100)

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#define S5P_APLL_CON1			S5P_CLKREG(0x14104)

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#define S5P_MPLL_CON0			S5P_CLKREG(0x14108)

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#define S5P_MPLL_CON1			S5P_CLKREG(0x1410C)

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#define S5P_CLKSRC_CPU			S5P_CLKREG(0x14200)

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#define S5P_CLKMUX_STATCPU		S5P_CLKREG(0x14400)

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#define S5P_CLKDIV_CPU			S5P_CLKREG(0x14500)

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#define S5P_CLKDIV_CPU1			S5P_CLKREG(0x14504)

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#define S5P_CLKDIV_STATCPU		S5P_CLKREG(0x14600)

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#define S5P_CLKDIV_STATCPU1		S5P_CLKREG(0x14604)

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#define S5P_CLKGATE_SCLKCPU		S5P_CLKREG(0x14800)

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#define S5P_CLKGATE_IP_CPU		S5P_CLKREG(0x14900)

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#define S5P_APLL_LOCKTIME		(0x1C20)	/* 300us */

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#define S5P_APLLCON0_ENABLE_SHIFT	(31)

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#define S5P_APLLCON0_LOCKED_SHIFT	(29)

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#define S5P_APLL_VAL_1000		((250 << 16) | (6 << 8) | 1)

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#define S5P_APLL_VAL_800		((200 << 16) | (6 << 8) | 1)

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#define S5P_CLKSRC_CPU_MUXCORE_SHIFT	(16)

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#define S5P_CLKMUX_STATCPU_MUXCORE_MASK	(0x7 << S5P_CLKSRC_CPU_MUXCORE_SHIFT)

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#define S5P_CLKDIV_CPU0_CORE_SHIFT	(0)

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#define S5P_CLKDIV_CPU0_CORE_MASK	(0x7 << S5P_CLKDIV_CPU0_CORE_SHIFT)

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#define S5P_CLKDIV_CPU0_COREM0_SHIFT	(4)

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#define S5P_CLKDIV_CPU0_COREM0_MASK	(0x7 << S5P_CLKDIV_CPU0_COREM0_SHIFT)

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#define S5P_CLKDIV_CPU0_COREM1_SHIFT	(8)

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#define S5P_CLKDIV_CPU0_COREM1_MASK	(0x7 << S5P_CLKDIV_CPU0_COREM1_SHIFT)

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#define S5P_CLKDIV_CPU0_PERIPH_SHIFT	(12)

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#define S5P_CLKDIV_CPU0_PERIPH_MASK	(0x7 << S5P_CLKDIV_CPU0_PERIPH_SHIFT)

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#define S5P_CLKDIV_CPU0_ATB_SHIFT	(16)

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#define S5P_CLKDIV_CPU0_ATB_MASK	(0x7 << S5P_CLKDIV_CPU0_ATB_SHIFT)

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#define S5P_CLKDIV_CPU0_PCLKDBG_SHIFT	(20)

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#define S5P_CLKDIV_CPU0_PCLKDBG_MASK	(0x7 << S5P_CLKDIV_CPU0_PCLKDBG_SHIFT)

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#define S5P_CLKDIV_CPU0_APLL_SHIFT	(24)

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#define S5P_CLKDIV_CPU0_APLL_MASK	(0x7 << S5P_CLKDIV_CPU0_APLL_SHIFT)

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#define S5P_CLKDIV_DMC0_ACP_SHIFT	(0)

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#define S5P_CLKDIV_DMC0_ACP_MASK	(0x7 << S5P_CLKDIV_DMC0_ACP_SHIFT)

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#define S5P_CLKDIV_DMC0_ACPPCLK_SHIFT	(4)

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#define S5P_CLKDIV_DMC0_ACPPCLK_MASK	(0x7 << S5P_CLKDIV_DMC0_ACPPCLK_SHIFT)

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#define S5P_CLKDIV_DMC0_DPHY_SHIFT	(8)

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#define S5P_CLKDIV_DMC0_DPHY_MASK	(0x7 << S5P_CLKDIV_DMC0_DPHY_SHIFT)

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#define S5P_CLKDIV_DMC0_DMC_SHIFT	(12)

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#define S5P_CLKDIV_DMC0_DMC_MASK	(0x7 << S5P_CLKDIV_DMC0_DMC_SHIFT)

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#define S5P_CLKDIV_DMC0_DMCD_SHIFT	(16)

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#define S5P_CLKDIV_DMC0_DMCD_MASK	(0x7 << S5P_CLKDIV_DMC0_DMCD_SHIFT)

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#define S5P_CLKDIV_DMC0_DMCP_SHIFT	(20)

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#define S5P_CLKDIV_DMC0_DMCP_MASK	(0x7 << S5P_CLKDIV_DMC0_DMCP_SHIFT)

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#define S5P_CLKDIV_DMC0_COPY2_SHIFT	(24)

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#define S5P_CLKDIV_DMC0_COPY2_MASK	(0x7 << S5P_CLKDIV_DMC0_COPY2_SHIFT)

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#define S5P_CLKDIV_DMC0_CORETI_SHIFT	(28)

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#define S5P_CLKDIV_DMC0_CORETI_MASK	(0x7 << S5P_CLKDIV_DMC0_CORETI_SHIFT)

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#define S5P_CLKDIV_TOP_ACLK200_SHIFT	(0)

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#define S5P_CLKDIV_TOP_ACLK200_MASK	(0x7 << S5P_CLKDIV_TOP_ACLK200_SHIFT)

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#define S5P_CLKDIV_TOP_ACLK100_SHIFT	(4)

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#define S5P_CLKDIV_TOP_ACLK100_MASK	(0xf << S5P_CLKDIV_TOP_ACLK100_SHIFT)

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#define S5P_CLKDIV_TOP_ACLK160_SHIFT	(8)

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#define S5P_CLKDIV_TOP_ACLK160_MASK	(0x7 << S5P_CLKDIV_TOP_ACLK160_SHIFT)

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#define S5P_CLKDIV_TOP_ACLK133_SHIFT	(12)

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#define S5P_CLKDIV_TOP_ACLK133_MASK	(0x7 << S5P_CLKDIV_TOP_ACLK133_SHIFT)

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#define S5P_CLKDIV_TOP_ONENAND_SHIFT	(16)

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#define S5P_CLKDIV_TOP_ONENAND_MASK	(0x7 << S5P_CLKDIV_TOP_ONENAND_SHIFT)

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#define S5P_CLKDIV_BUS_GDLR_SHIFT	(0)

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#define S5P_CLKDIV_BUS_GDLR_MASK	(0x7 << S5P_CLKDIV_BUS_GDLR_SHIFT)

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#define S5P_CLKDIV_BUS_GPLR_SHIFT	(4)

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#define S5P_CLKDIV_BUS_GPLR_MASK	(0x7 << S5P_CLKDIV_BUS_GPLR_SHIFT)

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/* Compatibility defines and inclusion */

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#include <mach/regs-pmu.h>

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#define S5P_EPLL_CON			S5P_EPLL_CON0

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#endif /* __ASM_ARCH_REGS_CLOCK_H */

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