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awilliam
GitHub Repository: awilliam/linux-vfio
 Path: blob/master/arch/arm/mach-exynos4/include/mach/regs-pmu.h
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/* linux/arch/arm/mach-exynos4/include/mach/regs-pmu.h

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 *

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 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.

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 *		http://www.samsung.com

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 *

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 * EXYNOS4 - Power management unit definition

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 *

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 * This program is free software; you can redistribute it and/or modify

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 * it under the terms of the GNU General Public License version 2 as

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 * published by the Free Software Foundation.

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*/

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#ifndef __ASM_ARCH_REGS_PMU_H

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#define __ASM_ARCH_REGS_PMU_H __FILE__

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#include <mach/map.h>

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#define S5P_PMUREG(x)				(S5P_VA_PMU + (x))

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#define S5P_CENTRAL_SEQ_CONFIGURATION		S5P_PMUREG(0x0200)

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#define S5P_CENTRAL_LOWPWR_CFG			(1 << 16)

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#define S5P_CENTRAL_SEQ_OPTION			S5P_PMUREG(0x0208)

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#define S5P_USE_STANDBY_WFI0			(1 << 16)

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#define S5P_USE_STANDBY_WFI1			(1 << 17)

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#define S5P_USE_STANDBY_WFE0			(1 << 24)

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#define S5P_USE_STANDBY_WFE1			(1 << 25)

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#define S5P_USE_MASK				((0x3 << 16) | (0x3 << 24))

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#define S5P_WAKEUP_STAT				S5P_PMUREG(0x0600)

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#define S5P_EINT_WAKEUP_MASK			S5P_PMUREG(0x0604)

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#define S5P_WAKEUP_MASK				S5P_PMUREG(0x0608)

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#define S5P_USBHOST_PHY_CONTROL			S5P_PMUREG(0x0708)

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#define S5P_USBHOST_PHY_ENABLE			(1 << 0)

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#define S5P_MIPI_DPHY_CONTROL(n)		S5P_PMUREG(0x0710 + (n) * 4)

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#define S5P_MIPI_DPHY_ENABLE			(1 << 0)

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#define S5P_MIPI_DPHY_SRESETN			(1 << 1)

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#define S5P_MIPI_DPHY_MRESETN			(1 << 2)

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#define S5P_PMU_SATA_PHY_CONTROL		S5P_PMUREG(0x0720)

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#define S5P_INFORM0				S5P_PMUREG(0x0800)

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#define S5P_INFORM1				S5P_PMUREG(0x0804)

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#define S5P_INFORM2				S5P_PMUREG(0x0808)

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#define S5P_INFORM3				S5P_PMUREG(0x080C)

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#define S5P_INFORM4				S5P_PMUREG(0x0810)

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#define S5P_INFORM5				S5P_PMUREG(0x0814)

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#define S5P_INFORM6				S5P_PMUREG(0x0818)

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#define S5P_INFORM7				S5P_PMUREG(0x081C)

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#define S5P_ARM_CORE0_LOWPWR			S5P_PMUREG(0x1000)

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#define S5P_DIS_IRQ_CORE0			S5P_PMUREG(0x1004)

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#define S5P_DIS_IRQ_CENTRAL0			S5P_PMUREG(0x1008)

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#define S5P_ARM_CORE1_LOWPWR			S5P_PMUREG(0x1010)

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#define S5P_DIS_IRQ_CORE1			S5P_PMUREG(0x1014)

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#define S5P_DIS_IRQ_CENTRAL1			S5P_PMUREG(0x1018)

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#define S5P_ARM_COMMON_LOWPWR			S5P_PMUREG(0x1080)

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#define S5P_L2_0_LOWPWR				S5P_PMUREG(0x10C0)

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#define S5P_L2_1_LOWPWR				S5P_PMUREG(0x10C4)

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#define S5P_CMU_ACLKSTOP_LOWPWR			S5P_PMUREG(0x1100)

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#define S5P_CMU_SCLKSTOP_LOWPWR			S5P_PMUREG(0x1104)

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#define S5P_CMU_RESET_LOWPWR			S5P_PMUREG(0x110C)

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#define S5P_APLL_SYSCLK_LOWPWR			S5P_PMUREG(0x1120)

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#define S5P_MPLL_SYSCLK_LOWPWR			S5P_PMUREG(0x1124)

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#define S5P_VPLL_SYSCLK_LOWPWR			S5P_PMUREG(0x1128)

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#define S5P_EPLL_SYSCLK_LOWPWR			S5P_PMUREG(0x112C)

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#define S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR	S5P_PMUREG(0x1138)

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#define S5P_CMU_RESET_GPSALIVE_LOWPWR		S5P_PMUREG(0x113C)

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#define S5P_CMU_CLKSTOP_CAM_LOWPWR		S5P_PMUREG(0x1140)

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#define S5P_CMU_CLKSTOP_TV_LOWPWR		S5P_PMUREG(0x1144)

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#define S5P_CMU_CLKSTOP_MFC_LOWPWR		S5P_PMUREG(0x1148)

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#define S5P_CMU_CLKSTOP_G3D_LOWPWR		S5P_PMUREG(0x114C)

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#define S5P_CMU_CLKSTOP_LCD0_LOWPWR		S5P_PMUREG(0x1150)

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#define S5P_CMU_CLKSTOP_LCD1_LOWPWR		S5P_PMUREG(0x1154)

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#define S5P_CMU_CLKSTOP_MAUDIO_LOWPWR		S5P_PMUREG(0x1158)

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#define S5P_CMU_CLKSTOP_GPS_LOWPWR		S5P_PMUREG(0x115C)

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#define S5P_CMU_RESET_CAM_LOWPWR		S5P_PMUREG(0x1160)

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#define S5P_CMU_RESET_TV_LOWPWR			S5P_PMUREG(0x1164)

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#define S5P_CMU_RESET_MFC_LOWPWR		S5P_PMUREG(0x1168)

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#define S5P_CMU_RESET_G3D_LOWPWR		S5P_PMUREG(0x116C)

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#define S5P_CMU_RESET_LCD0_LOWPWR		S5P_PMUREG(0x1170)

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#define S5P_CMU_RESET_LCD1_LOWPWR		S5P_PMUREG(0x1174)

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#define S5P_CMU_RESET_MAUDIO_LOWPWR		S5P_PMUREG(0x1178)

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#define S5P_CMU_RESET_GPS_LOWPWR		S5P_PMUREG(0x117C)

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#define S5P_TOP_BUS_LOWPWR			S5P_PMUREG(0x1180)

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#define S5P_TOP_RETENTION_LOWPWR		S5P_PMUREG(0x1184)

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#define S5P_TOP_PWR_LOWPWR			S5P_PMUREG(0x1188)

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#define S5P_LOGIC_RESET_LOWPWR			S5P_PMUREG(0x11A0)

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#define S5P_ONENAND_MEM_LOWPWR			S5P_PMUREG(0x11C0)

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#define S5P_MODIMIF_MEM_LOWPWR			S5P_PMUREG(0x11C4)

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#define S5P_G2D_ACP_MEM_LOWPWR			S5P_PMUREG(0x11C8)

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#define S5P_USBOTG_MEM_LOWPWR			S5P_PMUREG(0x11CC)

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#define S5P_HSMMC_MEM_LOWPWR			S5P_PMUREG(0x11D0)

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#define S5P_CSSYS_MEM_LOWPWR			S5P_PMUREG(0x11D4)

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#define S5P_SECSS_MEM_LOWPWR			S5P_PMUREG(0x11D8)

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#define S5P_PCIE_MEM_LOWPWR			S5P_PMUREG(0x11E0)

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#define S5P_SATA_MEM_LOWPWR			S5P_PMUREG(0x11E4)

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#define S5P_PAD_RETENTION_DRAM_LOWPWR		S5P_PMUREG(0x1200)

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#define S5P_PAD_RETENTION_MAUDIO_LOWPWR		S5P_PMUREG(0x1204)

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#define S5P_PAD_RETENTION_GPIO_LOWPWR		S5P_PMUREG(0x1220)

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#define S5P_PAD_RETENTION_UART_LOWPWR		S5P_PMUREG(0x1224)

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#define S5P_PAD_RETENTION_MMCA_LOWPWR		S5P_PMUREG(0x1228)

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#define S5P_PAD_RETENTION_MMCB_LOWPWR		S5P_PMUREG(0x122C)

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#define S5P_PAD_RETENTION_EBIA_LOWPWR		S5P_PMUREG(0x1230)

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#define S5P_PAD_RETENTION_EBIB_LOWPWR		S5P_PMUREG(0x1234)

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#define S5P_PAD_RETENTION_ISOLATION_LOWPWR	S5P_PMUREG(0x1240)

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#define S5P_PAD_RETENTION_ALV_SEL_LOWPWR	S5P_PMUREG(0x1260)

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#define S5P_XUSBXTI_LOWPWR			S5P_PMUREG(0x1280)

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#define S5P_XXTI_LOWPWR				S5P_PMUREG(0x1284)

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#define S5P_EXT_REGULATOR_LOWPWR		S5P_PMUREG(0x12C0)

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#define S5P_GPIO_MODE_LOWPWR			S5P_PMUREG(0x1300)

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#define S5P_GPIO_MODE_MAUDIO_LOWPWR		S5P_PMUREG(0x1340)

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#define S5P_CAM_LOWPWR				S5P_PMUREG(0x1380)

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#define S5P_TV_LOWPWR				S5P_PMUREG(0x1384)

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#define S5P_MFC_LOWPWR				S5P_PMUREG(0x1388)

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#define S5P_G3D_LOWPWR				S5P_PMUREG(0x138C)

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#define S5P_LCD0_LOWPWR				S5P_PMUREG(0x1390)

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#define S5P_LCD1_LOWPWR				S5P_PMUREG(0x1394)

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#define S5P_MAUDIO_LOWPWR			S5P_PMUREG(0x1398)

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#define S5P_GPS_LOWPWR				S5P_PMUREG(0x139C)

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#define S5P_GPS_ALIVE_LOWPWR			S5P_PMUREG(0x13A0)

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#define S5P_ARM_CORE0_CONFIGURATION		S5P_PMUREG(0x2000)

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#define S5P_ARM_CORE0_OPTION			S5P_PMUREG(0x2008)

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#define S5P_ARM_CORE1_CONFIGURATION		S5P_PMUREG(0x2080)

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#define S5P_ARM_CORE1_STATUS			S5P_PMUREG(0x2084)

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#define S5P_ARM_CORE1_OPTION			S5P_PMUREG(0x2088)

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#define S5P_ARM_COMMON_OPTION			S5P_PMUREG(0x2408)

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#define S5P_TOP_PWR_OPTION			S5P_PMUREG(0x2C48)

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#define S5P_CAM_OPTION				S5P_PMUREG(0x3C08)

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#define S5P_TV_OPTION				S5P_PMUREG(0x3C28)

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#define S5P_MFC_OPTION				S5P_PMUREG(0x3C48)

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#define S5P_G3D_OPTION				S5P_PMUREG(0x3C68)

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#define S5P_LCD0_OPTION				S5P_PMUREG(0x3C88)

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#define S5P_LCD1_OPTION				S5P_PMUREG(0x3CA8)

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#define S5P_MAUDIO_OPTION			S5P_PMUREG(0x3CC8)

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#define S5P_GPS_OPTION				S5P_PMUREG(0x3CE8)

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#define S5P_GPS_ALIVE_OPTION			S5P_PMUREG(0x3D08)

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#define S5P_PAD_RET_MAUDIO_OPTION		S5P_PMUREG(0x3028)

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#define S5P_PAD_RET_GPIO_OPTION			S5P_PMUREG(0x3108)

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#define S5P_PAD_RET_UART_OPTION			S5P_PMUREG(0x3128)

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#define S5P_PAD_RET_MMCA_OPTION			S5P_PMUREG(0x3148)

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#define S5P_PAD_RET_MMCB_OPTION			S5P_PMUREG(0x3168)

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#define S5P_PAD_RET_EBIA_OPTION			S5P_PMUREG(0x3188)

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#define S5P_PAD_RET_EBIB_OPTION			S5P_PMUREG(0x31A8)

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#define S5P_PMU_CAM_CONF			S5P_PMUREG(0x3C00)

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#define S5P_PMU_TV_CONF				S5P_PMUREG(0x3C20)

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#define S5P_PMU_MFC_CONF			S5P_PMUREG(0x3C40)

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#define S5P_PMU_G3D_CONF			S5P_PMUREG(0x3C60)

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#define S5P_PMU_LCD0_CONF			S5P_PMUREG(0x3C80)

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#define S5P_PMU_LCD1_CONF			S5P_PMUREG(0x3CA0)

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#define S5P_PMU_GPS_CONF			S5P_PMUREG(0x3CE0)

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#define S5P_PMU_SATA_PHY_CONTROL_EN		0x1

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#define S5P_INT_LOCAL_PWR_EN			0x7

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#define S5P_CHECK_SLEEP				0x00000BAD

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#endif /* __ASM_ARCH_REGS_PMU_H */

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