Path: blob/master/arch/arm/mach-exynos4/mach-universal_c210.c
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/* linux/arch/arm/mach-exynos4/mach-universal_c210.c1*2* Copyright (c) 2010 Samsung Electronics Co., Ltd.3*4* This program is free software; you can redistribute it and/or modify5* it under the terms of the GNU General Public License version 2 as6* published by the Free Software Foundation.7*/89#include <linux/platform_device.h>10#include <linux/serial_core.h>11#include <linux/input.h>12#include <linux/i2c.h>13#include <linux/gpio_keys.h>14#include <linux/gpio.h>15#include <linux/mfd/max8998.h>16#include <linux/regulator/machine.h>17#include <linux/regulator/fixed.h>18#include <linux/regulator/max8952.h>19#include <linux/mmc/host.h>2021#include <asm/mach/arch.h>22#include <asm/mach-types.h>2324#include <plat/regs-serial.h>25#include <plat/exynos4.h>26#include <plat/cpu.h>27#include <plat/devs.h>28#include <plat/iic.h>29#include <plat/sdhci.h>3031#include <mach/map.h>3233/* Following are default values for UCON, ULCON and UFCON UART registers */34#define UNIVERSAL_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \35S3C2410_UCON_RXILEVEL | \36S3C2410_UCON_TXIRQMODE | \37S3C2410_UCON_RXIRQMODE | \38S3C2410_UCON_RXFIFO_TOI | \39S3C2443_UCON_RXERR_IRQEN)4041#define UNIVERSAL_ULCON_DEFAULT S3C2410_LCON_CS84243#define UNIVERSAL_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \44S5PV210_UFCON_TXTRIG256 | \45S5PV210_UFCON_RXTRIG256)4647static struct s3c2410_uartcfg universal_uartcfgs[] __initdata = {48[0] = {49.hwport = 0,50.ucon = UNIVERSAL_UCON_DEFAULT,51.ulcon = UNIVERSAL_ULCON_DEFAULT,52.ufcon = UNIVERSAL_UFCON_DEFAULT,53},54[1] = {55.hwport = 1,56.ucon = UNIVERSAL_UCON_DEFAULT,57.ulcon = UNIVERSAL_ULCON_DEFAULT,58.ufcon = UNIVERSAL_UFCON_DEFAULT,59},60[2] = {61.hwport = 2,62.ucon = UNIVERSAL_UCON_DEFAULT,63.ulcon = UNIVERSAL_ULCON_DEFAULT,64.ufcon = UNIVERSAL_UFCON_DEFAULT,65},66[3] = {67.hwport = 3,68.ucon = UNIVERSAL_UCON_DEFAULT,69.ulcon = UNIVERSAL_ULCON_DEFAULT,70.ufcon = UNIVERSAL_UFCON_DEFAULT,71},72};7374static struct regulator_consumer_supply max8952_consumer =75REGULATOR_SUPPLY("vddarm", NULL);7677static struct max8952_platform_data universal_max8952_pdata __initdata = {78.gpio_vid0 = EXYNOS4_GPX0(3),79.gpio_vid1 = EXYNOS4_GPX0(4),80.gpio_en = -1, /* Not controllable, set "Always High" */81.default_mode = 0, /* vid0 = 0, vid1 = 0 */82.dvs_mode = { 48, 32, 28, 18 }, /* 1.25, 1.20, 1.05, 0.95V */83.sync_freq = 0, /* default: fastest */84.ramp_speed = 0, /* default: fastest */8586.reg_data = {87.constraints = {88.name = "VARM_1.2V",89.min_uV = 770000,90.max_uV = 1400000,91.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,92.always_on = 1,93.boot_on = 1,94},95.num_consumer_supplies = 1,96.consumer_supplies = &max8952_consumer,97},98};99100static struct regulator_consumer_supply lp3974_buck1_consumer =101REGULATOR_SUPPLY("vddint", NULL);102103static struct regulator_consumer_supply lp3974_buck2_consumer =104REGULATOR_SUPPLY("vddg3d", NULL);105106static struct regulator_init_data lp3974_buck1_data = {107.constraints = {108.name = "VINT_1.1V",109.min_uV = 750000,110.max_uV = 1500000,111.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |112REGULATOR_CHANGE_STATUS,113.boot_on = 1,114.state_mem = {115.disabled = 1,116},117},118.num_consumer_supplies = 1,119.consumer_supplies = &lp3974_buck1_consumer,120};121122static struct regulator_init_data lp3974_buck2_data = {123.constraints = {124.name = "VG3D_1.1V",125.min_uV = 750000,126.max_uV = 1500000,127.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |128REGULATOR_CHANGE_STATUS,129.boot_on = 1,130.state_mem = {131.disabled = 1,132},133},134.num_consumer_supplies = 1,135.consumer_supplies = &lp3974_buck2_consumer,136};137138static struct regulator_init_data lp3974_buck3_data = {139.constraints = {140.name = "VCC_1.8V",141.min_uV = 1800000,142.max_uV = 1800000,143.apply_uV = 1,144.always_on = 1,145.state_mem = {146.enabled = 1,147},148},149};150151static struct regulator_init_data lp3974_buck4_data = {152.constraints = {153.name = "VMEM_1.2V",154.min_uV = 1200000,155.max_uV = 1200000,156.valid_ops_mask = REGULATOR_CHANGE_STATUS,157.apply_uV = 1,158.state_mem = {159.disabled = 1,160},161},162};163164static struct regulator_init_data lp3974_ldo2_data = {165.constraints = {166.name = "VALIVE_1.2V",167.min_uV = 1200000,168.max_uV = 1200000,169.apply_uV = 1,170.always_on = 1,171.state_mem = {172.enabled = 1,173},174},175};176177static struct regulator_init_data lp3974_ldo3_data = {178.constraints = {179.name = "VUSB+MIPI_1.1V",180.min_uV = 1100000,181.max_uV = 1100000,182.apply_uV = 1,183.valid_ops_mask = REGULATOR_CHANGE_STATUS,184.state_mem = {185.disabled = 1,186},187},188};189190static struct regulator_init_data lp3974_ldo4_data = {191.constraints = {192.name = "VADC_3.3V",193.min_uV = 3300000,194.max_uV = 3300000,195.apply_uV = 1,196.valid_ops_mask = REGULATOR_CHANGE_STATUS,197.state_mem = {198.disabled = 1,199},200},201};202203static struct regulator_init_data lp3974_ldo5_data = {204.constraints = {205.name = "VTF_2.8V",206.min_uV = 2800000,207.max_uV = 2800000,208.apply_uV = 1,209.valid_ops_mask = REGULATOR_CHANGE_STATUS,210.state_mem = {211.disabled = 1,212},213},214};215216static struct regulator_init_data lp3974_ldo6_data = {217.constraints = {218.name = "LDO6",219.min_uV = 2000000,220.max_uV = 2000000,221.apply_uV = 1,222.valid_ops_mask = REGULATOR_CHANGE_STATUS,223.state_mem = {224.disabled = 1,225},226},227};228229static struct regulator_init_data lp3974_ldo7_data = {230.constraints = {231.name = "VLCD+VMIPI_1.8V",232.min_uV = 1800000,233.max_uV = 1800000,234.apply_uV = 1,235.valid_ops_mask = REGULATOR_CHANGE_STATUS,236.state_mem = {237.disabled = 1,238},239},240};241242static struct regulator_init_data lp3974_ldo8_data = {243.constraints = {244.name = "VUSB+VDAC_3.3V",245.min_uV = 3300000,246.max_uV = 3300000,247.apply_uV = 1,248.valid_ops_mask = REGULATOR_CHANGE_STATUS,249.state_mem = {250.disabled = 1,251},252},253};254255static struct regulator_init_data lp3974_ldo9_data = {256.constraints = {257.name = "VCC_2.8V",258.min_uV = 2800000,259.max_uV = 2800000,260.apply_uV = 1,261.always_on = 1,262.state_mem = {263.enabled = 1,264},265},266};267268static struct regulator_init_data lp3974_ldo10_data = {269.constraints = {270.name = "VPLL_1.1V",271.min_uV = 1100000,272.max_uV = 1100000,273.boot_on = 1,274.apply_uV = 1,275.valid_ops_mask = REGULATOR_CHANGE_STATUS,276.state_mem = {277.disabled = 1,278},279},280};281282static struct regulator_init_data lp3974_ldo11_data = {283.constraints = {284.name = "CAM_AF_3.3V",285.min_uV = 3300000,286.max_uV = 3300000,287.apply_uV = 1,288.valid_ops_mask = REGULATOR_CHANGE_STATUS,289.state_mem = {290.disabled = 1,291},292},293};294295static struct regulator_init_data lp3974_ldo12_data = {296.constraints = {297.name = "PS_2.8V",298.min_uV = 2800000,299.max_uV = 2800000,300.apply_uV = 1,301.valid_ops_mask = REGULATOR_CHANGE_STATUS,302.state_mem = {303.disabled = 1,304},305},306};307308static struct regulator_init_data lp3974_ldo13_data = {309.constraints = {310.name = "VHIC_1.2V",311.min_uV = 1200000,312.max_uV = 1200000,313.apply_uV = 1,314.valid_ops_mask = REGULATOR_CHANGE_STATUS,315.state_mem = {316.disabled = 1,317},318},319};320321static struct regulator_init_data lp3974_ldo14_data = {322.constraints = {323.name = "CAM_I_HOST_1.8V",324.min_uV = 1800000,325.max_uV = 1800000,326.apply_uV = 1,327.valid_ops_mask = REGULATOR_CHANGE_STATUS,328.state_mem = {329.disabled = 1,330},331},332};333334static struct regulator_init_data lp3974_ldo15_data = {335.constraints = {336.name = "CAM_S_DIG+FM33_CORE_1.2V",337.min_uV = 1200000,338.max_uV = 1200000,339.apply_uV = 1,340.valid_ops_mask = REGULATOR_CHANGE_STATUS,341.state_mem = {342.disabled = 1,343},344},345};346347static struct regulator_init_data lp3974_ldo16_data = {348.constraints = {349.name = "CAM_S_ANA_2.8V",350.min_uV = 2800000,351.max_uV = 2800000,352.apply_uV = 1,353.valid_ops_mask = REGULATOR_CHANGE_STATUS,354.state_mem = {355.disabled = 1,356},357},358};359360static struct regulator_init_data lp3974_ldo17_data = {361.constraints = {362.name = "VCC_3.0V_LCD",363.min_uV = 3000000,364.max_uV = 3000000,365.apply_uV = 1,366.valid_ops_mask = REGULATOR_CHANGE_STATUS,367.boot_on = 1,368.state_mem = {369.disabled = 1,370},371},372};373374static struct regulator_init_data lp3974_32khz_ap_data = {375.constraints = {376.name = "32KHz AP",377.always_on = 1,378.state_mem = {379.enabled = 1,380},381},382};383384static struct regulator_init_data lp3974_32khz_cp_data = {385.constraints = {386.name = "32KHz CP",387.state_mem = {388.disabled = 1,389},390},391};392393static struct regulator_init_data lp3974_vichg_data = {394.constraints = {395.name = "VICHG",396.state_mem = {397.disabled = 1,398},399},400};401402static struct regulator_init_data lp3974_esafeout1_data = {403.constraints = {404.name = "SAFEOUT1",405.valid_ops_mask = REGULATOR_CHANGE_STATUS,406.state_mem = {407.enabled = 1,408},409},410};411412static struct regulator_init_data lp3974_esafeout2_data = {413.constraints = {414.name = "SAFEOUT2",415.boot_on = 1,416.valid_ops_mask = REGULATOR_CHANGE_STATUS,417.state_mem = {418.enabled = 1,419},420},421};422423static struct max8998_regulator_data lp3974_regulators[] = {424{ MAX8998_LDO2, &lp3974_ldo2_data },425{ MAX8998_LDO3, &lp3974_ldo3_data },426{ MAX8998_LDO4, &lp3974_ldo4_data },427{ MAX8998_LDO5, &lp3974_ldo5_data },428{ MAX8998_LDO6, &lp3974_ldo6_data },429{ MAX8998_LDO7, &lp3974_ldo7_data },430{ MAX8998_LDO8, &lp3974_ldo8_data },431{ MAX8998_LDO9, &lp3974_ldo9_data },432{ MAX8998_LDO10, &lp3974_ldo10_data },433{ MAX8998_LDO11, &lp3974_ldo11_data },434{ MAX8998_LDO12, &lp3974_ldo12_data },435{ MAX8998_LDO13, &lp3974_ldo13_data },436{ MAX8998_LDO14, &lp3974_ldo14_data },437{ MAX8998_LDO15, &lp3974_ldo15_data },438{ MAX8998_LDO16, &lp3974_ldo16_data },439{ MAX8998_LDO17, &lp3974_ldo17_data },440{ MAX8998_BUCK1, &lp3974_buck1_data },441{ MAX8998_BUCK2, &lp3974_buck2_data },442{ MAX8998_BUCK3, &lp3974_buck3_data },443{ MAX8998_BUCK4, &lp3974_buck4_data },444{ MAX8998_EN32KHZ_AP, &lp3974_32khz_ap_data },445{ MAX8998_EN32KHZ_CP, &lp3974_32khz_cp_data },446{ MAX8998_ENVICHG, &lp3974_vichg_data },447{ MAX8998_ESAFEOUT1, &lp3974_esafeout1_data },448{ MAX8998_ESAFEOUT2, &lp3974_esafeout2_data },449};450451static struct max8998_platform_data universal_lp3974_pdata = {452.num_regulators = ARRAY_SIZE(lp3974_regulators),453.regulators = lp3974_regulators,454.buck1_voltage1 = 1100000, /* INT */455.buck1_voltage2 = 1000000,456.buck1_voltage3 = 1100000,457.buck1_voltage4 = 1000000,458.buck1_set1 = EXYNOS4_GPX0(5),459.buck1_set2 = EXYNOS4_GPX0(6),460.buck2_voltage1 = 1200000, /* G3D */461.buck2_voltage2 = 1100000,462.buck1_default_idx = 0,463.buck2_set3 = EXYNOS4_GPE2(0),464.buck2_default_idx = 0,465.wakeup = true,466};467468/* GPIO I2C 5 (PMIC) */469static struct i2c_board_info i2c5_devs[] __initdata = {470{471I2C_BOARD_INFO("max8952", 0xC0 >> 1),472.platform_data = &universal_max8952_pdata,473}, {474I2C_BOARD_INFO("lp3974", 0xCC >> 1),475.platform_data = &universal_lp3974_pdata,476},477};478479/* GPIO KEYS */480static struct gpio_keys_button universal_gpio_keys_tables[] = {481{482.code = KEY_VOLUMEUP,483.gpio = EXYNOS4_GPX2(0), /* XEINT16 */484.desc = "gpio-keys: KEY_VOLUMEUP",485.type = EV_KEY,486.active_low = 1,487.debounce_interval = 1,488}, {489.code = KEY_VOLUMEDOWN,490.gpio = EXYNOS4_GPX2(1), /* XEINT17 */491.desc = "gpio-keys: KEY_VOLUMEDOWN",492.type = EV_KEY,493.active_low = 1,494.debounce_interval = 1,495}, {496.code = KEY_CONFIG,497.gpio = EXYNOS4_GPX2(2), /* XEINT18 */498.desc = "gpio-keys: KEY_CONFIG",499.type = EV_KEY,500.active_low = 1,501.debounce_interval = 1,502}, {503.code = KEY_CAMERA,504.gpio = EXYNOS4_GPX2(3), /* XEINT19 */505.desc = "gpio-keys: KEY_CAMERA",506.type = EV_KEY,507.active_low = 1,508.debounce_interval = 1,509}, {510.code = KEY_OK,511.gpio = EXYNOS4_GPX3(5), /* XEINT29 */512.desc = "gpio-keys: KEY_OK",513.type = EV_KEY,514.active_low = 1,515.debounce_interval = 1,516},517};518519static struct gpio_keys_platform_data universal_gpio_keys_data = {520.buttons = universal_gpio_keys_tables,521.nbuttons = ARRAY_SIZE(universal_gpio_keys_tables),522};523524static struct platform_device universal_gpio_keys = {525.name = "gpio-keys",526.dev = {527.platform_data = &universal_gpio_keys_data,528},529};530531/* eMMC */532static struct s3c_sdhci_platdata universal_hsmmc0_data __initdata = {533.max_width = 8,534.host_caps = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |535MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |536MMC_CAP_DISABLE),537.cd_type = S3C_SDHCI_CD_PERMANENT,538.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,539};540541static struct regulator_consumer_supply mmc0_supplies[] = {542REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"),543};544545static struct regulator_init_data mmc0_fixed_voltage_init_data = {546.constraints = {547.name = "VMEM_VDD_2.8V",548.valid_ops_mask = REGULATOR_CHANGE_STATUS,549},550.num_consumer_supplies = ARRAY_SIZE(mmc0_supplies),551.consumer_supplies = mmc0_supplies,552};553554static struct fixed_voltage_config mmc0_fixed_voltage_config = {555.supply_name = "MASSMEMORY_EN",556.microvolts = 2800000,557.gpio = EXYNOS4_GPE1(3),558.enable_high = true,559.init_data = &mmc0_fixed_voltage_init_data,560};561562static struct platform_device mmc0_fixed_voltage = {563.name = "reg-fixed-voltage",564.id = 0,565.dev = {566.platform_data = &mmc0_fixed_voltage_config,567},568};569570/* SD */571static struct s3c_sdhci_platdata universal_hsmmc2_data __initdata = {572.max_width = 4,573.host_caps = MMC_CAP_4_BIT_DATA |574MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |575MMC_CAP_DISABLE,576.ext_cd_gpio = EXYNOS4_GPX3(4), /* XEINT_28 */577.ext_cd_gpio_invert = 1,578.cd_type = S3C_SDHCI_CD_GPIO,579.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,580};581582/* WiFi */583static struct s3c_sdhci_platdata universal_hsmmc3_data __initdata = {584.max_width = 4,585.host_caps = MMC_CAP_4_BIT_DATA |586MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |587MMC_CAP_DISABLE,588.cd_type = S3C_SDHCI_CD_EXTERNAL,589};590591static void __init universal_sdhci_init(void)592{593s3c_sdhci0_set_platdata(&universal_hsmmc0_data);594s3c_sdhci2_set_platdata(&universal_hsmmc2_data);595s3c_sdhci3_set_platdata(&universal_hsmmc3_data);596}597598/* I2C0 */599static struct i2c_board_info i2c0_devs[] __initdata = {600/* Camera, To be updated */601};602603/* I2C1 */604static struct i2c_board_info i2c1_devs[] __initdata = {605/* Gyro, To be updated */606};607608static struct platform_device *universal_devices[] __initdata = {609/* Samsung Platform Devices */610&mmc0_fixed_voltage,611&s3c_device_hsmmc0,612&s3c_device_hsmmc2,613&s3c_device_hsmmc3,614&s3c_device_i2c5,615616/* Universal Devices */617&universal_gpio_keys,618&s5p_device_onenand,619};620621static void __init universal_map_io(void)622{623s5p_init_io(NULL, 0, S5P_VA_CHIPID);624s3c24xx_init_clocks(24000000);625s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs));626}627628static void __init universal_machine_init(void)629{630universal_sdhci_init();631632i2c_register_board_info(0, i2c0_devs, ARRAY_SIZE(i2c0_devs));633i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));634635s3c_i2c5_set_platdata(NULL);636i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs));637638/* Last */639platform_add_devices(universal_devices, ARRAY_SIZE(universal_devices));640}641642MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")643/* Maintainer: Kyungmin Park <[email protected]> */644.boot_params = S5P_PA_SDRAM + 0x100,645.init_irq = exynos4_init_irq,646.map_io = universal_map_io,647.init_machine = universal_machine_init,648.timer = &exynos4_timer,649MACHINE_END650651652